JP2017034212A - Semiconductor device, method of manufacturing the same, and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing deterioration in withstanding voltage caused by chipping of the semiconductor device, and of performing inspection of voids.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1 that includes an active region 101 and a termination region 102 surrounding the active region 101, on its principle surface; a thermosetting adhesive layer 10 that covers at least the termination region 102; and a flat plate-like insulation film 9 adhered to the termination region 102 via the adhesive layer 10. The adhesive layer 10 extends to the outside of the principle surface, and covers at least a part of a lateral face of the semiconductor substrate 1.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device.

  An insulated gate bipolar transistor (hereinafter referred to as “IGBT” as appropriate) is a switching element that controls a current flowing between a collector and an emitter by applying a voltage to a gate electrode. The power that can be controlled by the IGBT is wide, from several tens of watts to several hundred thousand watts, and the switching frequency of the IGBT is also wide, from several tens of hertz to over one hundred kilohertz. Therefore, IGBTs are used from small power devices such as air conditioners to high power devices such as railways and steelworks.

  The IGBT includes an active region through which a current flows and a termination region. The termination region structure relaxes the electric field strength at the end of the chip and maintains a high avalanche breakdown (dielectric breakdown) voltage. The width of the termination region that employs a guard ring or a field plate (termination width) is generally wider as a high-voltage element. For example, it is shown that the termination width of the 6.5 kV withstand voltage element is 2.5 mm, which is about twice as long as that of the 3.3 kV element. For this reason, a higher breakdown voltage element is required to reduce the chip cost by reducing the termination width. It has been shown that, for example, the termination width can be reduced by 50% by an LNFLR (Linearly-Narrowed Field Limiting Ring, hereinafter referred to as “LNFLR” as appropriate) structure.

  When the termination width is reduced without changing the holding voltage, the electric field strength on the chip surface increases, so that the risk of creeping discharge increases. According to Paschen's law, the spark discharge voltage in an equal electric field is given as a function of the product of the gas pressure and the gap length. Since the surface of the termination region is often configured as an unequal electric field having a spark discharge voltage lower than that of the equal electric field, the risk of discharge due to termination width reduction (gap length reduction) is further increased.

  In addition, when conductive foreign matter such as fine shavings or metal powder generated when cutting an IGBT chip from one wafer rides on the termination region, the electric field strength is further increased at the end of the foreign matter. For this reason, there is a concern about the occurrence of discharge due to foreign matter.

  In connection with the suppression of creeping discharge, Patent Document 1 discloses a termination structure (FIG. 23), which covers a high-voltage semiconductor element and a termination region provided on the semiconductor substrate 1, and covers the junction termination region. A semiconductor device is described that includes an insulating frame 35 provided on an outer peripheral portion of the semiconductor substrate. By adopting such a structure, the above-described insulating frame 35 protrudes outward from the chip end, so that the creepage distance between the chip end and the main electrode is extended, and the discharge tolerance can be increased. In addition, even if conductive foreign matter adheres to the insulating frame 35, the electric field strength at the foreign matter end on the chip surface can be reduced as compared with an element without the insulating frame 35, thereby improving the reliability against discharge. Can do.

JP 2000-183282 A

  However, since the insulating frame 35 surrounding the end portion of the chip from the top surface to the side surface as in Patent Document 1 has mechanical strength, when the chip is brought into contact with the chip due to misalignment when the chip is fitted into the insulating frame 35, silicon is used. There is a concern of causing pressure-resistant deterioration due to chipping.

  Furthermore, there is a concern that gaps or voids may be generated in the adhesive layer 34 between the insulating frame 35 and the termination structure due to mechanical tolerances of the insulating frame 35 in contact with the top and side surfaces of the chip. Since voids cause insulation deterioration due to partial discharge, it is necessary to eliminate voids by inspection. However, since the insulating frame 35 that secures mechanical strength is thick and does not transmit light, it is difficult to visually inspect the void using a stereomicroscope.

  In order to solve the above-described problem, a semiconductor device according to one embodiment of the present invention includes a semiconductor substrate including an active region and a termination region surrounding the active region on a main surface, and a heat that covers at least the termination region. A curable adhesive layer and a flat insulating film bonded to the termination region via the adhesive layer, the adhesive layer extending to the outside of the main surface, Cover at least part of the side.

  It suppresses the breakdown voltage degradation due to chipping of the semiconductor device and enables inspection of voids.

3 is a plan view of the diode according to Embodiment 1. FIG. 2 is a cross-sectional view of the diode according to Embodiment 1. FIG. The electric field calculation model of a termination area | region in the case of being covered with the insulator is shown. An electric field calculation model of a termination region when not covered with an insulator is shown. The calculation result of the case where it is covered with an insulator and the case where it is not covered with an insulator is shown. An actual measurement result of the relationship between the size of the foreign matter and the pressure resistance is shown. It is sectional drawing which shows state S1 in a manufacturing process. It is sectional drawing which shows state S2 in a manufacturing process. It is sectional drawing which shows state S3 in a manufacturing process. It is sectional drawing which shows state S4 in a manufacturing process. It is sectional drawing which shows state S5 in a manufacturing process. It is sectional drawing which shows state S6 in a manufacturing process. It is sectional drawing which shows state S7 in a manufacturing process. It is sectional drawing which shows state S8 in a manufacturing process. It is sectional drawing which shows state S9 in a manufacturing process. It is sectional drawing which shows state S10 in a manufacturing process. 6 is a cross-sectional view of a diode according to Embodiment 2. FIG. 6 is a cross-sectional view of a diode according to Embodiment 3. FIG. 6 is a cross-sectional view of an IGBT according to a fourth embodiment. 6 shows a circuit configuration of an MMC according to a fifth embodiment. 6 shows a circuit configuration of a unit cell according to a fifth embodiment. The circuit structure of the inverter circuit which concerns on Embodiment 6 is shown. It is sectional drawing of the termination structure which concerns on patent document 1. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
(Embodiment 1)

  FIG. 1 is a plan view of the diode according to the first embodiment. FIG. 2 is a cross-sectional view of the diode according to the first embodiment. This sectional view shows a section taken along the line II-II in FIG.

  The diode of the present embodiment includes an active region 101 provided on the semiconductor substrate 1 and a termination region 102 formed so as to surround the active region 101. The main surface (pattern surface, anode side surface) of the active region 101 is covered with the anode electrode 3. An insulating film 9 is provided on the main surface of the termination region 102 via a thermosetting adhesive layer 10. Further, the thermosetting adhesive layer 10 is formed outside the outer shape (Si chip end portion 13) of the semiconductor substrate 1. Furthermore, the thermosetting adhesive layer 10 alone covers the outer peripheral end (upper side surface) of the termination region 102, and extends outside the outer shape of the semiconductor substrate 1. The termination region 102 covers the plurality of guard rings 4, the plurality of insulating films 7 provided therebetween, the plurality of field plate electrodes 6 provided on the plurality of guard rings 4, respectively. And a passivation film 8.

  In the present embodiment, since the adhesive layer 10 cured by heat covers the terminal end portion (outer peripheral end portion) of the termination region 102, deterioration of pressure resistance due to chipping is suppressed. That is, it is possible to prevent the breakdown voltage degradation due to the end portion of the termination region 102 being chipped and the breakdown voltage degradation due to the chipped piece being placed on the termination region 102. Further, with respect to the side surface of the semiconductor substrate 1, the thermosetting adhesive layer 10 alone covers the termination region, and the adhesive layer 10 transmits light.

  If the insulator covering the termination region 102 is too thin, the electric field strength between the field plate electrodes 6 is locally increased. By providing the insulating film 9 on the termination region 102 via the thermosetting adhesive layer 10, the film thickness of the insulator is increased and the risk of discharge with respect to foreign matters is reduced.

  In addition, since the potential from the lower surface to the side surface of the semiconductor substrate 1 is the same potential, the adhesive layer 10 covers the region from the termination region 102 to the upper portion of the side surface of the semiconductor substrate 1, so that the creeping distance can be extended and the creeping discharge is generated. Can be suppressed.

  The discharge risk for foreign objects will be described in detail below.

  FIG. 3 shows an electric field calculation model of the termination region when covered with an insulator. FIG. 4 shows an electric field calculation model of the termination region when not covered with an insulator.

  The termination region AA ′ includes a guard ring 4, a field plate electrode 6, and a passivation film 8. The electric field calculation model of the termination area AA ′ when covered with an insulator is a structure in which the total film thickness of the thermosetting adhesive layer 10 and the insulating film 9 is 100 μm as the insulator film. The electric field strength of the surface BB ′ on which the conductive foreign material 33 having a width of 200 μm was placed was evaluated. The electric field calculation model of the termination area AA ′ when not covered with an insulator has a structure in which the insulating film 9 and the thermosetting adhesive layer 10 are removed from the electric field calculation model when covered with an insulator. The electric field strength of the surface CC ′ on which the conductive foreign material 33 having a width of 200 μm was placed was evaluated.

  FIG. 5 shows the calculation results when the case is covered with an insulator and when the case is not covered with an insulator.

  In this figure, the horizontal axis represents the horizontal position [μm] in the termination area AA ′, and the vertical axis represents the electric field strength [kV / cm]. Here, the conductive foreign material 33 is provided between the horizontal positions 200 to 400 μm. In the electric field strength distribution of the electric field strength model (with an insulator) when covered with an insulator, the electric field strength is strong at the end of the conductive foreign material 33 but is not covered with an insulator (no insulator) It is suppressed to 1/10 or less as compared with the electric field strength of the electric field strength model.

  FIG. 6 shows an actual measurement result of the relationship between the size of the foreign matter and the pressure resistance.

  In this figure, the horizontal axis represents the size of foreign matter (arbitrary unit), and the vertical axis represents the breakdown voltage (arbitrary unit) of the diode. Moreover, this figure shows each measurement result of the diode when not covered with an insulator when the diode is covered with an insulator. When the size of the foreign material exceeds a certain value, the withstand voltage of the diode when not covered with the insulator starts to decrease. However, with a diode covered with an insulator, no breakdown voltage degradation occurs, and a constant breakdown voltage is maintained regardless of foreign matter.

  Next, a manufacturing process of the diode of the first embodiment will be described.

  FIG. 7 is a cross-sectional view showing a state S1 during the manufacturing process.

  The semiconductor substrate 1 is an n-type semiconductor substrate. First, in this manufacturing process, an n-type cathode layer 11 having a thickness of, for example, 20 μm is formed on the cathode-side surface (surface without pattern) which is the back surface of the semiconductor substrate 1. Thereafter, in this manufacturing process, an insulating film 7 which is an oxide film formed by thermal oxidation is formed on the anode side surface (main surface) by photolithography and etching (S1).

  FIG. 8 is a cross-sectional view showing a state S2 during the manufacturing process.

Subsequently, in this manufacturing process, a resist is applied to the main surface, and this is patterned to form a resist mask 14a on the channel stopper formation region. After forming the resist mask 14a, the manufacturing process performs ion implantation 15a with a dose of 5 × 10 ¹² to 1 × 10 ¹⁵ cm ⁻² , for example, from the anode side (S2).

  FIG. 9 is a cross-sectional view showing a state S3 during the manufacturing process.

Next, in this manufacturing process, after removing the resist mask 14a, a resist is again applied to the surface of the semiconductor substrate 1, and this is patterned to form a resist mask 14b having an opening on the channel stopper formation region. . In this manufacturing process, for example, phosphorus is ion-implanted 15b with a dose of 1 × 10 ¹⁵ cm ⁻² (S3).

  FIG. 10 is a cross-sectional view showing a state S4 during the manufacturing process.

  Next, in this manufacturing process, after removing the resist mask 14b, an annealing process is performed to activate the impurities implanted by the ion implantations 15a and 15b, whereby the p-type diffusion layer 2, the guard ring 4, and the channel stopper layer are activated. 5 is formed (S4).

  FIG. 11 is a cross-sectional view showing a state S5 during the manufacturing process.

  Next, in this manufacturing process, for example, an AlSi electrode 16 is formed on the anode side surface of the semiconductor substrate 1 by a sputtering method (S5).

  FIG. 12 is a cross-sectional view showing a state S6 during the manufacturing process.

  Next, in this manufacturing process, the anode electrode 3 and the field plate electrode 6 are formed by photolithography and etching processing on the AlSi electrode 16 (S6).

  FIG. 13 is a cross-sectional view showing a state S7 during the manufacturing process.

  After the anode electrode 3 is formed, this manufacturing process forms a passivation film 8 with a thickness of 1 μm to 10 μm on the main surfaces of the anode electrode 3 and the field plate electrode 6 (S7).

  FIG. 14 is a cross-sectional view showing a state S8 during the manufacturing process.

  Next, in this manufacturing process, a photoresist is applied to the main surface, and this is patterned to form a resist mask 14 having an opening on the anode electrode 3 (S8).

  FIG. 15 is a cross-sectional view showing a state S9 during the manufacturing process.

  In this manufacturing process, for example, a part of the anode electrode 3 is exposed by performing a wet etching process. In this manufacturing process, after the cathode electrode 12 is formed on the back surface, the adhesive 10a before curing is discharged to a predetermined position on the passivation film 8 by a predetermined amount with a liquid quantitative discharge device (S9). The adhesive 10a includes, for example, silicone.

  FIG. 16 is a cross-sectional view showing a state S10 during the manufacturing process.

  An upper step recess for fitting the insulating film 9 is formed at the center of the upper surface of the lower jig 17b, and a lower step recess for fitting the semiconductor substrate 1 is formed at a part of the bottom surface of the upper step recess. The size of the opening of the upper recess is a size into which the insulating film 9 is fitted. The size of the opening of the lower recess is a size into which the semiconductor substrate 1 is fitted. That is, the relative position between the semiconductor substrate 1 and the insulating film 9 is determined by the lower jig 17b. In this manufacturing process, in order to align the semiconductor substrate 1 and the insulating film 9, the semiconductor substrate 1 is set in the lower recess of the positioning lower jig 17b, and the insulating film 9 is set in the upper recess.

  After the semiconductor substrate 1 and the insulating film 9 are set on the lower jig 17b, this manufacturing process places the upper jig 17a on the lower jig 17b. The lower surface of the upper jig 17a is provided with a convex portion having a horizontal size smaller than the upper concave portion, and the film thickness of the adhesive 10a before being crushed by the convex portion is determined according to the height of the convex portion. Is done. If the adhesive 10a reaches the cathode electrode 12, when the cathode electrode 12 is connected to the pattern on the substrate by soldering after the diode is completed, a contact failure between the cathode electrode 12 and the pattern occurs. There is. Therefore, by preventing the adhesive 10a protruding to the outer peripheral portion of the semiconductor substrate 1 from reaching the cathode electrode 12, it is possible to suppress a decrease in yield in subsequent solder connection. Further, the side surface of the adhesive 10a on the active region 101 side is flush with the side surface of the insulating film 9 on the active region 101 side, or is located outside the side surface (S10). Such a state of the adhesive 10a can be realized by adjusting the position and amount of discharge by the liquid dispensing apparatus in the state S9.

  It should be noted that a part of the adhesive 10 a may be pushed outside the main surface of the semiconductor substrate 1 by sandwiching the adhesive 10 a between the termination region 102 and the insulating film 9 using another jig.

  Thereafter, in this manufacturing process, after setting the upper jig 17a, the jig set in a curing furnace at about 150 ° C. is put for about 1 hour to cure the adhesive 10a, whereby the diode of the first embodiment is completed.

  According to the above-described diode of the first embodiment, the hardened adhesive layer 10 covers and protects the termination region termination portion, so that the breakdown voltage degradation due to chipping is suppressed. Moreover, since the risk of contacting the semiconductor substrate 1 is low even if the positional deviation of the insulating film 9 occurs during the manufacturing process, the occurrence of chipping during the manufacturing process can be suppressed. Furthermore, with respect to the side surface of the semiconductor substrate 1, since the thermosetting adhesive layer 10 alone covers the termination region alone, a void inspection by visual inspection is possible.

  In addition, by making the total of the film thickness 201 of the adhesive layer 10 and the film thickness 202 of the insulating film 9 at least 100 μm or more, an increase in the electric field strength on the chip surface due to foreign substances can be suppressed, and the discharge risk is reduced. be able to.

  Further, as shown in the plan view of the diode of the present embodiment, the outer shape of the insulating film 9 may be larger than the outer shape of the semiconductor substrate 1 in the direction parallel to the main surface of the semiconductor substrate 1. It may be larger than the outer shape of the curable adhesive layer 10. By setting it as such a structure, the creeping distance between the edge part of the semiconductor substrate 1 and the anode electrode 3 can further be extended, and creeping discharge can be suppressed more.

  Moreover, the insulating film 9 has flexibility. Thereby, even if the insulating film 9 contacts the semiconductor substrate 1 during a manufacturing process, chipping can be suppressed.

The insulating film 9 may be a polyimide resin that transmits light. By adopting such a structure, it becomes possible to visually inspect the voids in the thermosetting adhesive layer 10 between the passivation film 8 and the insulating film 9, making the inspection easy and the final. Product reliability can be improved.
(Embodiment 2)

  FIG. 17 is a cross-sectional view of the diode according to the second embodiment.

  The diode of the second embodiment includes an active region 101 and a termination region 102 formed so as to surround the active region 101, as in the first embodiment. Further, the cathode electrode 12 provided on the back surface of the semiconductor substrate 1 is connected to the wiring pattern 19 on the insulating substrate 20 through the solder layer 18. Furthermore, an insulating film 9 is provided on the main surface of the termination region 102 via a thermosetting adhesive layer 10. Further, the thermosetting adhesive layer 10 covers the entire side surface of the semiconductor substrate 1 alone and extends outside the outer shape of the semiconductor substrate 1.

  In the manufacturing process of the second embodiment, the cathode electrode 12 is connected to the wiring pattern 19 on the insulating substrate 20 via the solder layer 18, and then the adhesive 10a and the insulating film 9 are placed on the insulating film 9 and the semiconductor. By sandwiching the adhesive 10 a with the substrate 10, the adhesive 10 protrudes from the side surface of the semiconductor substrate 1. At this time, since the back surface is covered with the insulating substrate 20, the adhesive 10 does not go from the side surface of the semiconductor substrate 10 to the back surface and does not affect the cathode electrode 12.

With the above-described structure, the side surface of the semiconductor substrate 1 is completely protected by the thermosetting adhesive layer 10, so that the risk of chipping can be further reduced.
(Embodiment 3)

  FIG. 18 is a cross-sectional view of the diode according to the third embodiment.

  Similar to the first embodiment, the diode of the present embodiment includes an active region 101 provided on the semiconductor substrate 1 and a termination region 102 formed so as to surround the active region 101. Furthermore, an insulating film 9 is provided on the main surface of the termination region 102 via a thermosetting adhesive layer 10. Further, the thermosetting adhesive layer 10 covers the outer peripheral end of the termination region 102 alone and extends outside the outer shape of the semiconductor substrate 1. Further, the position where the electric field intensity is maximum on the main surface of the termination region 102 is not on the outer peripheral edge of the semiconductor substrate 1 but on the inner side of the outer peripheral edge of the semiconductor substrate 1.

  By setting it as the structure mentioned above, since the increase in the electric field strength in the area | region 301 which is not covered with the insulating film 9 can be suppressed, the risk of discharge can be reduced.

  The diode of each of the embodiments described above has a structure in which the side surface (region 301) of the semiconductor substrate 1 is not covered with the insulating film 9 in order to prevent chipping due to the insulating frame as in Patent Document 1. For this reason, the structure of the diode of each of the above-described embodiments is likely to cause discharge when the electric field is concentrated in the region 301, as compared with the structure covered with the insulating frame.

  The electric field distribution in the termination region 102 can be controlled by the structure. By separating the position where the electric field strength becomes maximum from the outer peripheral end of the semiconductor substrate 1 inward, the electric field strength of the region 301 not covered with the insulating film 9 can be reduced. For example, the termination region 102 is spaced from the p-type diffusion layer 2 formed in the active region 101 and surrounds the p-type diffusion layer 2, and the guard ring 4 is separated from the guard ring 4 by a distance. By including a channel stopper layer 5 formed at the end of the semiconductor substrate 1 so as to surround the ring 4 and the p-type diffusion layer 2 and a field plate electrode 6 connected to the guard ring 4 and the channel stopper layer 5, Electric field strength can be controlled.

  In order to extend the depletion layer on the main surface of the termination region 102, the distance between the guard rings 4 is shorter as it is closer to the active region 101. The shorter the gap between the guard rings 4, the weaker the electric field strength. For this reason, in the termination region 102 before the interval is changed, the electric field strength decreases as it approaches the active region 101, and the electric field strength increases as it approaches the end of the semiconductor substrate 1.

In the present embodiment, the electric field strength is controlled by changing the interval between the plurality of guard rings 4. The equipotential lines in the termination region 102 are gathered between the adjacent guard rings 4 (field plate electrodes 6) when the plurality of field plate electrodes 6 are arranged. The higher the density of equipotential lines, the higher the electric field strength. Therefore, the closer to the active region 101, the shorter the interval between the guard rings 4 and the constant interval between the field plate electrodes 6. The interval between the guard rings 4 is increased, and the interval between the guard rings 4 near the end of the termination region 102 is decreased. By changing the distance between the guard rings 4 as described above, the position where the electric field intensity becomes maximum can be moved to the inside of the semiconductor substrate 1. For example, the position where the electric field intensity becomes maximum can be moved inward from the channel stopper layer 5 by changing the interval. Thereby, the electric field strength in the edge part of the semiconductor substrate 1 can be reduced and discharge can be suppressed.
(Embodiment 4)

  FIG. 19 is a cross-sectional view of an IGBT according to the fourth embodiment.

  The IGBT of the present embodiment includes an active region 101 and a termination region 102 formed so as to surround the active region 101. Further, the active region 101 includes a p-type base layer 21 selectively formed on the main surface of the semiconductor substrate 1, an n-type source layer 22 formed on the surface of the p-type base layer 21, and a p-type base layer 21. And an emitter electrode 25 electrically connected to the n-type source layer 22 and formed on the surface of the n-type source layer 22, and a surface of the p-type base layer 21 sandwiched between the semiconductor substrate 1 and the n-type source layer 22. Gate electrode 24 formed through gate oxide film 23, n-type buffer layer 26 formed on the opposite side of p-type base layer 21 with respect to semiconductor substrate 1, and part of the surface of n-type buffer layer 26 And a collector electrode 28 formed so as to be in contact with the p-type emitter layer 27 by vapor deposition or the like. Further, the termination region includes a guard ring 4 formed so as to be spaced from and surrounding the p-type base layer 21, a distance from the guard ring 4, and the guard ring 4 and the p-type base layer 21. A channel stopper layer 5 formed at the end of the chip so as to surround, a field plate electrode 6 connected to the guard ring 4 and the channel stopper layer 5, and a passivation film 8 formed on the main surface of the field plate electrode 6. Including. Further, an insulating film 9 is provided on the main surface of the termination region 102 via a thermosetting adhesive layer 10. Further, the thermosetting adhesive layer 10 covers the outer peripheral end of the termination region 102 alone and extends outside the outer shape of the semiconductor substrate 1.

  With such a structure, even in the IGBT, the cured adhesive layer 10 covers and protects the end portion of the termination region 102, so that deterioration in breakdown voltage due to chipping is suppressed. Further, since the thermosetting adhesive layer 10 covers the side surface of the termination region 102 alone, a void inspection can be made by visual observation. Furthermore, based on the electric field strength of silicon dielectric breakdown, the total of the film thickness 201 of the thermosetting adhesive layer and the film thickness 202 of the insulating film is 100 μm or more, so that The increase can be suppressed, and the discharge risk can be reduced.

The semiconductor device in each of the above embodiments desirably has the following configuration.
(1) The maximum value of the electric field strength is not located at the outer peripheral end of the semiconductor substrate 1.
(2) The outer shape of the insulating film 9 should be larger than the outer shape of the semiconductor substrate 1.
(3) The sum total of the film thickness of the adhesive layer 10 and the film thickness of the insulating film 9 is 100 μm or more.
(4) The insulating film 9 is a polyimide resin excellent in light transmittance.
(Embodiment 5)

  Next, a power conversion device that employs at least one of the IGBT and the diode according to the above-described embodiment will be described.

  FIG. 20 shows a circuit configuration of the MMC according to the fifth embodiment.

  The MMC (Modular Multilevel Converter) 29 includes a U-phase leg 801, a V-phase leg 802, and a W-phase leg 803 in which a plurality of unit cells 806 are connected in series.

  Three-phase AC power (voltage) is input or output at terminals (AC terminals) 804U, 804V, and 804W located at intermediate points of the U-phase leg 801, the V-phase leg 802, and the W-phase leg 803, respectively. One terminal of the U-phase leg 801, the V-phase leg 802, and the W-phase leg 803 is commonly connected to a terminal (DC terminal) 805P, and the other terminal is commonly connected to a terminal (DC terminal) 805N. . DC power (voltage) is output or input at the terminals 805P and 805N.

  The MMC 29 can convert AC power (voltage) to DC power (voltage) or DC power (voltage) by appropriately controlling the unit cells 806 of the U-phase leg 801, the V-phase leg 802, and the W-phase leg 803. It is a power converter that can also convert AC voltage (voltage) into AC power (voltage).

  FIG. 21 shows a circuit configuration of a unit cell according to the fifth embodiment.

  Unit cell 806 includes two IGBTs 808 connected in series, and a capacitor 810 connected to both ends of the series circuit. In addition, a free-wheeling diode 809 is connected in antiparallel between the emitter and collector of each IGBT 808.

  Further, the midpoint of the two IGBTs 808 connected in series is taken out to the terminal 811A, and one end of the capacitor 810 is taken out to the terminal 811B. In addition, electric power (electric energy, voltage) is input / output at these two terminals 811A and 811B.

  The gate terminal of each IGBT 808 is controlled to be turned on and off (ON-OFF) by each gate drive circuit 807 that receives a control signal from a control unit (not shown). The control unit controls the on / off (ON-OFF) of each IGBT of the plurality of unit cells 806 in the MMC 29 so as to be compatible with each operation. The MMC 29 has a breakdown voltage higher than that of the unit cell 806 by connecting a plurality of unit cells 806 in series.

By applying any of the above-described embodiments to at least one of the diode 809 and the IGBT 808, high reliability of the power conversion device that is the MMC 29 can be realized.
(Embodiment 6)

  Next, another circuit example of the power conversion device employing at least one of the IGBT and the diode according to the above-described embodiment will be described.

  FIG. 22 shows a circuit configuration of the inverter circuit according to the sixth embodiment.

  Inverter circuit 30 includes U-phase, V-phase, and W-phase legs including two IGBTs 908 each connected in series. Each of the U-phase, V-phase, and W-phase legs is connected between the DC terminals 904P and 904N. Three-phase AC power (voltage) terminals 905U, 905V, and 905W are taken out from the middle of the two IGBTs 908 in the U-phase, V-phase, and W-phase legs, respectively.

  In addition, a free-wheeling diode 909 is connected in antiparallel between the emitter and collector of each IGBT 908.

  The gate terminal of each IGBT 908 is controlled to be turned on and off (ON-OFF) by each gate drive circuit 907 that receives a control signal from a control unit (not shown). The control unit controls on and off (ON-OFF) of the plurality of IGBTs 908 in the inverter circuit 30 so as to be compatible with the operation as the inverter circuit 30.

  By applying any of the above-described embodiments to at least one of the diode 909 and the IGBT 908, high reliability of the power conversion device that is the inverter circuit 30 can be realized.

  The power conversion device in each of the above embodiments includes a pair of input terminals (DC terminals), a plurality of series connection circuits (legs) connected between the input terminals, and each series connection point of the plurality of series connection circuits. A plurality of output terminals (AC terminals) to be connected. The number of series connection circuits may be one. Each series connection circuit includes a plurality of semiconductor switching elements (for example, IGBTs) connected in series. A plurality of semiconductor switching elements are controlled and turned on / off to convert electric power. Each of the plurality of semiconductor switching elements is a semiconductor device having the configuration shown in the first to fourth embodiments.

  The present invention has been specifically described above based on the embodiments of the invention. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the fourth embodiment, the gate shape on the emitter side may be a trench type instead of the planar type, and the gates may be arranged in a stripe shape or a mesh shape.

  Although it has been described that the present invention is applied to the diode in the first embodiment and the IGBT in the fourth embodiment, the diode to which the present invention is applied and the IGBT may be arranged in the same chip.

  The semiconductor material of the semiconductor substrate 1 may be silicon or silicon carbide. The semiconductor substrate 1 has been described as being n-type (n-type), but may be a p-type (p-type) substrate. When a p-type (p-type) substrate is used, the p-type and n-type materials of the related semiconductor members are reversed.

  As an impurity element diffusing into a semiconductor, boron is shown as an example for a p-type semiconductor and phosphorus is used as an n-type semiconductor. However, another trivalent element is used instead of boron, and another pentavalent element is used instead of phosphorus. May be used.

  Even if the semiconductor chip which is at least one of the IGBT and the diode of each of the above embodiments is mounted by another mounting method, there is an effect of reducing the risk of occurrence of discharge. Other mounting methods include, for example, soldering a semiconductor chip to an insulating substrate, electrically connecting by wire bonding, and electrically connecting by applying pressure on the top and bottom of the gel-sealed module or semiconductor chip, and insulating gas. A pressure-welded package or the like in which By applying the structure shown in each of the above embodiments to such a module, the gel can be deleted. By removing the gel, it is possible to prevent the gel from expanding and exploding.

  Although the case where the semiconductor device (diode, IGBT) of another embodiment is used for the MMC 29 of the fifth embodiment or the inverter circuit 30 of the sixth embodiment has been described, the semiconductor device to which the present invention is applied is converted into a converter. The same effect can be obtained when used for other power conversion devices such as a chopper and a chopper.

  1: semiconductor substrate, 2: p-type diffusion layer, 3: anode electrode, 4: guard ring, 5: channel stopper layer, 6: field plate electrode, 7: insulating film, 8: passivation film, 9: insulating film, 10: thermosetting adhesive layer, 10a: adhesive before curing, 11: n-type cathode layer, 12: cathode electrode, 13: edge of Si chip, 14: resist mask 15: ion implantation, 16: AlSi electrode 17a: upper jig, 17b: lower jig, 18: solder layer, 19: wiring pattern, 20: insulating substrate, 21: p-type base layer, 22: n-type source layer, 23: gate oxide film, 24: gate electrode 25: emitter electrode, 26: n-type buffer layer, 27: p-type emitter layer, 28: collector electrode, 29: MMC, 30 Inverter circuit, 33: foreign matter, 34: adhesive layer, 35: insulating frame, 101: active region, 102: termination region, 201: film thickness of thermosetting adhesive layer, 202: film thickness of insulating film, 301: Region not covered with insulating film, 801: U-phase leg, 802: V-phase leg, 803: W-phase leg, 804U, 804V, 804W, 905U, 905V, 905W: AC terminal, 805N, 805P, 904N, 904P DC terminal, 806: unit cell, 807, 907: gate drive circuit, 808, 908: IGBT, 809, 909: diode, 810: capacitor

Claims (11)

On the main surface, a semiconductor substrate including an active region and a termination region surrounding the active region;
A thermosetting adhesive layer covering at least the termination region;
A flat insulating film adhered to the termination region via the adhesive layer;
With
The adhesive layer extends to the outside of the main surface and covers at least a part of a side surface of the semiconductor substrate;
Semiconductor device. In a direction parallel to the main surface of the semiconductor substrate, the outer shape of the insulating film is larger than the outer shape of the main surface of the semiconductor substrate.
The semiconductor device according to claim 1. The total of the film thickness of the adhesive layer and the film thickness of the insulating film is 100 μm or more.
The semiconductor device according to claim 2. The insulating film has flexibility.
The semiconductor device according to claim 3. The insulating film is a polyimide resin and transmits light.
The semiconductor device according to claim 4. The semiconductor substrate has a first conductivity type,
A second conductivity type diffusion layer is formed in the active region;
The termination region is
A plurality of guard rings surrounding the second conductivity type diffusion layer and spaced apart from the second conductivity type diffusion layer;
A channel stopper that surrounds the plurality of guard rings located at an end of the semiconductor substrate and separated from the plurality of guard rings;
A plurality of field plate electrodes respectively connected to the plurality of guard rings and the channel stopper;
including,
The semiconductor device according to claim 1. The position where the electric field strength is maximum in the termination region is inside the channel stopper,
The semiconductor device according to claim 6. The adhesive layer is separated from the back surface of the semiconductor substrate,
The semiconductor device according to claim 1. The back surface of the semiconductor substrate is connected to a wiring pattern on the insulating substrate via a solder layer,
The adhesive layer covers a side surface of the semiconductor substrate;
The semiconductor device according to claim 1. A method for manufacturing a semiconductor device, comprising:
On the main surface, a thermosetting adhesive is placed on the termination region for a semiconductor substrate including an active region and a termination region surrounding the active region,
Extruding a part of the adhesive to the outside of the main surface by sandwiching the adhesive in a flat insulating film and the termination region,
Curing the adhesive by heat;
Manufacturing method. A pair of DC terminals;
A series connection circuit including a plurality of semiconductor switching elements connected in series and connected between the pair of DC terminals;
An AC terminal connected between two semiconductor switching elements in the series connection circuit;
With
The semiconductor switching element is
On the main surface, a semiconductor substrate including an active region and a termination region surrounding the active region;
A thermosetting adhesive layer covering at least the termination region;
A flat insulating film adhered to the termination region via the adhesive layer;
Including
The adhesive layer extends to the outside of the main surface and covers at least a part of a side surface of the semiconductor substrate;
Power conversion device.

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