WO1996029744A1

WO1996029744A1 - Planar semiconductor device, its manufacturing method, and power converter

Info

Publication number: WO1996029744A1
Application number: PCT/JP1995/000478
Authority: WO
Inventors: Susumu Murakami; Yasumichi Yasuda; Mutsuhiro Mori; Hideo Kobayashi
Original assignee: Hitachi, Ltd.
Priority date: 1995-03-17
Filing date: 1995-03-17
Publication date: 1996-09-26

Abstract

An electric field limiting ring region and n+ type ring region surround a p-type semiconductor region forming a main p-n junction are provided. One main electrode is in contact with the p-type semiconductor region. A field plate is formed in the electric field limiting ring region. An auxiliary electrode is formed in the n+ type ring region. A thick insulating film is formed on an auxiliary p-n junction composed of the electric field limiting ring region and an n-type semiconductor region. The one main electrode and field plate cover the surfaces of the n-type semiconductor region and auxiliary p-n junction.

Description

Specification

TECHNICAL FIELD The present invention relates to a planar semiconductor device, a method of manufacturing the same, and a power converter.

The present invention relates to a semiconductor device, and more particularly to a high withstand voltage planar semiconductor device having high withstand voltage and high reliability.

Background art

Various techniques have been conventionally proposed to increase the breakdown voltage of a planar semiconductor device in which a ρ η junction is exposed on the main surface of a semiconductor substrate.

For example, a technique described in Japanese Patent Publication No. 1-20549 is known. In this prior art, a plurality of electric field limiting ring regions are provided to annularly surround a planar type main junction, and an electrode in contact with the electric field limiting ring region is formed on an insulating film formed on the surface of a semiconductor substrate. At a distance from the main joint. As a result, a so-called field plate effect is given to the electric-field-limited ring region. Further, a final insulating protective film is formed so as to cover the electrodes. According to this conventional technology, a high breakdown voltage that cannot be achieved only by the electric field limiting ring region is realized by adding a field plate to the electric field limiting ring region to reduce the electric field on the semiconductor surface. You. In addition, the final insulating protective film prevents discharge between the field plates, and the blocking characteristics are improved from a soft waveform to a hard waveform. For this reason, the yield of the blocking characteristics is improved.

Further, as a technique utilizing the same field plate effect as the above-mentioned prior art, a technique described in Japanese Patent Application Laid-Open No. 63-38259 is known. In this conventional technique, an insulating film interposed between a field plate and the surface of a semiconductor substrate is provided near an outer periphery of a contact window in an electric field limiting ring region. / JP95 / 00478

In this case, the withstand voltage is improved by being formed thinner than the vicinity of the outer periphery of the field plate.

Further, as another conventional technique for increasing the breakdown voltage of a planar semiconductor device, a technique described in Japanese Patent Publication No. 3-58185 is known. In this prior art, a plurality of electric field limiting ring regions are provided to annularly surround a planar type main junction, and electrodes in contact with the electric field limiting ring region are formed on an insulating film formed on the surface of a semiconductor substrate. It extends in the direction approaching. That is, a field plate effect opposite to the technique described in the above-mentioned Japanese Patent Publication No. 1-20549 is added to the electric field limiting ring region. According to the prior art, the influence of an external atmosphere such as electric charge and moisture in plastic and resin is reduced. For example, when charges having a negative polarity are accumulated on the surface of the η-type semiconductor region of the substrate, the η-type semiconductor surface is prevented from being inverted and the blocking characteristics are prevented from deteriorating.

The technology described in Japanese Patent Publication No. 1-20549 or Japanese Patent Application Laid-Open No. 63-38259 does not consider the reliability of the external atmosphere. For this reason, in semiconductor devices in which the semiconductor chip is molded with plastic or sealed with a resin such as silicone gel, if charge is accumulated on the final protective film, the η-type semiconductor surface is inverted and the blocking characteristics deteriorate. .

Further, in the technique described in Japanese Patent Publication No. 3-58185, the potential of the semiconductor surface may be affected by an external charge, and there is a limit to improvement in reliability. Further, in this conventional technique, two or more insulating films are formed between the electrodes, and the conductivity of the upper insulating film is made larger than the conductivity of the lower insulating film. For this reason, the electric field concentration on the semiconductor surface is caused by the potential difference between the semiconductor substrate surface and the upper insulating film, so that the breakdown voltage may be reduced.

The present invention has been made in consideration of the above-described problems, and has been made in consideration of the above-described problems, and provides a planar-type semiconductor device having high withstand voltage or high reliability and a device using the same. A power conversion device is provided. Disclosure of the invention

In the semiconductor device of the present invention, the second semiconductor region of the second conductivity type, which is the opposite conductivity type, is provided in the first semiconductor region of the first conductivity type in the semiconductor substrate. The first semiconductor region and the second semiconductor region are in contact with the first main electrode and the second main electrode, respectively, to form a main element region. Around the second semiconductor region, a plurality of third semiconductor regions of the same conductivity type as this region are provided so as to surround this region. These multiple third semiconductor regions have an action as an electric field limiting ring region. A conductor contacts at least one of the plurality of third semiconductor regions. Furthermore, the surface of the semiconductor substrate has a portion covered with an insulator. In particular, on the insulator on the surface of the third semiconductor region adjacent to the second semiconductor region, a second main electrode extends from the second semiconductor region, and a conductor extends from another third semiconductor region. . The portions of the second main electrode and the conductor extending on the insulator act as field plates.

In such a configuration, a ρ η junction (hereinafter referred to as a main ρ η junction) between the first semiconductor region and the second semiconductor region is reversely biased between the first main electrode and the second main electrode. When such a voltage is applied, a depletion layer extending from the main ρη junction is exposed at a portion of the semiconductor substrate surface adjacent to the second semiconductor region. However, since the second main electrode extends over this portion, the electric field distribution in the depletion layer is not affected by external contaminants or moisture. Further, after the depletion layer has its tip reaching the third semiconductor region adjacent to the second semiconductor region, the depletion layer has a ρ η junction between the third semiconductor region and the first semiconductor region (hereinafter referred to as a sub ρ η junction). And spread again. For this reason, the depletion layer is hardly exposed on the surface of the third semiconductor region, and extends from the sub ρη junction. The exposed region is exposed again to the surface of the semiconductor substrate. However, since the conductor extends from another adjacent third semiconductor region on the surface of the semiconductor substrate, the electric field distribution is hardly affected by external contaminants and moisture.

As described above, in the semiconductor device of the present invention, the electric field distribution on the surface of the semiconductor substrate is not affected by external contaminants or moisture, but is determined by the field plate action of the second main electrode and the conductor. Thus, the electrical characteristics of the semiconductor device are stabilized, and the reliability is improved.

It should be noted that the reliability is similarly improved by replacing the second main electrode extending over the third semiconductor region with a conductor that is in contact with another adjacent third semiconductor region.

Further, as a preferred configuration, on the surface of the semiconductor substrate, the thickness of the insulator on the exposed portion of the sub pn junction is larger than the thickness of the insulator adjacent to the second semiconductor region and the third semiconductor region in contact with the conductor. There are large configurations. As a result, a sudden change in the electric field distribution near the sub pn junction is reduced, and local electric field concentration is prevented. Therefore, the breakdown voltage is improved.

In a modular semiconductor device incorporating the semiconductor device of the present invention, the withstand voltage does not deteriorate even if the resin filled in the package contains moisture.

Next, a method for manufacturing a semiconductor device of the present invention will be described.

First, in the first step, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type (opposite conductivity type) located in the first semiconductor region and exposed on the surface of the semiconductor substrate, A semiconductor substrate having a plurality of third semiconductor regions, which is conductive and surrounds the second semiconductor region and is exposed on the surface of the semiconductor substrate, is prepared. Next, in a second step, a first insulating film is formed on the surface of the semiconductor substrate. Further, in the third step, the first insulating film on the surface of at least one third semiconductor region is removed. Further, in a fourth step, a second insulating film is formed on the surface of the semiconductor substrate. Then, the fifth step In the method, the second insulating film adjacent to the second semiconductor region and the third semiconductor region from which the insulating film on the surface has been removed in the third step is removed.

According to such a method, the thickness of the oxide film is larger in the region where the second insulating film remains without being removed on the surface of the semiconductor substrate than in other regions. That is, the more preferable structure of the semiconductor device of the present invention described above is manufactured.

Similarly, the manufacturing method in which an oxide film is formed as the first insulating film in the second step, and the subsequent step is replaced with a step to which a so-called LOCOS oxidation method is applied, is also provided by the semiconductor device of the present invention. The preferred configuration is created. In the present manufacturing method, in the third step, an antioxidant film is formed on the oxide film. Further, in the fourth step, the antioxidant film on the surface of at least one third semiconductor region is removed. Thereafter, in the fifth step, when the semiconductor substrate is oxidized, the oxide film in the region where the antioxidant film has been removed grows and becomes thick.

The semiconductor device or the modular semiconductor device of the present invention as described above is applied as a semiconductor device such as a switching element or a diode in a device that performs power conversion or power control by turning on and off a semiconductor switching element. Then, a highly reliable and long-life high-voltage device can be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic sectional view of a high breakdown voltage planar type diode according to an embodiment of the present invention.

FIG. 2 is a schematic plan view showing one embodiment of the high breakdown voltage planar type diode according to the embodiment of the present invention.

FIG. 3 shows a high breakdown voltage planar diode according to an embodiment of the present invention. D is a schematic sectional view showing how a depletion layer expands.

FIG. 4 shows the electric field distribution on the surface of the semiconductor substrate corresponding to the expansion of the depletion layer in FIG.

FIG. 5 is a schematic cross-sectional view showing the expansion of a depletion layer when a voltage equal to the withstand voltage is applied to the high breakdown voltage planar type diode according to the embodiment of the present invention.

FIG. 6 shows the electric field distribution on the surface of the semiconductor substrate corresponding to the expansion of the depletion layer in FIG.

FIG. 5 is a schematic sectional view of a high-breakdown-voltage planar IGBT according to an embodiment of the present invention.

FIG. 8 is a schematic sectional view of another high breakdown voltage planar type diode according to the embodiment of the present invention.

FIG. 9 is a schematic sectional view of another high-breakdown-voltage planar IGBT according to an embodiment of the present invention.

FIG. 10 shows a method of manufacturing the diode shown in FIG.

FIG. 11 shows a method of manufacturing the diode shown in FIG.

FIG. 12 shows a module type semiconductor device according to an embodiment of the present invention. FIG. 13 shows a main circuit of an induction motor driving inverter device according to an embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a schematic sectional view of a high breakdown voltage planar type diode according to an embodiment of the present invention. In FIG. 1, a semiconductor substrate 100 having a pair of main surfaces 110 and 120 has an n-type semiconductor region 10 adjacent to one main surface 110 and one main surface 110. A central pn junction extending from the main surface into the n-type semiconductor region 10 at the center of the n-type semiconductor region 10 with the n-type semiconductor region 10 P + -type semiconductor region 20, which is formed between the other main surface 120 and the n-type semiconductor region 10 and has an impurity concentration higher than that of the n-type semiconductor region 10. At the periphery of one main surface 110, a plurality of P + type electric field limiting ring regions 21 to 2 extending from this main surface into n type semiconductor region 10 and surrounding p + type semiconductor region 20 An n + -type ring having an impurity concentration higher than that of the n-type semiconductor region 10 extending from the main surface 110 into the n-type semiconductor region 10 and surrounding the p + -type electric field limiting ring region 21 to 29 It has region 30.

The anode electrode 1 is in ohmic contact with the P + type semiconductor region 20, extends on the first insulating film 31 and the second insulating film 41 formed in the n type semiconductor region 10, and further has a P + type It is formed so as to cover the sub-P n junction composed of the electric field limiting ring region 21 and the n-type semiconductor region 10. Force source electrode 2 makes ohmic contact with n + type semiconductor region 40. The auxiliary electrode 3 is in intimate contact with the n + type ring region 30 and extends on the first insulating film 35 and the second insulating film 45 formed in the n type semiconductor region 10. Further, it is formed so as to cover the sub ρ η junction composed of the p + type electric field limiting ring region 29 and the η type semiconductor region 10. The field plates 11 to 14 are in ohmic contact with the ρ + type electric field limiting ring regions 22, 24, 26, 28, respectively, and are formed on the first insulating films 31 to 35 and the second insulating film. 41 extends over 1 to 45 and is formed so as to cover the subΡη junction consisting of the ρ + electric field limiting ring regions 21, 23, 25, 27, 29 and the η type semiconductor region 10. You.

The third insulating film 70 made of polyimide silicone or the like is formed around the anode electrode 1, the surface of the auxiliary electrode 3, on the field plates 11 to 14, and further on the surface of the second insulating film. You. Further, a fourth insulating film 80 is formed on the third insulating film 70.

Figure 2 shows the high breakdown voltage planar diode shown in Figure 1 on one main table. FIG. 4 is a plan view from the surface 110, showing the anode electrode 1, the field plates 11 to 14, the auxiliary electrode 3, and the vicinity of the contact portion between the anode electrode 1 and the p + type semiconductor region 2a, n + The inside 3a of the contact portion with the mold ring region 30 is shown. FIG. 1 is a schematic cross-sectional view taken along the line AA ′ in FIG.

FIG. 3 shows how the depletion layer spreads in the high breakdown voltage planar diode shown in FIG. When a reverse bias voltage such that the anode electrode 1 is negative and the force source electrode 2 is positive is applied to the diode, the main diode consisting of the n-type semiconductor region 10 and the p + -type semiconductor region 20 is applied. The depletion layer mainly extends from the pn junction into the n-type semiconductor region 10 having a low impurity concentration. As shown by the depletion layer tip 201 when the applied voltage is low, the depletion layer is formed more on the surface than on the inside of the semiconductor due to the field plate effect of the anode electrode 1 extending over the n-type semiconductor region 10. Easy to spread. Until the tip 201 of the depletion layer spreading on the surface of the semiconductor reaches the electric field limiting ring region 21. The electric field strength on the surface of the n-type semiconductor region 10 is approximated as shown in Fig. 4 (a). Are represented by triangles.

When the applied voltage further increases, the depletion layer reaches the electric field limiting ring region 21 and thereafter expands from the electric field limiting ring region 21. In the present embodiment, a field plate 11 that is in intimate contact with the electric field limiting ring region 22 is formed so as to cover the surface of the n-type semiconductor region 10 and reach the electric field limiting ring region 21. The depletion layer is hardly spread on the surface of the n-type semiconductor region 10, as indicated by the tip 202 of the depletion layer.

The electric field strength on the surface of 10 is as shown in Fig. 4 (b). Here, the electric field strength on the right side of the electric field limiting ring region 21 is

By setting the interval 22 to be shorter than the interval between the p + type semiconductor region 20 and the electric field limiting ring region 21, it is possible to suppress the electric field intensity to an appropriate value. further y As the applied voltage further increases, the depletion layer further expands, as indicated by its tip 204. The electric field strength in that case is shown in Fig. 4 (c) and (d).

In the present embodiment, the surface of the low impurity concentration n-type semiconductor region 10 is shielded by an electrode or a field plate. This prevents deterioration of the blocking characteristics, such as the inversion of the surface of the n-type semiconductor region 10 to the P-type due to the influence of the external atmosphere such as electric charge and moisture in the resin, which lowers the breakdown voltage and increases the leak current. Is done. Furthermore, the second insulating films 41 to 45 form an insulating film on the sub pn junction composed of the electric field limiting ring regions 21, 23, 25, 27, 29 and the n-type semiconductor region 10. Is thick. For this reason, the effect of the field plate is weakened near these sub pn junctions, and local electric field concentration near the sub pn junction is prevented. Therefore, as shown in FIGS. 4 (c) and 4 (d), the peak values of the electric field intensity between the p + semiconductor region 20 and the electric field limiting ring region 21 and between the electric field limiting ring regions are substantially uniform. At the same time, the electric field strength that causes avalanche drop-off can be kept below Emax. When the applied voltage is increased to the withstand voltage of the semiconductor device, the depletion layer 200 expands as shown in FIG. At this time, as shown in FIG. 6, the maximum electric field intensity at each part of the surface of the n-type semiconductor region can be kept almost equal to a constant value and suppressed to Emax or less. Therefore, according to the present invention, a high breakdown voltage of the planar semiconductor device is realized.

FIG. 7 is a schematic sectional view of an insulated gate bipolar transistor (IGBT) according to another embodiment of the present invention. In this embodiment, an n-type semiconductor region 101, an n-type semiconductor region 60 formed adjacent to the n-type semiconductor region 101, and a p + region formed adjacent to the n-type semiconductor region 60 are formed. Electrode 22 2, gate electrode 11 2, n + type semiconductor region 10 2, p + type p-type region 2 10, ohmic contact with p-type semiconductor region 50, P + type semiconductor region 50 E. CT / JP95 / 00478

An insulating film 370 such as Si ₂ surrounding the gate electrode 112 and an emitter electrode 111 are provided. In the IGBT shown in FIG. 7, in the forward blocking state, the main pn junction composed of the p + type well region 210 and the n− type semiconductor region 101 is reverse-biased. Since the p + type well region 210 in FIG. 7 corresponds to the P + type semiconductor region 20 shown in FIG. 1, the operation of this embodiment is the same as that of the diode of FIG.

FIG. 8 is a schematic sectional view of a diode according to another embodiment of the present invention. In this embodiment, the first insulating film and the second insulating film are formed by L0C0S oxidation. Also in this embodiment, the surface of the electric field limiting ring regions 21, 23, 25, 27, the electric field limiting ring regions 21, 23, 25, 27 and the n-type semiconductor region 10 The thickness of the fifth insulating films 51 to 55 formed on the surface of the sub pn junction is thicker than others. Therefore, this embodiment operates in the same manner as the diode of FIG. 1, and has high breakdown voltage and high reliability. The configuration of this embodiment can be applied to GBT as shown in FIG.

FIG. 10 shows a method of manufacturing the diode shown in FIG.

In the step (a), first, the p + type semiconductor region 20 and the electric field limiting ring region 21 to 29 are formed on one main surface 110 side of the n-type semiconductor substrate 100 by thermal diffusion or ion implantation. And n + type ring region 30 are formed, and impurities such as phosphorus are diffused from other main surface 120 to form n + type semiconductor region 40. The n-type semiconductor region 10 may be formed on the n + -type semiconductor region 40 by epitaxy. The first insulating film 300 is formed on the surface of the semiconductor substrate on which the bonding structure is formed as described above. The first insulating film 300 is a composite film of the SiO ₂ film formed by the heat treatment and the PSG film deposited by the CVD method.

In step (b), the P + type semiconductor region 20, the electric field limiting ring regions 22, 24, 26, 28 and the n + type On the exposed surface of the region 30, the portion of the first insulating film in contact with the electrode is removed. By this step, the insulating film formed in the step (a) is divided into first insulating films 31 to 35.

In the step (c), a second insulating film 400 is formed by a CVD method or a microwave plasma CVD method.

In the step (d), the surfaces of the electric field limiting ring regions 21, 23, 25, 27 and the electric field limiting ring regions 21, 23, 25, 27 and the n-type semiconductor region 10 In order to increase the thickness of the insulating film on the surface of the sub pn junction, the insulating film formed in step (c) is processed by a photoetching technique to form second insulating films 41 to 45.

In the step (e), a metal such as aluminum is selectively deposited on the substrate surface by an electron beam evaporation method or a sputtering method, or is selectively etched after being deposited on the entire substrate surface. The electrode 1, field plates 11 to 14, and auxiliary electrode 3 can be formed.

In step (f), a PSG formed by a CVD method to protect the second insulating films 41 to 45, the anode electrode 1, the field plates 11 to 14 and the auxiliary electrode 3 is formed. A third insulating film 70 such as a film and a fourth insulating film 80 such as polyimide silicon are formed by a photo-etching technique. Further, a force source electrode 2 for contacting the n + type semiconductor region 40 having a high impurity concentration is formed of a multilayer film made of aluminum, nickel, chromium and silver.

FIG. 11 shows a method of manufacturing the diode shown in FIG. In this production method, the steps (b) to (d) are particularly different from the above-mentioned production method, and a so-called LOCOS oxidation method is applied. As described below, an oxide film having a partially different thickness is formed by the LOCOS oxidation method.

In step (b), CVD method or bra on S i 〇 ₂ film 3 0 0 A non-oxidizing insulating film 90 such as Si ₃ N ₄ is formed by the plasma CVD method.

In the step (c), the insulating film formed in the step (b) is partially removed by a photo-etching technique. The remaining insulating films 91 to 96 are formed on the surface of the p + type semiconductor region 20, the electric field limiting ring regions 22, 24, 26, 28, and the n + type semiconductor region 30 and the electric field limiting ring. Overlying the surface of the sub-P n junction consisting of the silicon region and the n-type semiconductor region. Thereafter, when the semiconductor substrate is thermally oxidized, the S i 0, film at the portion where the insulating film is removed grows and becomes thicker.

In the step (d), the remaining insulating film is removed with hot phosphoric acid or the like. Thereafter, the ho Toetsuchingu technology, p + -type semiconductor region 2 0, field limiting ring region 2 2, 2 4, 2 6, 2 8, and S i 0 ₂ film is partially of the n + -type semiconductor regions 3 0 of the surface Is removed. Note that a PSG film may be formed on the SiO film after the insulating film is removed by hot phosphoric acid or the like. FIG. 12 shows a modular semiconductor device incorporating a semiconductor device embodying the present invention. The semiconductor devices 60 1 and 60 1 ′ embodying the present invention are adhered to a metal heat sink plate 62 through an electrical insulating plate 60 3, and these semiconductor devices and the extraction electrodes 60 05 Are electrically connected by the internal wiring 604. The semiconductor device and the electrodes mounted on the metal plate as described above are sealed in the plastic case 607 for mechanical protection. The inside of the plastic case is filled with an insulating material 606 such as gel silicone for insulation and protection of the semiconductor device and the internal wiring 504 and the like.

As described above, the electrical characteristics of the semiconductor device and the module-type semiconductor device to which the present invention is applied are such that a voltage of 1600 V is applied for 1000 hours under a humidity of 85% and a temperature of 85 ° C. It is stable without deterioration in reliability tests performed. The present invention is not limited to diodes and IGBTs, but can be applied to various planar semiconductor devices. In each embodiment, the present invention can be applied to a semiconductor device in which the conductivity type of each semiconductor region is reversed, that is, a semiconductor device in which p-type is replaced with n-type and n-type is replaced with p-type.

FIG. 13 shows a main circuit of an inverter device for driving an induction motor in which a modular semiconductor device having a built-in IGBT and a diode according to the present invention is used. The portion surrounded by a square in the figure, that is, the anti-parallel circuit portion of IGBT 60] and the diode 61 1 ′ is a module type semiconductor device. This inverter device has a pair of DC terminals 543 and 544, and three AC terminals 557 to 559 having the same number of phases. A DC power supply is connected to the DC terminal, and each of the IGBTs 545 to 550 is switched, so that DC power is converted to AC power. The AC power is output to each AC terminal, and the induction motor 100 is driven. Between the DC terminals, two IGBTs connected in series have both ends connected by the number equal to the number of AC phases. An AC terminal is taken out from the interconnection point of the two IGBTs connected in series. A diode is connected in anti-parallel to each IGB T to circulate the load current. In addition, in the anti-parallel circuit part of the IGBT and the diode, a snubber circuit consisting of a diode 600 ′, a resistor 71 0 and a capacitor 62 0 is connected in parallel. The present invention may be applied to '. Note that the 1 GBT 601 and the diode 601 'may be individually packaged.

Although the life of the inverter device depends on the reliability of the semiconductor device, according to the present invention, the IGBT and the diode have a high withstand voltage and the reliability is improved. The device is realized. The present invention is not limited to the inverter device, and can be applied to various power conversion devices and power control devices. As described in detail above, according to the present invention, a planar semiconductor device or a module semiconductor device having high withstand voltage or high reliability is realized. Further, according to the present invention, a power conversion device such as an inverter device having a large capacity and high reliability is realized.

Claims

The scope of the claims

1. a semiconductor substrate having a first semiconductor region of a first conductivity type;

A second semiconductor region of the second conductivity type, which is located in the first semiconductor region and is exposed on the surface of the semiconductor substrate;

A plurality of third semiconductor regions of the second conductivity type, located in the first semiconductor region, surrounding the second semiconductor region, and exposed on the surface of the semiconductor substrate;

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

A conductor contacting at least one of the plurality of third semiconductor regions, an insulator located on a surface of the semiconductor substrate,

With

A semiconductor device in which a second main electrode and a conductor extend on an insulator on a surface of a third semiconductor region adjacent to the second semiconductor region.

2. The insulator according to claim 1, wherein the thickness of the insulator first portion on the exposed portion of the junction between the third semiconductor region and the first semiconductor region adjacent to the second semiconductor region on the surface of the semiconductor substrate is equal to or greater than the second semiconductor thickness. A semiconductor device having a thickness greater than a thickness of a second portion of the insulator adjacent to the third semiconductor region with which the region and the conductor are in contact.

3. The semiconductor device according to claim 2, wherein the first portion of the insulator covers an exposed portion of the junction.

4. The semiconductor device according to claim 1, wherein a distance between the second semiconductor region and a third semiconductor region adjacent to the second semiconductor region is equal to a distance between the third semiconductor region adjacent to the second semiconductor region and the third semiconductor region. A semiconductor device that is wider than the distance from the semiconductor area.

5. The semiconductor device according to claim 1, wherein one third semiconductor region is located between two third semiconductor regions in contact with the conductor, and 半導体 b A semiconductor device in which a conductor extends from the two third semiconductor regions on an insulator on the surface.

6. In Claim 5, the thickness of the first portion of the insulator on the exposed portion of the junction between the one third semiconductor region and the first semiconductor region is adjacent to the two third semiconductor regions. A semiconductor device that is larger than the thickness of the second portion of the insulating material.

7. The semiconductor device according to claim 6, wherein the first portion of the insulator covers an exposed portion of the junction.

8. A semiconductor substrate having a first semiconductor region of a first conductivity type;

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

A conductor contacting at least two of the plurality of third semiconductor regions, an insulator located on the surface of the semiconductor substrate,

With

One third semiconductor region is located between two third semiconductor regions in contact with the conductor, and the two third semiconductor regions are formed on an insulator on a surface of the one third semiconductor region. A semiconductor device having a conductor extending from the semiconductor device.

9. In Claim 8, the thickness of the first portion of the insulator on the exposed portion of the junction between the one third semiconductor region and the first semiconductor region is adjacent to the two third semiconductor regions. A semiconductor device that is larger than the thickness of the second portion of the insulating material.

10. The method of claim 9, wherein the first portion of the insulator is exposed to the junction. Semiconductor device covering part.

11. The device according to claim 8, wherein the distance between the one third semiconductor region and the third semiconductor region located on the side of the second semiconductor region among the two third semiconductor regions is smaller than the distance between the one third semiconductor region and the third semiconductor region. A semiconductor device in which an interval between a third semiconductor region and a third semiconductor region of the two third semiconductor regions located on the opposite side of the second semiconductor region is widened.

12. A first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type located in the first semiconductor region and exposed on the surface of the semiconductor substrate, and a first semiconductor region of the first conductivity type. A plurality of third semiconductor regions of a second conductivity type, surrounding the second semiconductor region, and exposing to the surface of the semiconductor substrate; and

A second step of forming a first insulating film on the surface of the semiconductor substrate;

A third step of removing the first insulating film on the surface of at least one third semiconductor region;

A second step of forming a second insulating film on the surface of the semiconductor substrate;

A fourth step of removing the second insulating film adjacent to the second semiconductor region and the one third semiconductor region;

A method for manufacturing a semiconductor device having:

1 3. A first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type located in the first semiconductor region and exposed on the surface of the semiconductor substrate, and in the first semiconductor region. A plurality of third semiconductor regions of a second conductivity type, surrounding the second semiconductor region, and exposing to the surface of the semiconductor substrate; and

A second step of forming an oxide film on the surface of the semiconductor substrate;

A third step of forming an antioxidant film on the oxide film,

Removing the antioxidant film on the surface of at least one third semiconductor region; 1 o process and

A fifth step of oxidizing the semiconductor substrate;

A method for manufacturing a semiconductor device having:

1 4. Metal plate and

A plastic case that covers the metal plate,

An insulating plate adhered to the metal plate in the plastic case,

A semiconductor element adhered on the insulating plate;

An electrode terminal that is bonded to the insulating plate and pulled out of the plastic case, and is electrically connected to the semiconductor element;

In a plastic case, an insulating resin covering the semiconductor element is provided.

Wherein the semiconductor element is

A semiconductor substrate having a first semiconductor region of a first conductivity type;

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

With

1 5. Metal plate and

A plastic case that covers the metal plate, An insulating plate bonded to the metal plate in the plastic case; a semiconductor element bonded to the insulating plate;

Wherein the semiconductor element is

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

A conductor contacting at least two of the plurality of third semiconductor regions; and an insulator located on a surface of the semiconductor substrate.

One third semiconductor region is located between two third semiconductor regions in contact with a conductor, and the two third semiconductor regions are formed on an insulator on a surface of the one third semiconductor region. A semiconductor device having a conductor extending from the semiconductor device.

1 6. A pair of DC terminals,

The number of AC terminals equal to the number of AC phases;

Has,

A plurality of semiconductor devices connected in series has a number equal to the number of AC phases, and a plurality of semiconductor devices connected in series is connected between DC terminals, An AC terminal is taken out from an interconnection point of the plurality of semiconductor devices connected in series,

Semiconductor device

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

With

A power converter in which a second main electrode and a conductor extend on an insulator on a surface of a third semiconductor region adjacent to the second semiconductor region.

1 7. A pair of DC terminals,

The number of AC terminals equal to the number of AC phases;

Has,

A plurality of semiconductor devices connected in series has a number equal to the number of AC phases, and a plurality of semiconductor devices connected in series is connected between DC terminals,

An AC terminal is taken out from an interconnection point of the plurality of semiconductor devices connected in series,

Semiconductor device

A semiconductor base having a first semiconductor region of a first conductivity type;

A second conductive layer located in the first semiconductor region and exposed on the surface of the semiconductor substrate; A second semiconductor region of the mold;

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

With

One third semiconductor region is located between two third semiconductor regions in contact with a conductor, and the two third semiconductor regions are formed on an insulator on a surface of the one third semiconductor region. A power converter in which a conductor extends from the power converter.

1 8. A pair of DC terminals,

The number of AC terminals equal to the number of AC phases;

Has,

The AC terminal is taken out from an interconnection point of the plurality of semiconductor elements connected in series,

Semiconductor device

A metal plate,

A plastic case that covers the metal plate,

An insulating plate adhered to the metal plate in the plastic case,

A semiconductor element adhered on the insulating plate;

An electrode terminal that is bonded to the insulating plate and pulled out of the plastic case, and is electrically connected to the semiconductor element; In a plastic case, an insulating resin covering the semiconductor element is provided.

Wherein the semiconductor element is

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

With

1 9. A pair of DC terminals,

The number of AC terminals equal to the number of AC phases;

Has,

Semiconductor device

A metal plate,

Wherein the semiconductor element is

A first main electrode contacting the first semiconductor region;

A second main electrode contacting the second semiconductor region;

With