JP2000183282A - Device and module of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To aim at improvement in the reliability of a semiconductor device and a reduction in the impedance between chips in the device by a method, wherein the device is provided with a high breakdown voltage semiconductor element provided on a semiconductor substrate, the bonded terminal region of the semiconductor chip and an insulative frame provided on the outer periphery part of the substrate in such a way as to cover the bonded terminal region. SOLUTION: An insulative adhesion layer 32, such as a silicon layer, is formed in such a way as to cover a passivation film 9b', one end of an emitter electrode 7 and an electrode 10 and an insulative chip plate 31 is mounted on the outer periphery of a semiconductor chip 30 via the layer 32. As a result, the frame 31 covers the bonded terminal part of the chip 30. The frame 31 is further extended until the side surface part of the chip 30, in such a way as to cover the layer 32 and completely covers the bonded terminal part of the chip 30. Accordingly, the chip 30 is protected from creeping discharge in the bonded terminal part by the frame 31 consisting of an insulative resin, and a defective chip is extracted and be excepted in advance by a test of a high-voltage application.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a semiconductor device having a high withstand voltage and a semiconductor module including one or more of these devices.

[0002]

2. Description of the Related Art Conventionally, insulated gate type transistors (IG)
2. Description of the Related Art High-breakdown-voltage semiconductor elements having a large rated voltage, such as BT) and injection-promoting gate transistor (IEGT), generally have a large rated current and use a semiconductor module having a plurality of high-breakdown-voltage semiconductor chips mounted in parallel.

FIG. 26 shows a high breakdown voltage semiconductor device (IGBT).
FIG. 10 is a cross-sectional view showing a conventional terminal structure of a semiconductor chip provided with the above. As shown in FIG. 26, n-type buffer layer 3 is formed on one surface of n ^- type base layer 301 made of an n ^- type substrate.
02 and a p ⁺ -type collector layer 303 are sequentially formed.
^The p-type base layer 304 is provided on the other surface of the
Are selectively formed, and an n ⁺ -type source layer 305 is selectively formed in the p-type base layer 304.

[0004] A collector electrode 306 is formed on the surface of the p ⁺ -type collector layer 303, and an emitter electrode 307 is formed over the p-type base layer 304 and the n ⁺ -type source layer 305. Further, a gate electrode 308 is formed on the surface of the p-type base layer 304 between the n ⁺ -type source layer 305 and the n ⁻ -type base layer 301 via a gate insulating film 309a. An insulating film 309 is formed on the gate electrode 308.
b, and the above-described emitter electrode 307 is formed on the insulating film 309b. As described above, the IGBT is provided on the semiconductor substrate (chip) as a high breakdown voltage semiconductor element.

A passivation film 309b 'made of an insulating film (such as a silicon oxide film) or a high-resistance film (such as a semi-insulating polycrystalline silicon film) is formed on the terminal surface of the semiconductor chip provided with such an IGBT. I have. One end of the passivation film 309b 'is a p-type base layer 30.
4 and the other end is connected to the n ⁺
It is connected to the mold stopper layer 311 and is kept at the substrate potential. The electrode 310 and the n ⁺ type stopper layer 311 play a role in preventing the depletion layer at the terminal end from extending to the chip end. Furthermore, in order to strengthen the high withstand voltage structure, an electric field relaxation structure such as a RESURF layer or a guard ring layer is often added to the surface of the semiconductor substrate on which the passivation film 309b 'is formed.

Next, a description will be given of a semiconductor module on which a semiconductor chip provided with a high breakdown voltage semiconductor element such as an IGBT is mounted. FIG. 27 is a schematic view showing the structure of a conventional semiconductor module. FIG. 27A is a plan view of the semiconductor module, and FIG. 27B is a cross-sectional view taken along line AA ′ of FIG.

As shown in FIG. 27, the IG described in FIG.
Semiconductor chip 3 provided with a high breakdown voltage semiconductor element such as BT
A plurality 30 are mounted on the module substrate 320 in parallel connection. A first main electrode (collector electrode, 3 in FIG. 26) formed on the first main surface of the semiconductor chip 330.
Equivalent to 06. ) Is soldered to the first wiring pattern 321 on the module substrate 320 and the second wiring pattern 321 on the second main surface.
Main electrode (emitter electrode; equivalent to 307 in FIG. 26);
And a control electrode (gate electrode; equivalent to 308 in FIG. 26)
Are bonded to the second and third wiring patterns 322 and 323 on the module substrate 320, respectively.
24, 325. First, second and third
The wiring patterns 321, 322, and 323 are provided with a collector electrode lead-out part 326, an emitter electrode lead-out part 327, and a gate electrode lead-out part 328, respectively, and these lead-out parts electrically connect to an external device.

In such a conventional semiconductor module, a plurality of semiconductor chips 330 are
After mounting and bonding to 20, the entire surface is sealed with a gel-like passivating agent (not shown) to prevent creeping discharge between the emitter electrode 307 and the electrode 310 and between adjacent wiring patterns and bonding wires. It has been.

However, according to this method, if any of the plurality of semiconductor chips 330 connected in parallel has a defective chip in terms of withstand voltage, maximum breaking current, and the like, the entire module becomes a defective module. At this stage, it is extremely difficult to select and repair defective chips. In particular, there is a problem that a module including a large number of chips and having a large rated current has a high possibility that a defective chip is mixedly mounted.

Further, in the conventional semiconductor module, the respective wiring patterns 32 of the collector, the emitter, and the gate are provided.
1, 322, and 323 are all fixed to the module substrate 320, and the size of the module substrate 320 is increased in order to secure the insulation distance of each wiring pattern. Therefore, there is a problem that the length of the bonding wires 324 and 325 connecting the semiconductor chip 330 and the wiring patterns 322 and 323 increases, and the inductance component increases.

On the other hand, an IGBT provided on a semiconductor chip
And the like have the following problems. That is, in a conventional high-breakdown-voltage semiconductor device such as an IGBT, when a large current causes the temperature of the device to rise and reach a high temperature of, for example, 150 ° C., the device breaks down due to the temperature rise and operates. There was a problem of disappearing.

In order to solve this problem, conventionally, there has been known a method of detecting such a temperature rise and feeding back the detection result to an element. According to this method, when the element temperature reaches a high temperature, the detection result of the temperature rise is fed back to the element to control the switch of the element, whereby the high breakdown voltage semiconductor element can be protected.

In such a conventional method, it is necessary to separately provide a protection circuit for monitoring the element temperature and providing feedback outside the high voltage semiconductor element. This protection circuit constantly supplies a current to measure the element temperature, and monitors a voltage value generated by the current, that is, a temperature detection circuit that monitors the element temperature, and controls an element switch when the element temperature rises, thereby controlling the element switch. And a feedback circuit for sending a feedback signal to the element in order to protect the device.

FIG. 24 is a sectional view showing an element structure used in a temperature detection circuit in such a conventional protection circuit. As shown in FIG. 24, an insulating film 242 is formed on a semiconductor substrate 241 on which a high breakdown voltage semiconductor element such as an IGBT is formed.
, A deposited film of polysilicon or the like is formed, and a plurality of diodes are formed on the deposited film so as to be arranged in series with each other. 243 is a p-type anode region,
Reference numeral 244 denotes an n-type cathode region, and these regions are alternately arranged. Further, an anode electrode 245a is formed on the p-type anode region 243, and a connection electrode 2 is provided between the n-type cathode region and the p-type anode region in order from the side closer to the anode electrode 245a.
45b, 245c, and 245d are formed, and a cathode electrode 245e is formed on the n-type cathode region 244. Anode electrode 245a and cathode electrode 24
5e is electrically connected to each other via a constant current source (external DC power supply) 246, and a constant DC current always flows between the anode electrode 245a and the cathode electrode 245e. The voltage value between the anode electrode 245a and the cathode electrode 245e is monitored, and feedback for element protection is performed according to the voltage value.

The feedback to the high breakdown voltage semiconductor device using such a diode is performed as follows. FIG.
5 is a characteristic diagram showing the on-current-voltage characteristic of the diode. When the temperature of the diode rises (for example, from 25 ° C. to 125 ° C.) as shown in FIG. , The voltage value appearing at the diode decreases. Therefore, when the element temperature of the high breakdown voltage semiconductor element rises rapidly, the element temperature of the diode provided adjacently also rises, and the voltage value appearing at the diode decreases. The element temperature is detected by monitoring this voltage value, and feedback for element protection is performed in accordance with the detection result to control the switch of the element, whereby the high breakdown voltage semiconductor element can be protected.

However, since the protection circuit is provided outside the high-breakdown-voltage semiconductor element and uses control from such an external circuit, it is difficult to quickly and accurately cope with the temperature rise of the element, and there is a time lag. Was. Therefore, it is impossible to cope with an instantaneous rise in element temperature or the like, and the element cannot be sufficiently protected. In addition, there is also a problem that power consumption increases because a constant current always flows through the diode.

[0017]

As described above, in the conventional semiconductor device and semiconductor module with a high breakdown voltage, there is a possibility that a defective chip may be mixed, and the production yield and the reliability of the module are reduced. there were. Further, it has been difficult to reduce the size of the module and reduce the inductance of the wiring between chips.

In a conventional high breakdown voltage semiconductor device, a protection circuit is provided outside the high breakdown voltage semiconductor element in order to prevent the element from being destroyed when the element temperature reaches a high temperature. It was impossible to cope with the rapid rise of the temperature, and the element could not be sufficiently protected.

As described above, the conventional high breakdown voltage semiconductor device and semiconductor module have problems to be solved in terms of reliability, performance, and the like. The present invention has been made in view of such circumstances, and has as its object to provide a semiconductor device and a semiconductor module which are excellent in reliability, performance, and the like.

[0020]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a high-breakdown-voltage semiconductor element and a junction termination region provided on a semiconductor substrate, and the semiconductor substrate covering the junction termination region. And an insulating frame provided on an outer peripheral portion of the semiconductor device.

According to a second aspect of the present invention, there is provided a high-breakdown-voltage semiconductor element and a junction termination region provided on a semiconductor substrate, and an insulating frame provided to cover the junction termination region and an outer peripheral end of the semiconductor substrate. And a semiconductor device comprising:

In the first and second aspects of the present invention, it is desirable to provide the following configuration. (1) An insulating or semi-insulating first film is formed between the semiconductor substrate and the insulating frame so as to cover a surface of the semiconductor substrate, and an opening is formed in the first film. And an electrode of the high breakdown voltage semiconductor element and an electrode of the junction termination region are formed from the bottom of the opening to the first film.

(2) An insulating second film is formed between the first film and the insulating frame. (3) The second film is formed so as to cover an outer peripheral end of the semiconductor substrate.

(4) The second film is formed so as to cover the first film, the electrode of the high-breakdown-voltage semiconductor element, and the electrode in the junction termination region, and has a flat upper surface. That you are.

(5) The insulating frame is made of resin. (6) The resin is a resin selected from silicone and polyetherimide.

According to a third aspect of the present invention, there is provided a wiring board, and a semiconductor device provided on the wiring board. The semiconductor device has a high breakdown voltage semiconductor element and a junction termination region provided on the semiconductor substrate. An insulating frame provided on an outer peripheral portion of the semiconductor substrate so as to cover the junction termination region, wherein an electrode of the high breakdown voltage semiconductor element and an electrode of the wiring substrate are electrically connected to each other via the insulating frame. And a semiconductor module connected to the semiconductor module.

Still further, according to a fourth aspect of the present invention, there is provided a wiring board, and a plurality of semiconductor devices arranged on the wiring board. Each of the plurality of semiconductor devices is provided on the semiconductor substrate. A high breakdown voltage semiconductor element and a junction termination region, and an insulating frame provided on an outer peripheral portion of the semiconductor substrate so as to cover the junction termination region, wherein an electrode of the high breakdown voltage semiconductor element and an electrode of the wiring board are provided. Provides a semiconductor module which is electrically connected via the insulating frame.

In the third and fourth aspects of the present invention, it is desirable to provide the following configuration. (1) The electrode of the high breakdown voltage semiconductor element and the electrode of the wiring board are electrically connected by a bonding wire.

(2) A conductive film is provided on the insulating frame, and the electrode of the high breakdown voltage semiconductor element and the electrode of the wiring board are electrically connected via the conductive film. (3) A conductive plate for electrically connecting a conductive film provided on each of the insulating frames is provided in contact with the conductive film in an adjacent one of the plurality of semiconductor devices.

(4) The electrode of the high breakdown voltage semiconductor element and the conductive film are electrically connected by a bonding wire. (5) The electrode of the high breakdown voltage semiconductor element is pulled out to a position on the upper surface of the insulating frame by a conductive pin or a block member, and the insulating frame is inserted between adjacent semiconductor devices among the plurality of semiconductor devices. Be electrically connected to each other via a conductive plate provided thereon.

(6) An insulating or semi-insulating first film is formed between the semiconductor substrate and the insulating frame so as to cover the surface of the semiconductor substrate. Is provided with an opening, and the first portion is formed from the bottom of the opening.
The electrode of the high breakdown voltage semiconductor element and the electrode of the junction termination region are formed over the film of (1).

(7) An insulating second film is formed between the first film and the insulating frame. (8) The second film is formed so as to cover an outer peripheral end of the semiconductor substrate.

(9) The second film is formed so as to cover the first film, the electrode of the high-breakdown-voltage semiconductor element, and the electrode of the junction termination region. That you are.

(10) The insulating frame is made of resin. (11) The resin is a resin selected from silicone and polyetherimide.

According to the first to fourth aspects of the present invention described above,
Since the semiconductor substrate (semiconductor chip) is protected from creeping discharge at the junction termination by the insulating frame, before the mounting on the wiring substrate (module substrate), the withstand voltage test and the cutoff test (for each semiconductor substrate) It is possible to carry out high voltage application tests such as maximum rated voltage test, switching test when high voltage is applied, etc., and extract defective semiconductor substrates (those with poor breakdown voltage, maximum breaking current, etc.) in advance. Can be excluded.

Further, by using the insulating frame, it is possible to prevent the outer peripheral portion of the semiconductor substrate from being damaged during mounting on the wiring board. Further, it is possible to prevent a decrease in dielectric strength caused by the bonding wire approaching or contacting the outermost substrate potential electrode of the semiconductor substrate, the collector wiring pattern on the substrate, or the like. Furthermore, the insulating frame can be used for positioning when arranging a plurality of semiconductor substrates on a wiring substrate.

Further, prior to forming a conductive film such as an emitter wiring pattern or a gate wiring pattern on an insulating frame and mounting the conductive film on a wiring substrate, the electrodes (emitter electrodes, gate electrodes, etc.) of the respective semiconductor substrates are connected to the above-mentioned electrodes. By bonding the conductive film and the conductive film, bonding work on the wiring substrate can be eliminated. By performing the operation of extracting a defective chip from each of the bonded semiconductor substrates, it is possible to prevent the elements from being destroyed at the bonding stage, and to further improve the production yield of the module.

Further, a plurality of conductive films (emitter wiring patterns, gate wiring patterns, etc.) on the insulating frame.
By connecting the members on the insulating frame, an emitter wiring pattern, a gate wiring pattern, and the like on the module substrate become unnecessary, and the module can be reduced in size. Furthermore, it is possible to reduce the length of the bonding wire to each semiconductor substrate and to perform a low inductance connection, thereby realizing uniform operation between parallel chips.

According to a fifth aspect of the present invention, there is provided a main switching element provided on a semiconductor substrate, the main switching element having a high voltage side main electrode, a low voltage side main electrode, and a gate electrode; A diode inserted between the high-voltage side main electrode and the low-voltage side main electrode in a direction in which a reverse voltage is applied when the main switching element is on, and the gate electrode of the main switching element. A control switching element inserted between the high voltage side main electrode and the low voltage side main electrode, and when the main switching element is in an ON state and the element temperature rises, a reverse current flowing through the diode is provided. A semiconductor device is provided, wherein an increase in a leakage current in a direction is detected, and the control switching element is turned on by the leakage current.

According to a sixth aspect of the present invention, there is provided a main switching element provided on a semiconductor substrate, the main switching element having a high voltage side main electrode, a low voltage side main electrode, and a first gate electrode. An anode electrode connected to the low-voltage main electrode via a resistor, a cathode electrode connected to the first gate electrode, a source electrode, a drain electrode, and a second gate electrode; A field-effect transistor in which the second gate electrode is connected to the anode electrode, the source electrode is connected to the low-voltage side main electrode of the main switching element, and the drain electrode is connected to the first gate electrode. And a semiconductor device comprising:

According to a seventh aspect of the present invention, there is provided a main switching element provided on a semiconductor substrate, the main switching element having a high voltage side main electrode, a low voltage side main electrode, and a first gate electrode. A diode having a cathode electrode connected to the first gate electrode, an emitter electrode, a collector electrode, and a base electrode; the base electrode connected to the anode electrode of the diode; There is provided a semiconductor device comprising: a bipolar transistor having the electrode connected to the emitter electrode and the first gate electrode connected to the collector electrode.

According to an eighth aspect of the present invention, there is provided a main switching element provided on a semiconductor substrate and having a high voltage side main electrode, a low voltage side main electrode, and a first gate electrode, an anode electrode, a base electrode, A thyristor having a cathode electrode, wherein the anode electrode is connected to the first gate electrode of the main switching element, and the cathode electrode is connected to a low-voltage main electrode of the main switching element; and a base of the thyristor. A semiconductor device comprising: a diode having an anode connected to the electrode; and a diode having a cathode connected to the first gate electrode of the main switching element.

In the fifth, sixth, seventh and eighth aspects of the present invention, it is desirable to provide the following configuration. (1) The main switching element and the diode are provided on the same semiconductor substrate.

(2) The control switching element is provided outside the semiconductor substrate. (3) A pressure contact package is attached to the semiconductor substrate, and the control switching element is provided in the pressure contact package.

(4) The semiconductor device is mounted on a wiring board, and the control switching element is provided on the wiring board. An eighth aspect of the present invention provides a main switching element provided on a semiconductor substrate and including a high-voltage main electrode, a low-voltage main electrode, and a gate electrode, and a main switching element provided on the semiconductor substrate, A diode inserted between the gate electrode and the high voltage side main electrode or the low voltage side main electrode in a direction in which a reverse voltage is applied when the main switching element is in an on state; and a diode provided on the semiconductor substrate. A bonded termination region, an insulating frame provided on an outer peripheral portion of the semiconductor substrate to cover the junction termination region,
A control switching element provided on the insulating frame and inserted between the gate electrode of the main switching element and the high voltage side main electrode or the low voltage side main electrode, wherein the main switching element is In the on state,
Provided is a semiconductor device, wherein when the element temperature rises, an increase in a reverse leakage current flowing through the diode is detected, and the control switching element is turned on by the leakage current.

According to the fifth to eighth aspects of the present invention described above,
When the main switching element is turned on, the amount of heat generated in the element increases, and the element temperature rises rapidly, the leak current in the reverse direction flowing through the diode rapidly increases. By detecting the increase of the leak current in the reverse direction and turning on the control switching element by the leak current,
A short circuit occurs between the gate electrode of the main switching element and the high voltage side main electrode or the low voltage side main electrode, and the main switching element is turned off. Therefore, the generation of heat in the main switching element is suppressed, and it is possible to prevent the main switching element from being damaged by heat in advance.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device and semiconductor module of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. 2 is a plan view showing a structure of a semiconductor module using the semiconductor device of FIG. 1, and FIG. 3 is a sectional view showing a section taken along line AA 'of the semiconductor module shown in FIG.

As shown in FIG. 1, n ^- type substrate n
^An n-type buffer layer 2 and ap ⁺ -type collector layer 3 are sequentially formed on one surface of the-type base layer 1, and the n ^- type base layer 1
A p-type base layer 4 is selectively formed on the other surface of
An n ⁺ type source layer 5 is selectively formed in the type base layer 4.

A collector electrode 6 is formed on the surface of the p ⁺ -type collector layer 3, and an emitter electrode 7 is formed across the p-type base layer 4 and the n ⁺ -type source layer 5. Further, a gate electrode 8 is formed on the surface of the p-type base layer 4 between the n ⁺ -type source layer 5 and the n ^-- type base layer 1 via a gate insulating film 9a. An insulating film 9b is formed on the gate electrode 8, and the above-described emitter electrode 7 is formed on the insulating film 9b. As described above, the IGBT is provided on the semiconductor substrate (chip) 30 as a high breakdown voltage semiconductor element.

A passivation film 9b 'made of an insulating film (such as a silicon oxide film) or a high-resistance film (such as a semi-insulating polycrystalline silicon film) is formed on the terminal surface of the semiconductor chip 30 provided with such an IGBT. ing. One end of the passivation film 9b 'is connected to the terminal end of the p-type base layer 4, and the other end (outermost peripheral portion of the chip) is an n ⁺ -type stopper via a substrate potential ring-shaped electrode (substrate potential ring) 10. Connected to layer 11 and held at substrate potential. Here, an insulating film (such as a silicon oxide film) and a high-resistance film (such as a semi-insulating polycrystalline silicon film) may be formed in this order from the bottom, and the high-resistance film is formed as a passivation film 9b '.
The electrical connection may be made as described above. The electrode 10 and the n ⁺ -type stopper layer 11 serve to prevent the depletion layer at the terminal end from extending to the chip end and preventing the breakdown voltage from lowering. Furthermore, in order to strengthen the high withstand voltage structure,
An electric field relaxation structure such as a resurf layer or a guard ring layer is often added to the surface of the semiconductor substrate on which the passivation film 9b 'is formed.

Further, as shown in FIG. 1, the passivation film 9b ', one end of the emitter electrode 7 and the electrode 1
An insulating adhesive layer 32 made of silicone, polyimide, or the like is formed so as to cover the semiconductor chip 30 via the adhesive layer 32. As a result, the chip frame 31 has a structure in which the bonding end portion of the semiconductor chip 30 is covered. The chip frame 31 further extends to cover the side surface of the semiconductor chip 30 with the adhesive layer 32 interposed therebetween.
The outer peripheral edge of the semiconductor chip 30 is completely covered.

The chip frame 31 is molded from an insulating resin selected from silicone, polyetherimide, and the like, and has a size satisfying a space creepage distance according to the maximum rated voltage of the chip. Here, it is also possible to use a composite containing the above resin material and glass fiber as the insulating resin, and it is particularly preferable to use a composite containing polyetherimide and glass fiber.

A plurality of the semiconductor chips 30 described above are mounted and bonded on the wiring pattern of the module substrate in a state where the chip frame 31 is mounted so as to cover the joint termination. 2 and 3 are schematic diagrams showing the structure of the semiconductor module. FIG. 2 is a plan view of the semiconductor module, and FIG. 3 is a sectional view taken along line AA ′ in FIG.

As shown in FIGS. 2 and 3, a plurality of semiconductor chips 30 provided with a high-voltage semiconductor element such as the IGBT described in FIG. 1 are mounted on the module substrate 20 in parallel. A first main electrode (collector electrode, which corresponds to 6 in FIG. 1) formed on the first main surface of the semiconductor chip 30 is a first wiring pattern (collector wiring pattern) 21 on the module substrate 20. Is mounted by soldering or the like.

A second main electrode (emitter electrode; equivalent to 7 in FIG. 1) and a control electrode (gate electrode; equivalent to 8 in FIG. 1) on the second main surface are each a module substrate. Second wiring pattern on 20 (emitter wiring pattern)
22 and third wiring pattern (gate wiring pattern) 2
3 are connected by bonding wires 24a and 25a, respectively. Bonding wire 24
a and 25 a are provided so as to straddle over the chip frame 31.

The first, second, and third wiring patterns 21, 22, and 23 are provided with a collector electrode lead portion 26a, an emitter electrode lead portion 27a, and a gate electrode lead portion 28a, respectively. , An electrical connection to an external device is made.

According to the semiconductor chip 30 of this embodiment and the semiconductor module using the same, the semiconductor chip 30 is formed by the chip frame 31 made of insulating resin.
Is protected from creeping discharge at the junction termination, so it is possible to perform high voltage application tests such as withstand voltage test and cutoff test on the semiconductor chip before mounting, and extract and exclude defective chips in advance. Can be. The test jig includes a pressure contact device such as a spring structure or a hydraulic device for connecting each electrode of the semiconductor chip to the test circuit.

Further, by using the chip frame 31 of this embodiment, it is possible to prevent the chip outer peripheral portion from being damaged during chip mounting. Further, it is possible to prevent a decrease in withstand voltage due to the bonding wire approaching the substrate potential ring 10 on the outermost periphery of the chip and the collector wiring pattern 21 on the substrate. Further, in the present embodiment, long-term reliability can be improved by sealing with a gel-like passivation agent (not shown). Furthermore, the chip frame 31 can also be used for positioning when arranging a plurality of semiconductor chips 30 on the module substrate 20.

FIG. 4 is a sectional view showing a modification of the structure of the semiconductor device according to the above-described embodiment. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 4, instead of the chip frame 31, a coating type frame 33 is used as a chip frame. That is, in addition to attaching the chip frame 31 to the semiconductor chip 30 by the adhesive layer 32, an insulating resin selected from silicone, polyetherimide, or the like is used to satisfy the space creepage distance according to the maximum rated voltage of the chip. It is also possible to apply the coating to the bonding end portion of the chip 30, or this portion and the outer peripheral end portion. According to this modification, the same effects as those of the above-described embodiment can be obtained, and the chip frame can be easily provided on the semiconductor chip without using an adhesive. Note that it is also possible to use a composite containing the resin material and glass fiber as the insulating resin, and it is particularly preferable to use a composite containing polyetherimide and glass fiber.

(Second Embodiment) FIG. 5 is a perspective view showing a structure of a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a plan view showing the structure of a semiconductor module using the semiconductor device of FIG. 1, 2, and 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 5A, a chip frame 31 is mounted on a semiconductor chip 30 on which an IGBT is formed, and an emitter wiring pattern 22 'and a gate wiring pattern 23 are provided on the upper surface of the chip frame 31. 'Is provided. The emitter wiring pattern 22 'and the gate wiring pattern 23'
The emitter electrode 7 and the gate electrode 8 on the reference numeral 0 are connected by bonding wires 24b and 25b, respectively.

It is also possible to provide circuit components (such as resistors and capacitors) other than the wiring patterns on the upper surface of the chip frame 31. For example, as shown in FIG. 5B, a gate wiring pattern 23a 'is provided in addition to 23', and the wiring pattern 23a 'and the gate electrode 8 are connected by a bonding wire 25b'. A gate resistor 23b 'can be provided between the wiring patterns 23' and 23a '.

According to the present embodiment, the defective chips can be sorted out after bonding to the semiconductor chip 30, so that the defective chips broken by the bonding can be extracted, and the module manufacturing yield can be further improved compared to the first embodiment. It is possible to improve.

As shown in FIG. 6, a plurality of semiconductor chips 30 having undergone the bonding process are mounted on the module substrate 20 in parallel. Each semiconductor chip 30 is mounted on the module substrate 20 such that the sides of the chip frame 31 are brought into close contact with each other. In this embodiment, the emitter wiring pattern 22 and the gate wiring pattern 2 on the module substrate 20 are used.
Numerals 3 are respectively connected to the emitter wiring pattern 22 'and the gate wiring pattern 23' on the chip frame 31 by bonding wires 24c and 25c.

As described above, the emitter electrode 7 and the gate electrode 8 on the semiconductor chip 30 are
When connecting to the emitter wiring pattern 22 and the gate wiring pattern 23 on the chip frame 31, respectively.
If the connection is made via the upper emitter wiring pattern 22 'and the gate wiring pattern 23', the bonding wires 2 are directly connected between them as in the first embodiment.
Compared to the case where 4a and 25a are provided so as to straddle over the chip frame 31, the connection by the bonding wire can be performed more reliably, and the manufacturing yield of the bonding step can be improved. Also, the size of the semiconductor module can be reduced.

(Third Embodiment) FIG. 7 is a plan view showing the structure of a semiconductor module according to a third embodiment of the present invention. 1 to 6 are denoted by the same reference numerals, and detailed description will be omitted.

As shown in FIG. 7, only the collector wiring pattern 21 is formed on the module substrate 20, and a plurality of semiconductor chips 30 are mounted on the collector wiring pattern 21 in parallel. Each of the semiconductor chips 30 is connected to the collector wiring pattern 21 so that the sides of the chip frames 31 are brought into close contact with each other.
Mounted on top.

The emitter wiring patterns 22 ′ on these chip frames 31 are connected by metal plates 51 between adjacent semiconductor chips 30. Similarly, the gate wiring patterns 23 ′ on the chip frames 31 are connected by metal plates 52 between adjacent chip frames 31. Each of the collector wiring pattern 21, the metal plate 51, and the metal plate 52 has
b, an emitter electrode lead-out portion 27b, and a gate electrode lead-out portion 28b are provided, and these lead-out portions electrically connect to an external device.

According to the semiconductor module of the present embodiment, the emitter wiring pattern and the gate wiring pattern on the chip frame 31 are respectively connected to the adjacent semiconductor chip 3.
By connecting between the zeros on the chip frame 31, the emitter wiring pattern and the gate wiring pattern on the module substrate 20 become unnecessary, and the module substrate area can be reduced and the semiconductor module can be downsized. Further, the length of the bonding wire from each semiconductor chip 30 can be reduced, thereby enabling low inductance connection. Therefore, a uniform operation can be realized between the semiconductor chips connected in parallel, and a stable switching operation can be performed.

(Fourth Embodiment) FIG. 8 is a plan view showing the structure of a semiconductor module according to a fourth embodiment of the present invention. 1 to 6 are denoted by the same reference numerals, and detailed description will be omitted.

As shown in FIG. 8, only a collector wiring pattern 21 'is formed on the module substrate 20, and a plurality of semiconductor chips (IGBT chips) 30 are connected in parallel on the collector wiring pattern 21'. In addition to being mounted, a plurality of semiconductor chips (FRD (First Recover) for FWD (Free Wheel Diode)
y Diode) chip) 30 'is an IGBT chip 30
Are mounted in parallel so that the conduction direction is reversed. The chip frame 31 'is also mounted on the semiconductor chip 30' for FWD. Specifically, IGBT
Four chips 30 and two FRD chips 30 ′ are mounted, and these semiconductor chips 30 and 30 ′ are mounted.
Are arranged such that the sides of the chip frames 31 and 31 'are brought into close contact with each other and the collector wiring pattern 21 is formed.
′ Are mounted in an accurate arrangement.

The anode wiring pattern 2 is provided on the chip frame 31 'mounted on the FRD semiconductor chip 30'.
9 are provided. It is not necessary to provide the gate wiring pattern 23 'on the chip frame 31'. The anode wiring pattern 29 is connected to the anode electrode on the FRD by a bonding wire 24d,
On the other hand, the cathode electrode of the FRD provided on the back surface of the FRD chip 30 ′ is soldered to the collector wiring pattern 21 ′ on the module substrate 20.

The emitter wiring pattern 22 'on the chip frame 31 and the anode wiring pattern 29 on the chip frame 31' are connected by a metal plate 53 between the adjacent semiconductor chips 30, 30 '. Similarly, the gate wiring patterns 23 'on the chip frame 31 are connected between the adjacent chip frames 31 by the metal plates 54a and 54b. The collector wiring pattern 21 ', the metal plate 53, and the metal plates 54a and 54b respectively have a collector electrode lead portion 26c and an emitter electrode lead portion 2
7c, a gate electrode lead-out portion 28c is provided, and these lead-out portions electrically connect to an external device. In this way, the reverse conducting IGBT can be made compact, and can be easily applied to an inverter circuit or the like.

(Fifth Embodiment) FIG. 9 is a schematic view showing the structure of a semiconductor module and a semiconductor chip according to a fifth embodiment of the present invention. FIG. 9A is a plan view showing the structure of the semiconductor module, and FIG. 9B is a plan view of FIG.
Semiconductor chip (IGB) mounted on a semiconductor module
It is a perspective view which shows one structure (T chip). 1 to 6 are denoted by the same reference numerals, and detailed description will be omitted.

As shown in FIG. 9B, the I
In the GBT chip 30, no wiring pattern is formed on the chip frames 31 and 31 ', and no bonding connection is used. A metal block 57 and pins 58 are soldered to IGBT electrodes formed on each of the IGBT chips 30. In the present embodiment, a metal block 57 is connected to the emitter electrode of the IGBT, and a metal pin 58 is connected to the gate electrode.

The IGBT chip 30 shown in FIG.
As shown in (2), it is mounted on the module substrate 20 on which only the collector wiring pattern 21 'is formed. Also in the present embodiment, the collector wiring pattern 2 is similar to the fourth embodiment.
1 'is mounted with a 4-chip IGBT chip 30 connected in parallel, and a 2-chip FRD chip 30' is
It is mounted in anti-parallel connection with the T chip 30.

IGBT chip 30 and FRD chip 30
'Chip frames 31 and 3 respectively mounted on
On the upper surface of 1 ′, metal plates 55 and 56 are respectively provided with metal blocks 57 and pins 5 of four IGBT chips 30.
8 is connected by soldering.

Similarly, a metal block (not shown) is provided on the anode electrode on the FRD chip 30 'while maintaining electrical connection with the electrode. Metal plate 5 described above
5 is also electrically connected to the metal block of the FRD chip 30 '.

The four IGBT chips 30 are connected in parallel to each other by the metal plates 55 and 56, and two FRD chips 3 are connected to these IGBT chips 30.
0 'is anti-parallel connected.

Further, the collector wiring pattern 21 ', the metal plates 55 and 56 are provided with a collector electrode lead-out portion 26d, an emitter electrode lead-out portion 27d, and a gate electrode lead-out portion 28d, respectively. Electrical connections have been made. In this case, since no bonding connection is used, low inductance connection is possible, and uniform operation between the semiconductor chips connected in parallel can be realized. In this way, a high-performance reverse conducting IGBT can be made compact, and can be easily applied to inverter circuits and the like.

As described above, in the first to fifth embodiments, I
Although the description has been given by taking the GBT as an example, the invention is not limited to the IGBT,
The present invention is also applicable to modules of other semiconductor devices such as OSFET and IEGT. In addition, the gate shape of the semiconductor element and the electric field relaxation structure at the junction termination can be applied without being limited to the above embodiment. Others
Various modifications can be made without departing from the spirit of the present invention.

Next, a semiconductor device of the present invention for preventing element breakdown due to high temperature in a high breakdown voltage semiconductor device will be described. (Sixth Embodiment) FIG. 10 is a circuit diagram showing a sixth embodiment according to the semiconductor device of the present invention. FIG. 12 is a sectional view showing the element structure.

As shown in FIG. 10, the semiconductor device of this embodiment includes a gate drive power element 101 having a collector electrode, an emitter electrode, and a gate electrode, a protection diode 102 connected to the power element 101, and Field effect transistor (n-channel type MOSFET) 10
4 and a resistor 1 connected in series with the protection diode 102.
03. In FIG. 10, G is a gate electrode terminal, E is an emitter electrode terminal, and C is a collector electrode terminal.

The gate electrode of the power element 101 has a cathode electrode of the protection diode 102 and an n-channel type M
The drain electrode of the OSFET 104 is connected, and the source electrode of the n-channel MOSFET 104 is connected to the emitter electrode of the power element 101. Also,
An anode electrode of the protection diode 102 is connected to an emitter electrode of the power element 101 via a resistor 103 connected in series, and the anode electrode is an n-channel type
It is also connected to the gate electrode of the OSFET 104.

Next, the principle of element protection operation in the semiconductor device of the present invention shown in FIG. 10 will be described. FIG. 11 is a characteristic diagram showing a reverse current-voltage characteristic of the protection diode for explaining the principle of the element protection operation.

In FIG. 11, line A shows the characteristics of the protection diode at a low temperature (room temperature), and line B shows the characteristics of the protection diode at a high temperature (for example, 100 ° C. or higher). As shown in FIG. 11, at a low temperature (room temperature), only a small leak current (for example, (100 μA)) flows through the protection diode, but at a high temperature, a large current (for example, 125
At (° C.) (10 mA)) flows.

Therefore, the gate drive power element 10
When the element 1 is turned on and the amount of heat generated in the element increases and the element temperature rises rapidly, the current flowing through the protection diode 102 rapidly increases. As a result, the current flowing through the resistor 103 connected in series to the protection diode 102 also increases rapidly, and the potential drop increases at this portion, and a sufficiently positive voltage is applied to the gate electrode of the n-channel MOSFET 104. The Rukoto.

Thus, the n-channel type MOSFET 1
Since the element 04 is turned on, the gate electrode and the emitter electrode of the power element 101 are short-circuited (that is, the gate voltage decreases), and the power element 101 is turned off. Therefore, the generation of heat in the power element 101 is suppressed, and it is possible to prevent the power element 101 from being damaged by heat in advance.

FIG. 12 shows the protection diode 10 described above.
FIG. 3 is a cross-sectional view showing an element structure in a case where two-channel and n-channel MOSFETs 104 are formed on the same semiconductor substrate as a gate drive power element 101. The protection diode 102 for detecting the temperature is preferably provided in the vicinity of the power element 101, but is not provided in the main element portion (portion where the power element is formed) so as not to reduce the effective area of the power element 101. It is formed using a joint end portion for securing. Similarly, the n-channel MOSFET 104 is formed utilizing this junction termination.

As shown in FIG. 12, p-type regions 112 and 114 are selectively formed on the surface of n ⁻ type semiconductor substrate 111, and protective diode 102 is formed in p-type region (anode region) 112. However, the n-channel MOSFET 104 is formed in the p-type region 114.

That is, an n ⁺ -type cathode region 113 is selectively formed on the surface of the anode region 112, and an anode electrode 117 and a cathode region 118 are provided in the anode region 112 and the cathode region 113, respectively. I have.

On the other hand, the p-type region 114 has n ⁺
The source region 116 and the drain region 115 are selectively formed, and the source region 116 and the drain region 1 are formed.
The gate insulating film 121 is formed on the surface of the p-type region 114 between
The gate electrode 120 is provided through the gate electrode. Further, a source electrode 122 is provided so as to extend over the source region 116 and the p-type region 114, and a drain electrode 119 is provided in the drain region 115.

The cathode electrode 118 of the protection diode 102 and the drain electrode 119 of the n-channel MOSFET 104 are connected to the gate electrode of the power element 101, and the source electrode of the n-channel MOSFET 104 is connected to the emitter electrode of the power element 101. ing. Further, the anode electrode 117 of the protection diode 102 is connected to the emitter electrode of the power element 101 via the resistor 103 connected in series.
7 is a gate electrode 12 of the n-channel MOSFET 104
0 is also connected.

(Seventh Embodiment) FIG. 13 is a circuit diagram showing a seventh embodiment according to the semiconductor device of the present invention. The difference from the sixth embodiment is that a bipolar transistor 105 is used instead of the MOSFET 104 as a control element. That is, as shown in FIG. 13, the gate electrode of the power element 101 is connected to the cathode electrode of the protection diode 102 and the collector electrode of the bipolar transistor 105, and the emitter electrode of the bipolar transistor 105 is connected to the power element 101. Connected to the emitter electrode. Further, the anode electrode of the protection diode 102 is connected to the base electrode of the bipolar transistor 105.

The principle of element protection operation in the semiconductor device of this embodiment shown in FIG. 13 will be described. When the gate drive power element 101 is turned on, the amount of heat generated in the element increases, and the element temperature rises rapidly, the current flowing through the protection diode 102 increases rapidly. As a result, the value of the current flowing into the base electrode of the bipolar transistor 105 also sharply increases, and the bipolar transistor 105 is turned on, so that the gate electrode and the emitter electrode of the power element 101 are short-circuited (that is, the power element 101 is short-circuited). , The gate voltage decreases), and the power element 101 is turned off. Therefore, the generation of heat in the power element 101 is suppressed, and it is possible to prevent the power element 101 from being damaged by heat in advance.

As described above, according to the present embodiment, since the control is performed by using the leak current of the protection diode 102 as it is as the base current of the bipolar transistor 105, the resistor 103 shown in the sixth embodiment is omitted. It is possible to simplify the configuration. The bipolar transistor 105 is connected to the protection diode 102.
Since the semiconductor device has the same temperature characteristics as described above and is easily turned on as the element temperature increases, protection of the high breakdown voltage semiconductor device can be performed more easily and reliably.

FIG. 14 is a cross-sectional view in the case where all the protection circuits of the seventh embodiment are formed on the same semiconductor substrate as the power elements. The same parts as those in FIG. 12 are denoted by the same reference numerals,
Detailed description is omitted. As shown in FIG. 14, the above-described protection diode 102 and bipolar transistor 1
05 is formed on the same semiconductor substrate as the gate drive type power element 101. The protection diode 102 (and, if possible, the bipolar transistor 105) is preferably provided close to the power element 101. However, in order to prevent the effective area of the power element 101 from decreasing, the main element portion (the portion where the power element is formed) is provided. ), But is formed by using a joint termination portion for ensuring a withstand voltage. Similarly, the bipolar transistor 105 is formed utilizing this junction termination.

As shown in FIG. 14, a p-type region (base region) 124 is selectively formed on the surface of an n ⁻ -type semiconductor substrate 111 in addition to a p-type region (anode region) 112. Bipolar transistor 105 is formed in p-type region 124.

That is, the base region 124 has n
^{A +} type emitter region 125 and a collector region 123 are selectively formed, and the emitter region 125 and the collector region 123 are provided with an emitter electrode 128 and a collector electrode 126, respectively. A base electrode 127 is provided on the surface of the base region 124 between the emitter region 125 and the collector region 123.

Further, the cathode electrode 118 of the protection diode 102 and the collector electrode 126 of the bipolar transistor 105 are connected to the gate electrode of the power element 101, and the emitter electrode 128 of the bipolar transistor 105 is connected to the emitter of the power element 101. Connected to electrodes. The anode electrode 117 of the protection diode 102 is connected to the base electrode 127 of the bipolar transistor 105.

FIG. 15 is a sectional view showing a modification of the element structure according to the present embodiment. The same parts as those in FIG. 14 are denoted by the same reference numerals, and detailed description will be omitted. As shown in FIG. 15, the p-type region (anode region) 112 and the p-type region (base region) 124 are united into one p-type region 1.
10a. With such a configuration, it is possible to manufacture a more integrated element by a simpler process.

The p-type region 110a shown in FIG. 15 has a p ⁺ -type region 110a 'having a higher concentration than the p-type region 110a in a region below the cathode region 113 and the collector region 123.
Are formed. This p ⁺ type region 110a ′ extends from the lower region of cathode region 113 to the lower region between emitter region 125 and collector region 123. With such a configuration, the leak current of the protection diode 102 can efficiently reach the p-type region 110a (base region) between the emitter region 125 and the collector region 123 through the p ⁺ -type region 110a ′. An efficient element protection operation can be achieved.

Further, the collector region 123 is divided into a plurality of parts, and the protection diode 1 is provided between the collector regions 123.
Even when the leakage current of 02 flows, the efficiency of the leakage current reaching the base region can be improved, and an efficient element protection operation can be ensured.

FIG. 16 is a sectional view showing another modification of the element structure in this embodiment. The same parts as those in FIG. 14 are denoted by the same reference numerals, and detailed description will be omitted. FIG.
As shown in FIG. 6, the p-type region (base region) 110b
The mold region (anode region) 110c is formed so as to be in contact with each other. These p-type regions 110b and 1
10c are each formed at a desired p-type impurity concentration suitable for element operation.

As a method for forming the p-type regions 110b and 110c, for example, double diffusion of p-type impurities can be used. In the embodiment of FIG.
Similarly to the third embodiment, it is possible to provide a region corresponding to the high-concentration p ⁺ -type region 110a 'or to divide the collector region 123 into a plurality of parts. In this case, efficient element protection operation is achieved. It is possible.

(Eighth Embodiment) FIG. 17 is a circuit diagram showing an eighth embodiment according to the semiconductor device of the present invention. The difference from the sixth embodiment is that the control element is not the MOSFET 104 but the thyristor 10.
6 is used. That is, as shown in FIG. 17, the protection diode 1 is connected to the gate electrode of the power element 101.
02 is connected to the anode electrode of the thyristor 106, and the cathode electrode of the thyristor 106 is connected to the emitter electrode of the power element 101. The anode electrode of the protection diode 102 is connected to the base electrode of the thyristor 106.

The principle of the element protection operation in the semiconductor device of this embodiment shown in FIG. 17 will be described. When the gate drive power element 101 is turned on, the amount of heat generated in the element increases, and the element temperature rises rapidly, the current flowing through the protection diode 102 increases rapidly. As a result, the value of the current flowing into the base electrode of the thyristor 106 also sharply increases, and the thyristor 106 is turned on, so that the gate electrode and the emitter electrode of the power element 101 are short-circuited (that is, the gate is closed). When the voltage decreases), the power element 101 is turned off. Therefore, the generation of heat in the power element 101 is suppressed, and it is possible to prevent the power element 101 from being damaged by heat in advance.

As described above, according to the present embodiment, the leakage current of the protection diode 102 is directly used as the thyristor 10.
Since the control is performed using the base current of No. 6, the resistor 103 shown in the sixth embodiment can be omitted similarly to the seventh embodiment, and the configuration can be simplified. The thyristor 106 is connected to the protection diode 102.
Since the semiconductor device has the same temperature characteristics as described above and is easily turned on as the element temperature increases, protection of the high breakdown voltage semiconductor device can be performed more easily and reliably.

Furthermore, in this embodiment, when the element temperature rises, the thyristor 106 is turned on to turn off the power element 101. However, once the thyristor 106 is turned on, an external voltage is applied. The ON state is maintained until the gate voltage becomes negative by the application. Therefore, the power element 101 can be kept in the off state and not returned to the on state, and the element can be more reliably protected when the element temperature is high.

FIG. 18 is a sectional view in the case where all the protection circuits of the eighth embodiment are formed on the same semiconductor substrate as the power elements. The same parts as those in FIG. 12 are denoted by the same reference numerals,
Detailed description is omitted. As shown in FIG. 18, the above-described protection diode 102 and thyristor 106 are formed on the same semiconductor substrate as the gate drive power element 101. The protection diode 102 (and, if possible, the thyristor 106) is preferably provided close to the power element 101. However, in order to reduce the effective area of the power element 101, the main element portion (the part where the power element is formed) , And is formed using a joint termination portion for ensuring a withstand voltage. In addition, the thyristor 106 is similarly formed by utilizing the joint end portion.

As shown in FIG. 18, a p-type region (p-type base region) 129 is selectively formed on the surface of an n ⁻ -type semiconductor substrate 111 in addition to a p-type region (anode region) 112. The p-type region 129 has a thyristor 106
Are formed.

That is, an n-type base region 131 is selectively formed on the surface of the p-type base region 129, and a p-type anode region 132 is selectively formed on the surface of the n-type base region 131. Is formed. The n-type base region 131 is provided on the surface of the p-type base region 129.
An n-type cathode region 130 is formed at a distance from the substrate. An anode electrode 134 and a cathode electrode 133 are provided in the p-type anode region 132 and the n-type cathode region 130, respectively. Also, an n-type base region 1
A base electrode 135 is provided on the surface of p-type base region 129 between 31 and n-type cathode region 130.

Further, the cathode electrode 118 of the protection diode 102 and the anode electrode 13 of the thyristor 106
4 is connected to the gate electrode of the power element 101, and the cathode electrode 133 of the thyristor 106 is connected to the emitter electrode of the power element 101. Also,
The anode electrode 117 of the protection diode 102 is connected to the base electrode 135 of the thyristor 106 (the p-type base region 12).
9 above).

FIG. 19 is a sectional view showing a modification of the element structure in this embodiment. The same parts as those in FIG. 18 are denoted by the same reference numerals, and detailed description will be omitted. As shown in FIG. 19, the p-type region (anode region) 112 and the p-type region (p-type base region) 129 are combined into one p-type region 110d. With such a configuration,
It is possible to produce a more integrated device by a simpler process.

In the p-type region 110d of FIG. 19, a p ⁺ -type region 110d 'having a higher concentration than the p-type region 110d is formed in a region below the cathode region 113 and the cathode region 130.
Are formed. The p ⁺ type region 110 d ′ extends from the lower region of the cathode region 113 to the lower region between the cathode region 130 and the base region 131.
With this configuration, the leakage current of the protection diode 102 passes through the p ⁺ -type region 110d ′ and
It is possible to efficiently reach the p-type region 110d (base region) between 0 and the base region 131, and it is possible to achieve an efficient element protection operation.

Further, the cathode region 130 is divided into a plurality of parts, and the protection diode 1 is provided between the cathode regions 130.
Even when the leakage current of 02 flows, the efficiency of the leakage current reaching the base region can be improved, and an efficient element protection operation can be ensured.

FIG. 20 is a sectional view showing another modification of the element structure in this embodiment. The same parts as those in FIG. 18 are denoted by the same reference numerals, and detailed description will be omitted. FIG.
0, a p-type region (p-type base region) 110
e and the p-type region (anode region) 110f are formed to be in contact with each other. These p-type regions 110e
And 110f are each formed at a desired p-type impurity concentration suitable for element operation. p-type regions 110e and 11
As a method of forming 0f, for example, double diffusion of a p-type impurity can be used.

In the embodiment of FIG. 20, also in FIG.
Similarly to the third embodiment, it is possible to provide a region corresponding to the high-concentration p ⁺ -type region 110d 'or to divide the collector region 130 into a plurality of parts. In this case, an efficient element protection operation is achieved. It is possible.

(Ninth Embodiment) FIG. 21 is a circuit diagram showing a ninth embodiment according to the semiconductor device of the present invention. FIG. 22 is a perspective view showing a structure in this embodiment, and FIG. 23 is a cross-sectional view showing an element structure in this embodiment. The same parts as those in FIG. 10 are denoted by the same reference numerals.

As shown in FIG. 21, the semiconductor device of this embodiment is divided into two portions P and Q, and the portion Q is formed on the same substrate as the high breakdown voltage semiconductor device (gate drive power element 101). The P portion is a portion different from the substrate on which the high breakdown voltage semiconductor device (gate drive power element 101) is provided (for example, a module substrate on which wiring and the like are formed, a lid portion of a press-contact package). , And the chip frame in the above-described embodiment).

The part Q is a gate drive type power element 1 having a collector electrode, an emitter electrode, and a gate electrode.
01 and a protection diode 102 connected to the power element 101. Power element 101
The cathode electrode of the protection diode 102 is connected to the gate electrode, and these gate electrode and cathode electrode can be connected to the outside via the electrode terminal G. The anode electrode of the protection diode 102 can be connected to the outside via the electrode terminal A.

On the other hand, the portion P is composed of a field effect transistor (n-channel MOSFET) 104 and a resistor 103 connected to the field effect transistor 104. The gate electrode of the n-channel MOSFET 104 is connected to the source electrode of the MOSFET 104 via the resistor 103, and these gate and source electrodes can be connected to the outside via the electrode terminals A 'and E', respectively. Also, the n-channel MOSFET 10
The drain electrode 4 can be connected to the outside via the electrode terminal G '.

In the semiconductor device of the present embodiment having the above configuration, the electrode terminal G ', the electrode terminal A' and the electrode terminal E 'of the P portion are respectively replaced with the electrode terminal G, the electrode terminal A and the electrode terminal of the Q portion. The terminal E is connected to the terminal E. When the terminal E is connected, the circuit has the same configuration as the circuit shown in FIG.

As in the present embodiment, the semiconductor device is divided into two parts P and Q, and a protection diode 102 is provided in the part Q formed on the same substrate as the power element 101, and the power element 101 is provided. If the field effect transistor 104 is included in the portion of P formed in a portion different from the substrate provided, the protection diode 102 is provided in close proximity to the power element 101. Thus, the element temperature of the power element 101 can be accurately detected, and the feedback to the power element 101 can be performed accurately and quickly, so that the power element 101 can be reliably protected.

Further, since the field effect transistor 104 which is not directly related to the detection of the element temperature is provided in a portion different from the substrate on which the power element 101 is provided, the field effect transistor 104 does not affect the detection of the element temperature and Power element 1
01 can be made compact without reducing the effective area of the device.

Next, a case where the semiconductor device of the present embodiment is mounted using a chip frame will be described. As shown in FIG. 22, a semiconductor substrate (semiconductor chip) 201
A power element 101 and a protection diode 102 are formed, and a chip frame 208 is mounted on the outer peripheral portion of the semiconductor substrate 201 as in the first embodiment. This chip frame 208 is
In order to improve the breakdown voltage yield at the time of assembling into the module, the junction termination portion of the semiconductor substrate 201 is covered as in the first embodiment. Further, the chip frame 208
Are provided with a gate wiring pattern 207a, an anode wiring pattern 207b, an emitter wiring pattern 207c, a resistor 203, and an n-channel MOSFET 204.

The gate wiring pattern 207a and the drain electrode of the n-channel MOSFET 204 are electrically connected by a wiring.
Are electrically connected to the anode wiring pattern 207b and the emitter wiring pattern 207c by wiring, respectively. The source electrode of the n-channel MOSFET 204 is electrically connected to the anode wiring pattern 207b via a resistor 203 by wiring. Further, the cathode electrode of the protection diode 102 of the semiconductor substrate 201 (reference numeral 222 in FIG. 23) and the anode electrode (corresponding to 221 in FIG. 23) are respectively connected to the gate wiring pattern 207a and the anode wiring pattern 207b by bonding wires 209a and 209b.
Is electrically connected to The emitter electrode (corresponding to 216 in FIG. 23) and the gate electrode (corresponding to 215 in FIG. 23) of the power element 101 of the semiconductor substrate 201 are provided.
They are electrically connected to the emitter wiring pattern 207c and the gate wiring pattern 207a by bonding wires 209c and 209d, respectively. The collector electrode 207d of the power element 101 is provided on the back surface of the semiconductor substrate 201.

On the other hand, as shown in FIG. 23, an n ⁻ type semiconductor layer 211 is provided on a semiconductor substrate 201, and a p-type region (p-type base region) 212 and a ring-shaped p-type A region (anode region) 219 is selectively formed, and a p ⁻ -type resurf layer (termination region) 223 is formed outside the anode region 219. p
IG as a power element 101
A BT is provided, and a protection diode 102 is provided in each of the anode regions 219.

That is, an n ⁺ -type source region (emitter region, cathode region) 213 is selectively formed on the surface of the p-type base region 212, for example, in a ring shape, and the source region 213 and the n ⁻ -type are formed. P between the semiconductor layers 211
A gate electrode 215 is provided on the surface of the base region 212 of the mold via a gate insulating film 214. The source electrode (emitter electrode, cathode electrode) 216 is provided so as to straddle the source region 213 and the p-type base region 212. A p ⁺ -type drain region (anode region) 217 is formed on the back surface of the semiconductor substrate 201, and a drain electrode (anode electrode) 218 is provided in the drain region 217.

The anode region 219 has an n ⁺ -type cathode region 220 selectively formed on the surface thereof. The anode region 219 and the cathode region 220 are provided with an anode electrode 221 and a cathode electrode 222, respectively. I have.

Further, the gate electrode 2 of the power element 101
Reference numeral 15 denotes a cathode electrode 222 of the protection diode 102.
The gate electrode 215 and the cathode electrode 222 are connected to the gate wiring pattern 207a via the electrode terminal G as described above. The anode electrode 221 of the protection diode 102 and the source electrode (emitter electrode, cathode electrode) 216 of the power element 101 are
As described above, they are connected to the anode wiring pattern 207b and the emitter wiring pattern 207c via the electrode terminal A and the electrode terminal K (E), respectively.

As described above, the protection diode 102 is provided on the semiconductor substrate 201 and the n-channel MOSFET
By providing the element 204 on the upper surface of the chip frame 208, the element temperature of the power element 101 can be accurately detected, and the power element 101 can be reliably protected by accurate and quick feedback to the power element 101. At the same time, it is possible to reduce the size of the entire apparatus without affecting the detection of the element temperature and without reducing the effective area of the power element 101.

The present invention is not limited to the sixth to ninth embodiments. For example, in the above embodiment, an n-channel type I
The present invention has been described by taking the GBT as an example, but the present invention is not limited to this, and the present invention can be applied to, for example, a p-channel IGBT.

In this case, the anode electrode of the protection diode and the drain electrode of the p-channel MOSFET are connected to the gate electrode of the p-channel IGBT,
The source electrode of the p-channel MOSFET is connected to the emitter electrode of the p-channel IGBT. The cathode electrode of the protection diode is connected to the emitter electrode of a p-channel MOSFET via a resistor connected in series, and the cathode electrode is connected to a p-channel MOSFET.
It is also connected to the gate electrode of ET.

Further, the first to fifth embodiments and the sixth to ninth embodiments can be appropriately combined and implemented. In addition, various modifications can be made without departing from the spirit of the present invention.

[0136]

As described above, according to the present invention,
By providing a frame on a semiconductor chip, a semiconductor device and a semiconductor module with high manufacturing yield and high reliability can be provided. Further, by forming a wiring pattern or the like on the frame, a semiconductor module capable of reducing the size and inductance of the module can be provided. Further, according to the present invention, it is possible to provide a semiconductor device capable of protecting the element from destruction in response to a rapid rise in the element temperature or the like.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the structure of the semiconductor module according to the first embodiment of the present invention.

FIG. 3 is a line segment AA ′ of the semiconductor module shown in FIG. 2;
Sectional drawing which shows the cross section in FIG.

FIG. 4 is a sectional view showing a modification of the structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a perspective view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing the structure of a semiconductor module according to a second embodiment of the present invention.

FIG. 7 is a plan view showing the structure of a semiconductor module according to a third embodiment of the present invention.

FIG. 8 is a plan view showing the structure of a semiconductor module according to a fourth embodiment of the present invention.

FIG. 9 is a plan view showing a structure of a semiconductor module according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a sixth embodiment according to the semiconductor device of the present invention.

FIG. 11 is a characteristic diagram showing a reverse current-voltage characteristic of a protection diode for explaining the principle of element protection operation in the semiconductor device of the present invention.

FIG. 12 is a sectional view showing an element structure according to a sixth embodiment of the semiconductor device of the present invention.

FIG. 13 is a circuit diagram showing a seventh embodiment according to the semiconductor device of the present invention.

FIG. 14 is a sectional view showing an element structure according to a seventh embodiment of the semiconductor device of the present invention.

FIG. 15 is a sectional view showing a modification of the element structure according to the seventh embodiment of the semiconductor device of the present invention.

FIG. 16 is a sectional view showing another modification of the element structure according to the seventh embodiment of the semiconductor device of the present invention.

FIG. 17 is a circuit diagram showing an eighth embodiment according to the semiconductor device of the present invention.

FIG. 18 is a sectional view showing an element structure according to an eighth embodiment of the semiconductor device of the present invention.

FIG. 19 is a sectional view showing a modification of the element structure according to the eighth embodiment of the semiconductor device of the present invention.

FIG. 20 is a sectional view showing another modification of the element structure according to the eighth embodiment of the semiconductor device of the present invention.

FIG. 21 is a circuit diagram showing a ninth embodiment according to the semiconductor device of the present invention.

FIG. 22 is a perspective view showing a structure according to a ninth embodiment of the semiconductor device of the present invention.

FIG. 23 is a sectional view showing an element structure according to a ninth embodiment of the semiconductor device of the present invention.

FIG. 24 is a cross-sectional view illustrating an element structure of a temperature detection circuit.

FIG. 25 is a characteristic diagram showing on-current-voltage characteristics of a diode.

FIG. 26 is a cross-sectional view showing the structure of a chip termination portion of a conventional high breakdown voltage semiconductor device.

27A and 27B are a plan view and a cross-sectional view illustrating a structure of a conventional semiconductor module.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n ^- type substrate (n ^- type base layer) 2 ... n-type buffer layer 3 ... p ⁺ type collector layer 4 ... p-type base layer 5 ... n ⁺ type source layer 6 ... collector electrode 7 ... emitter electrode 8 ... gate Electrode 9a: Gate insulating film 9b: Insulating film 9b '... Passivation film 10: Electrode 11: n ⁺ type stopper layer 20: Module substrate 21, 21': Collector wiring pattern 22, 22 ': Emitter wiring pattern 23, 23' 23a 'gate wiring pattern 23b' gate resistance 24a, 24b, 24c emitter bonding wire 24d anode bonding wire 25a, 25b, 25c, 25b 'gate bonding wire 26a, 26b, 26c, 26d collector lead-out portion 27a , 27b, 27c ... Emitter electrode lead-out portions 28a, 28b, 28c Gate electrode lead-out part 30 Semiconductor chip (IGBT) 30 'Semiconductor chip (FRD) 31, 33 Chip frame 32 Adhesive layer 101 Main switching element 102 Protection diode 103 Protection resistor 104 Protection MOSFET 105 ... protection transistor 106 ... protective thyristor 111 ... n ^- -type substrate layer 112 ... p-type anode layer 113 ... n ⁺ -type cathode layer 114 ... p-type well layer 115 ... n ⁺ -type drain layer 116 ... n ⁺ -type source layer 117 ... Anode electrode 118 ... Cathode electrode 119 ... Drain electrode 120 ... Gate electrode 121 ... Gate insulating film 122 ... Source electrode 123 ... N ⁺ type collector layer 124 ... P type base layer 125 ... N ⁺ type emitter layer 126 ... Collector electrode 127 ... Base electrode 128 ... Emitter electrode 129 ... P type Source electrode 130 ... n-type emitter (cathode) layer 131 ... n-type base layer 132 ... p-type emitter (anode) layer 133 ... cathode electrode 134: anode electrode 135 ... base electrode 219 ... p-type ring layer 223 ... p ^- -type RESURF layer

Claims (30)

[Claims] 1. A semiconductor device comprising: a high-breakdown-voltage semiconductor element and a junction termination region provided on a semiconductor substrate; and an insulating frame provided on an outer peripheral portion of the semiconductor substrate so as to cover the junction termination region. Semiconductor device. 2. A semiconductor device comprising: a high-breakdown-voltage semiconductor element and a junction termination region provided on a semiconductor substrate; and an insulating frame provided to cover the junction termination region and an outer peripheral end of the semiconductor substrate. Semiconductor device. 3. An insulating or semi-insulating first film is formed between the semiconductor substrate and the insulating frame so as to cover a surface of the semiconductor substrate. 3. The electrode according to claim 1, wherein an opening is provided, and an electrode of the high breakdown voltage semiconductor element and an electrode of the junction termination region are formed from the bottom of the opening to the first film. Semiconductor device. 4. The semiconductor device according to claim 3, wherein an insulating second film is formed between said first film and said insulating frame. 5. The semiconductor device according to claim 4, wherein said second film is formed to cover an outer peripheral end of said semiconductor substrate. 6. The second film is formed so as to cover the first film, the electrode of the high-breakdown-voltage semiconductor element, and the electrode of the junction termination region, and has a flat upper surface. The semiconductor device according to claim 4, wherein: 7. The semiconductor device according to claim 1, wherein the insulating frame is made of a resin. 8. The resin according to claim 7, wherein the resin is a resin selected from silicone and polyetherimide.
13. The semiconductor device according to claim 1. 9. A semiconductor device comprising: a wiring substrate; and a semiconductor device provided on the wiring substrate. The semiconductor device covers a high breakdown voltage semiconductor element and a junction termination region provided on the semiconductor substrate, and covers the junction termination region. And an insulating frame provided on an outer peripheral portion of the semiconductor substrate, wherein an electrode of the high breakdown voltage semiconductor element and an electrode of the wiring substrate are electrically connected via the insulating frame. Characteristic semiconductor module. 10. A semiconductor device comprising: a wiring substrate; and a plurality of semiconductor devices arranged on the wiring substrate. Each of the plurality of semiconductor devices includes a high breakdown voltage semiconductor element provided on the semiconductor substrate and a junction termination. A region, and an insulating frame provided on the outer peripheral portion of the semiconductor substrate so as to cover the junction termination region, wherein the electrode of the high breakdown voltage semiconductor element and the electrode of the wiring substrate pass through the insulating frame. A semiconductor module, which is electrically connected. 11. The semiconductor module according to claim 9, wherein an electrode of said high breakdown voltage semiconductor element and an electrode of said wiring board are electrically connected by a bonding wire. 12. A conductive film is provided on the insulating frame, and an electrode of the high breakdown voltage semiconductor element and an electrode of the wiring substrate are electrically connected through the conductive film. The semiconductor module according to claim 9, wherein: 13. An adjacent semiconductor device among the plurality of semiconductor devices is provided with a conductive plate for electrically connecting a conductive film provided on each insulating frame in contact with the conductive film. The semiconductor module according to claim 12, wherein: 14. The semiconductor module according to claim 13, wherein an electrode of said high breakdown voltage semiconductor element and said conductive film are electrically connected by a bonding wire. 15. An electrode of the high-breakdown-voltage semiconductor element is pulled out to a position on an upper surface of the insulating frame by a conductive pin or a block member, and the insulating layer is provided between adjacent semiconductor devices among the plurality of semiconductor devices. The semiconductor module according to claim 10, wherein the semiconductor modules are electrically connected to each other via a conductive plate provided on the conductive frame. 16. An insulating or semi-insulating first film is formed between the semiconductor substrate and the insulating frame so as to cover the surface of the semiconductor substrate. 11. The opening according to claim 9, wherein an electrode of the high breakdown voltage semiconductor element and an electrode of the junction termination region are formed from the bottom of the opening to the first film. 12. Semiconductor module. 17. The semiconductor module according to claim 16, wherein an insulating second film is formed between said first film and said insulating frame. 18. The semiconductor device according to claim 1, wherein the second film is formed to cover an outer peripheral end of the semiconductor substrate.
8. The semiconductor module according to 7. 19. The second film is formed so as to cover the first film, the electrode of the high-breakdown-voltage semiconductor element, and the electrode of the junction termination region, and has a flat upper surface. 19. The semiconductor module according to claim 17, wherein: 20. The semiconductor module according to claim 9, wherein said insulating frame is made of resin. 21. The semiconductor module according to claim 20, wherein said resin is a resin selected from silicone and polyetherimide. 22. A main switching element provided on a semiconductor substrate and comprising a high-voltage main electrode, a low-voltage main electrode, and a gate electrode; and the gate electrode and the high-voltage main electrode of the main switching element. Between the low-voltage side main electrode, a diode inserted in a direction to which a reverse voltage is applied when the main switching element is in an ON state, the gate electrode of the main switching element and the high-voltage side main electrode or A control switching element inserted between the main switching element and the low-voltage side main electrode, wherein when the main switching element is in an ON state and the element temperature rises, an increase in a reverse leakage current flowing through the diode is reduced. A semiconductor device, wherein the control switching element is turned on by detecting the leakage current. 23. A main switching element provided on a semiconductor substrate, the main switching element having a high voltage side main electrode, a low voltage side main electrode, and a first gate electrode, and a resistor connected to the low voltage side main electrode of the main switching element. An anode electrode connected to the first gate electrode, a cathode electrode connected to the first gate electrode, a source electrode, a drain electrode, and a second gate electrode; and the second electrode connected to the anode electrode of the diode.
And a field-effect transistor in which the source electrode is connected to the low-voltage side main electrode of the main switching element, and the drain electrode is connected to the first gate electrode. Semiconductor device. 24. A main switching element provided on a semiconductor substrate, the main switching element including a high-voltage main electrode, a low-voltage main electrode, and a first gate electrode, and the first switching element of the main switching element.
A diode having a cathode electrode connected to the gate electrode thereof, an emitter electrode, a collector electrode, and a base electrode, the base electrode being connected to the anode electrode of the diode, and a low voltage side main electrode of the main switching element. A bipolar transistor having the emitter electrode connected thereto and the collector electrode connected to the first gate electrode. 25. A semiconductor device comprising: a main switching element provided on a semiconductor substrate, the main switching element including a high-voltage side main electrode, a low-voltage side main electrode, and a first gate electrode; an anode electrode, a base electrode, and a cathode electrode; A thyristor in which the anode electrode is connected to the first gate electrode of the main switching element, and the cathode electrode is connected to a low-voltage main electrode of the main switching element, and an anode electrode is connected to a base electrode of the thyristor. , The first of the main switching elements
A diode in which a cathode electrode is connected to a gate electrode of the semiconductor device. 26. The semiconductor device according to claim 22, wherein said main switching element and said diode are provided on the same semiconductor substrate. 27. The semiconductor device according to claim 22, wherein the control switching element is provided outside the semiconductor substrate. 28. The pressure contact package is attached to the semiconductor substrate, and the control switching element is provided on the pressure contact package.
13. The semiconductor device according to claim 1. 29. The semiconductor device according to claim 27, wherein said semiconductor device is mounted on a wiring board, and said control switching element is provided on said wiring board. 30. A main switching element provided on a semiconductor substrate and having a high-voltage main electrode, a low-voltage main electrode, and a gate electrode; and a gate electrode of the main switching element provided on the semiconductor substrate. A diode inserted between the high-voltage-side main electrode and the low-voltage-side main electrode in a direction in which a reverse voltage is applied when the main switching element is in an on state; and a junction termination provided on the semiconductor substrate. Region, an insulating frame provided on the outer peripheral portion of the semiconductor substrate covering the junction termination region, and provided on the insulating frame, the gate electrode and the high voltage side main electrode of the main switching element or A control switching element inserted between the main switching element and a low-voltage side main electrode. A semiconductor device characterized by detecting an increase in a reverse leak current flowing through an ode and turning on the control switching element by the leak current.