JP2020035946A - Semiconductor device for electric power, power conversion device, manufacturing method for semiconductor device for electric power and manufacturing method for power conversion device - Google Patents

Abstract

To provide a semiconductor device capable of suppressing degradation in the insulation reliability of a semiconductor device by improving heat radiation performance in an ineffective region of a semiconductor element.SOLUTION: The semiconductor device for electric power includes: a semiconductor element (2) disposed on a top face of an insulation substrate (5) through a junction layer (3); a first top face heat dissipation member (4a) partially formed on the top face of the semiconductor element. The semiconductor element has a cell region (101) and an ineffective region (102) surrounding the cell region in plan view. The first top face heat dissipation member is formed on the top face corresponding to the ineffective region of the semiconductor element.SELECTED DRAWING: Figure 3

Description

  The technology disclosed in the present specification relates to a power semiconductor device, a power converter, a method for manufacturing a power semiconductor device, and a method for manufacturing a power converter.

  High-breakdown-voltage semiconductor elements used in power semiconductor devices are classified into a cell region through which a large current flows during operation of the power semiconductor device, and an ineffective region surrounding the cell region in plan view.

  Here, the ineffective region is used to prevent dielectric breakdown in the semiconductor element even when the rated withstand voltage is applied between the front electrode and the back electrode of the semiconductor element when the power semiconductor device is not operating. This is a region where a structure, that is, a withstand voltage structure such as a guard ring, a field limiting ring (FLR), or a variation of lateral doping (VLD) is formed.

  In a conventional power semiconductor device, metal wiring is formed on the upper and lower surfaces of a ceramic plate made of silicon nitride or the like and having heat dissipation and insulation properties. The lower surface of the semiconductor element is joined to the upper surface of the ceramic plate, and the heat sink is joined to the lower surface of the ceramic plate. With such a configuration, heat generated in the semiconductor element can be dissipated through the heat sink.

  In addition, if there is a portion of the semiconductor element where the amount of heat generation exceeds the amount of heat radiation, the temperature rise of the semiconductor element cannot be suppressed.

  Therefore, for example, as shown in Patent Document 1, the bonding layer formed between the semiconductor element and the metal wiring on the upper surface of the substrate is different from the portion located in the peripheral portion of the semiconductor element in plan view. In the case where the semiconductor element is turned on, the current concentrates on a portion having a low electric resistivity, and the current is locally concentrated. Temperature can be suppressed from occurring.

JP-A-2007-201314

  When the size of the ineffective area varies due to dimensional tolerances or the like generated in the manufacturing process of the semiconductor element, when the power semiconductor device is not operating, a voltage is applied between the front surface and the back surface of the semiconductor device so that the back surface has a high voltage. The voltage causes a local area where the leak current increases in the invalid area.

  As a result, during a non-operation time when a high voltage is applied between the front surface electrode and the back surface electrode of the semiconductor element, a local heat generation amount in an ineffective region of the semiconductor element due to a leak current exceeds a heat radiation amount. Then, the temperature may locally increase in the semiconductor element.

  Then, there is a problem that the withstand voltage of the semiconductor element decreases, that is, the insulation reliability of the semiconductor element decreases.

  In the semiconductor device disclosed in Patent Document 1, when a semiconductor element is turned on, a current flowing in a cell region is concentrated on a portion having a low electric resistivity, so that a local temperature rise occurs in the cell region. Is suppressed. However, such an effect cannot be expected in the invalid area.

  Therefore, since a local temperature rise in the ineffective region cannot be suppressed, there has been a problem that the insulation reliability of the semiconductor device is reduced due to individual differences between semiconductor elements.

  The technology disclosed in the specification of the present application has been made in order to solve the problems described above, and by improving heat dissipation in an ineffective region of a semiconductor element, the insulation reliability of a semiconductor device has been improved. It is an object of the present invention to provide a technique capable of suppressing the reduction.

  A first aspect of the technology disclosed in the specification of the present application is a semiconductor element disposed on an upper surface of an insulating substrate via a bonding layer, and a first upper surface heat radiation member partially formed on the upper surface of the semiconductor element. Wherein the semiconductor element has a cell area and an ineffective area surrounding the cell area in plan view, and the first upper surface heat dissipation member is formed on an upper surface corresponding to the ineffective area of the semiconductor element. Is done.

  According to a second aspect of the technology disclosed in the specification of the present application, there is provided a conversion circuit that includes the power semiconductor device described above, converts an input power and outputs the power, and drives the power semiconductor device. A driving circuit for outputting a driving signal to the power semiconductor device, and a control circuit for outputting a control signal for controlling the driving circuit to the driving circuit.

  According to a third aspect of the technology disclosed in the specification of the present application, a semiconductor element is disposed on an upper surface of an insulating substrate via a bonding layer, and a first upper surface heat radiation member is partially disposed on the upper surface of the semiconductor element. Wherein the semiconductor element has a cell region and an ineffective region surrounding the cell region in plan view, and the first upper surface heat radiation member is formed on an upper surface corresponding to the ineffective region of the semiconductor element. Is done.

  A fourth aspect of the technology disclosed in the specification of the present application includes a power semiconductor device manufactured by the above manufacturing method, and further includes a conversion circuit that converts input power and outputs the converted power. A drive circuit for outputting a drive signal for driving the power semiconductor device to the power semiconductor device is provided, and a control circuit for outputting a control signal for controlling the drive circuit to the drive circuit is provided.

  A first aspect of the technology disclosed in the specification of the present application is a semiconductor element disposed on an upper surface of an insulating substrate via a bonding layer, and a first upper surface heat radiation member partially formed on the upper surface of the semiconductor element. Wherein the semiconductor element has a cell area and an ineffective area surrounding the cell area in plan view, and the first upper surface heat dissipation member is formed on an upper surface corresponding to the ineffective area of the semiconductor element. Is what is done. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member. Therefore, a decrease in insulation reliability of the power semiconductor device can be suppressed.

  According to a second aspect of the technology disclosed in the specification of the present application, there is provided a conversion circuit that includes the power semiconductor device described above, converts an input power and outputs the power, and drives the power semiconductor device. A driving circuit for outputting a driving signal to the power semiconductor device, and a control circuit for outputting a control signal for controlling the driving circuit to the driving circuit. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member.

  According to a third aspect of the technology disclosed in the specification of the present application, a semiconductor element is disposed on an upper surface of an insulating substrate via a bonding layer, and a first upper surface heat radiation member is partially disposed on the upper surface of the semiconductor element. Wherein the semiconductor element has a cell region and an ineffective region surrounding the cell region in plan view, and the first upper surface heat radiation member is formed on an upper surface corresponding to the ineffective region of the semiconductor element. Is done. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member. Therefore, a decrease in insulation reliability of the power semiconductor device can be suppressed.

  A fourth aspect of the technology disclosed in the specification of the present application includes a power semiconductor device manufactured by the above manufacturing method, and further includes a conversion circuit that converts input power and outputs the converted power. A drive circuit for outputting a drive signal for driving the power semiconductor device to the power semiconductor device is provided, and a control circuit for outputting a control signal for controlling the drive circuit to the drive circuit is provided. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member.

  Further, objects, features, aspects, and advantages of the technology disclosed in the present specification will become more apparent from the detailed description given below and the accompanying drawings.

FIG. 2 is a cross-sectional view schematically illustrating an example of a structure of a semiconductor element used in a power semiconductor device according to the embodiment; FIG. 1 is a plan view schematically showing an example of a structure of a power semiconductor device according to an embodiment. It is sectional drawing in A-A 'of FIG. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 1 is a cross-sectional view schematically illustrating an example of a structure of a power semiconductor device according to an embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 1 is a cross-sectional view schematically illustrating an example of a structure of a power semiconductor device according to an embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. It is sectional drawing which shows the example of the arrangement | positioning position of the heat radiation member in the lower surface of a semiconductor element. FIG. 2 is a cross-sectional view schematically showing an example of the structure of the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 1 is a cross-sectional view schematically illustrating an example of a structure of a power semiconductor device according to an embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a method of manufacturing the power semiconductor device according to the embodiment. 1 is a diagram conceptually illustrating an example of a configuration of a power conversion system including a power conversion device according to an embodiment.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  The drawings are schematically shown, and for convenience of explanation, the configuration is omitted or simplified as appropriate. Further, the relationship between the size and the position of the configuration and the like shown in the different drawings is not necessarily accurately described, and can be appropriately changed. Further, hatching may be applied to drawings such as plan views which are not cross-sectional views so as to facilitate understanding of the contents of the embodiments.

  In the following description, the same components are denoted by the same reference numerals, and their names and functions are the same. Therefore, a detailed description thereof may be omitted to avoid duplication.

  Further, in the following description, a specific position and direction such as “up”, “down”, “left”, “right”, “side”, “bottom”, “front” or “back” are referred to. Even when terms that mean are sometimes used, these terms are used for the sake of convenience to facilitate understanding of the contents of the embodiments, and are not related to the direction in which the terms are actually implemented. It does not.

  Further, in the following description, even when an ordinal number such as “first” or “second” may be used, these terms are used to understand the contents of the embodiments. It is used for convenience for the sake of simplicity, and is not limited to the order that can be generated by these ordinal numbers.

<First embodiment>
Hereinafter, a power semiconductor device and a method of manufacturing the power semiconductor device according to the present embodiment will be described.

<About the configuration of the power semiconductor device>
Insulated gate bipolar transistor (i.e., IGBT), metal-oxide-semiconductor field-effect transistor (i.e., MOSFET), or the power of a semiconductor device such as a diode. In a power semiconductor device mounted as an element, a large current flows through the semiconductor element during operation. Therefore, the semiconductor element generates heat.

  If the temperature of the semiconductor element continues to rise due to heat generation, the rectifying property of the semiconductor element is lost. Then, it becomes difficult to control the power semiconductor device.

  2. Description of the Related Art In a conventional power semiconductor device, an insulating substrate is used in which metal wiring such as a copper pattern is formed on the upper and lower surfaces of a ceramic plate made of silicon nitride or the like and having heat dissipation and insulation properties.

  Then, in order to suppress a rise in temperature of the semiconductor element, the lower surface of the semiconductor element was bonded to the upper surface of the insulating substrate via a bonding layer made of solder or the like, thereby ensuring heat dissipation of the semiconductor element. (See, for example, Patent Document 1).

  Here, FIG. 1 is a sectional view schematically showing an example of the structure of a semiconductor element used in the power semiconductor device according to the present embodiment.

  As illustrated in FIG. 1, the semiconductor element 2 is divided into a cell region 101 through which a current flows when the semiconductor element 2 operates, and an invalid region 102 surrounding the cell region 101 in plan view.

  In the cell region 101, the n− type semiconductor layer 110, the p− type semiconductor layer 111 partially formed in the surface layer of the n− type semiconductor layer 110, and the p− type semiconductor layer 111 A partially formed n + -type semiconductor layer 112, a p + -type semiconductor layer 113 formed through the n + -type semiconductor layer 112, and an n + -type semiconductor layer on the upper surface of the n − -type semiconductor layer 110 A gate oxide film 114 formed so as to cover the p − type semiconductor layer 111 sandwiched between the n − type semiconductor layer 110 and the n − type semiconductor layer 110; a gate electrode 115 formed on the upper surface of the gate oxide film 114; An insulating film 116 formed over the gate electrode 115 and the gate electrode 115; an insulating film 116, the exposed n + type semiconductor layer 112 and the exposed p + type semiconductor layer 113; And the emitter electrode 117 is provided.

  Further, in the invalid region 102, the n − type semiconductor layer 110, the p − type semiconductor layer 111, and a part of the surface layer of the n − type semiconductor layer 110 on the outer peripheral side of the p − type semiconductor layer 111. A p- type semiconductor layer 121 formed on the outer surface and an n + type semiconductor layer 122 partially formed on the surface layer of the n- type semiconductor layer 110 on the outer peripheral side of the p- type semiconductor layer 121. An insulating film 116 formed to cover the p − type semiconductor layer 111, the p − type semiconductor layer 121 and the n + type semiconductor layer 122, and an insulating protective film 123 formed on the upper surface of the insulating film 116. Is provided.

  Here, the ineffective region 102 does not cause dielectric breakdown in the semiconductor element 2 even when the rated withstand voltage is applied between the front surface electrode and the back surface electrode of the semiconductor element 2 when the semiconductor element 2 is not operating. , That is, a region where a breakdown voltage structure such as a guard ring, FLR, or VLD is formed.

  On the other hand, if there is a portion in the semiconductor element 2 where the amount of heat generation exceeds the amount of heat radiation, the temperature rise of the semiconductor element 2 cannot be suppressed.

  For example, as shown in Patent Document 1, a bonding layer formed between a semiconductor element and a metal wiring on an upper surface of a substrate has a semiconductor layer in a plan view and a portion located in a peripheral portion of the semiconductor element. Due to the material composition having a different tensile strength from the portion located at the center of the device, when the semiconductor device is turned on, current concentrates on the portion with low electrical resistivity, and the temperature locally increases. The rise can be suppressed.

Here, if the size of the ineffective area varies due to a dimensional tolerance or the like generated during the manufacturing process of the semiconductor element, when the power semiconductor device is not operated (for example, in the case of a MOSFET, the voltage applied to the gate electrode is lower than the threshold value). At a low level), a voltage applied between the front surface and the back surface of the semiconductor element so that the back surface side has a high voltage causes a local area (for example, 1 μm ² or more, where the leakage current is large in the invalid region, and , 50 μm ² or less).

  This is because, in the invalid area, the electric field strength in the small-sized area is higher than the electric field strength in the large-sized area.

  As a result, during a non-operation time when a high voltage is applied between the front surface electrode and the back surface electrode of the semiconductor element, a local heat generation amount in an ineffective region of the semiconductor element due to a leak current exceeds a heat radiation amount. Then, the temperature may locally increase in the semiconductor element.

  As the temperature in the invalid region of the semiconductor element increases, the leakage current further increases. Then, the insulation reliability of the power semiconductor device decreases.

  In the semiconductor device disclosed in Patent Document 1, when a semiconductor element is turned on, a current flowing in a cell region is concentrated on a portion having a low electric resistivity, so that a local temperature rise occurs in the cell region. Is suppressed. However, the thermal conductivity of the material exemplified in Patent Literature 1 is, for example, about the same as that of the solder joining the central part of the semiconductor element, and the thermal conductivity in the peripheral part of the semiconductor element (that is, the ineffective area). It is not as effective as increasing the conductivity. Therefore, the effect of suppressing the temperature rise in the ineffective region of the semiconductor element cannot be expected, and the insulation reliability of the semiconductor device decreases.

  Therefore, in the present embodiment, in order to solve the above-described problem, the heat dissipation in the ineffective region of the semiconductor element is increased, so that the insulation of the power semiconductor device due to the variation in the size of the ineffective region of the semiconductor element is improved. A power semiconductor device capable of suppressing a decrease in reliability will be described.

  FIG. 2 is a plan view schematically showing an example of the structure of the power semiconductor device according to the present embodiment. FIG. 3 is a sectional view taken along line A-A 'in FIG.

  As shown in FIGS. 2 and 3, the power semiconductor device 1 includes a metal film 7 a, a ceramic plate 8 formed on the upper surface of the metal film 7 a, and a ceramic plate 8 partially formed on the upper surface of the ceramic plate 8. Metal film 7b, a bonding layer 3 partially formed on the upper surface of the metal film 7b, the semiconductor element 2 disposed on the upper surface of the bonding layer 3, and the inactive region of the upper surface of the semiconductor element 2 The heat radiating member 4 a formed at the location, the metal wire 9 connected to the upper surface of the semiconductor element 2, and the sealing material 6 (not shown in FIG. 2) for sealing these components are provided. Prepare. Here, the metal film 7a, the ceramic plate 8 and the metal film 7b form the insulating substrate 5.

  Further, the heat radiating member 4 a improves heat radiating property in an ineffective area of the semiconductor element 2. The semiconductor element 2 is, for example, an IGBT. In addition, an insulative protective film 123 (see FIG. 1) made of, for example, a polyimide resin material is formed in the invalid region of the semiconductor element 2. The bonding layer 3 is, for example, solder. The sealing material 6 is, for example, an insulating silicone gel.

<About the manufacturing method of the power semiconductor device>
Next, a method for manufacturing the power semiconductor device according to the present embodiment will be described below. Here, FIGS. 4 to 8 are diagrams showing a method of manufacturing the power semiconductor device according to the present embodiment.

  First, as shown in FIG. 4, a ceramic plate 8 is formed on the upper surface of the metal film 7a. Further, the metal film 7b is partially formed on the upper surface of the ceramic plate 8.

  Next, as shown in FIG. 4, the bonding layer 3 is partially formed on the upper surface of the metal film 7b. Here, the bonding layer 3 is, for example, a plate solder. Further, as shown in FIG. 5, the semiconductor element 2 is arranged on the upper surface of the bonding layer 3.

  Next, as illustrated in FIG. 5, the semiconductor element 2 and the metal film 7b are joined by heating the semiconductor element 2 and the bonding layer 3. Here, the semiconductor element 2 has a cell region and an invalid region surrounding the cell region in plan view.

  Next, as shown in an example in FIG. 6, the heat radiating member 4 a is arranged in an invalid area of the semiconductor element 2. Then, as shown in FIG. 7, a metal wire connected to the semiconductor element 2 in order to obtain electrical continuity between the semiconductor element 2 and a main circuit for flowing a large current through the semiconductor element 2 9 is formed.

  Next, as shown in FIG. 8, a power semiconductor device according to the present embodiment is manufactured by forming an insulating sealing material 6 covering the formed structure.

  Here, as the insulating sealing material 6, for example, silicone gel or elastomer is used. The thermal conductivity of the sealing material 6 is, for example, 0.15 W / m · K.

  In the present embodiment, a heat radiating member 4 a is interposed between the ineffective region of the semiconductor element 2 and the sealing material 6. Therefore, the heat dissipation of the ineffective region of the semiconductor element 2 can be improved. Then, it is possible to prevent the insulation reliability of the power semiconductor device from being lowered due to the generation of heat in the ineffective region of the semiconductor element 2.

  The heat dissipation member 4a is capable of withstanding a high voltage applied between the emitter electrode 117 (see FIG. 1) formed on the upper surface of the semiconductor element 2 and the collector electrode formed on the lower surface of the semiconductor element 2. Any insulator having a withstand voltage of, for example, 1 kV / mm or more and 15 kV / mm or less may be used, and an insulator having a higher thermal conductivity is more desirable. In particular, those having a thermal conductivity of 10 W / m · K or more are preferable.

  Further, when the state of the heat radiating member 4a when it is arranged on the upper surface of the semiconductor element 2 is a liquid phase, it is difficult to arrange the heat radiating member 4a only in the ineffective area of the semiconductor element 2. It is.

  When the heat radiating member 4a is in the liquid phase, the liquid heat radiating member 4a may flow into the cell region of the semiconductor element 2, and in this case, the metal is transferred to the emitter electrode 117 (see FIG. 1) of the semiconductor element 2. The area for joining the wires 9 may be lost.

  Therefore, it is desirable that the heat radiating member 4a be in a solid state when disposed on the upper surface of the semiconductor element 2.

  On the other hand, the heat dissipating member 4a may be a material having a viscosity of 150 Pa · s or more, even if the heat dissipating member 4a is in a liquid state when disposed on the upper surface of the semiconductor element 2. The heat dissipating member 4a satisfying such conditions includes, for example, a heat dissipating sheet PK-95 manufactured by Asahi Rika Kagaku Corporation or a heat conductive sheet TG-X manufactured by T-GLOBAL.

The area where the heat radiating member 4a contacts the semiconductor element 2 is a local area where heat generation is assumed to occur in the ineffective region, for example, 10 times as large as a range of 1 μm ² or more and 50 μm ² or less. It is desirable that the range be, for example, 10 μm ² or more and 500 μm ² or less.

<Second embodiment>
A power semiconductor device according to the present embodiment and a method for manufacturing the power semiconductor device will be described. In the following description, the same components as those described in the above-described embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate. .

<About the configuration of the power semiconductor device>
FIG. 9 is a sectional view schematically showing an example of the structure of the power semiconductor device according to the present embodiment.

  As shown in FIG. 9, the power semiconductor device 1a includes a metal film 7a, a ceramic plate 8, a metal film 7b, a bonding layer 3, a semiconductor element 2, a heat radiating member 4a, and a metal wire 9a. A heat dissipating member 4b formed on the upper surface of the heat dissipating member 4a and made of a material having a higher thermal conductivity than the heat dissipating member 4a; and a sealing material 6 for sealing these components.

  Here, the semiconductor element 2 is, for example, a MOSFET. In addition, an insulative protective film 123 (see FIG. 1) made of, for example, a polyimide resin material is formed in the invalid region of the semiconductor element 2. The bonding layer 3 is, for example, solder. The sealing material 6 is, for example, an insulating silicone gel.

<About the manufacturing method of the power semiconductor device>
Next, a method for manufacturing the power semiconductor device according to the present embodiment will be described below. Here, FIGS. 10 to 15 are views showing a method of manufacturing the power semiconductor device according to the present embodiment.

  First, as shown in FIG. 10, a ceramic plate 8 is formed on the upper surface of the metal film 7a. Further, the metal film 7b is partially formed on the upper surface of the ceramic plate 8.

  Next, as shown in FIG. 10, the bonding layer 3 is partially formed on the upper surface of the metal film 7b. Here, the bonding layer 3 is, for example, a plate solder. Further, as shown in FIG. 11, the semiconductor element 2 is disposed on the upper surface of the bonding layer 3.

  Next, as shown in FIG. 11, the semiconductor element 2 and the metal film 7b are joined by heating the semiconductor element 2 and the bonding layer 3.

  Next, as shown in an example in FIG. 12, the heat radiating member 4 a is arranged in the invalid area of the semiconductor element 2. Then, as shown in FIG. 13, the heat radiating member 4b is arranged on the upper surface of the heat radiating member 4a. Here, the heat dissipating member 4 b is arranged apart from the semiconductor element 2.

  Next, as shown in FIG. 14, in order to obtain electrical conduction between the semiconductor element 2 and a main circuit for flowing a large current through the semiconductor element 2, a metal connected to the semiconductor element 2 is used. The wire 9 is formed.

  Next, as shown in an example in FIG. 15, a power semiconductor device according to the present embodiment is manufactured by forming an insulating sealing material 6 covering the formed structure.

  In the present embodiment, a heat dissipating member 4a and a heat dissipating member 4b having higher thermal conductivity than the heat dissipating member 4a are interposed between the ineffective region of the semiconductor element 2 and the sealing material 6. Therefore, the heat dissipation of the ineffective region of the semiconductor element 2 can be improved. Then, it is possible to prevent the insulation reliability of the power semiconductor device from being lowered due to the generation of heat in the ineffective region of the semiconductor element 2.

  The heat dissipating member 4b has a thermal conductivity higher than 100 W / m · K, for example, a metal material such as silver, copper, gold, titanium, iron, nickel or aluminum, aluminum nitride, silicon nitride, or the like. A ceramic material, diamond, or graphite is desirable.

  When the thickness of the heat radiating member 4a is small, when a high voltage is applied to the source electrode on the drain electrode side of the semiconductor element 2, the heat radiating member 4a passes through the conductive heat radiating member 4b and discharges. An electrical short may occur.

  Therefore, it is preferable that the heat radiating member 4 a has a thickness that does not cause the above-described electrical short circuit in accordance with the rated withstand voltage of the semiconductor element 2.

  For example, when the withstand voltage of the semiconductor element 2 is 3 kV, it is desirable that the thickness of the heat radiation member 4 a is 1 mm or more. According to such a configuration, heat generation in the invalid region of the semiconductor element 2 can be reliably suppressed.

<Third embodiment>
A power semiconductor device according to the present embodiment and a method for manufacturing the power semiconductor device will be described. In the following description, the same components as those described in the above-described embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate. .

<About the configuration of the power semiconductor device>
FIG. 16 is a sectional view schematically showing an example of the structure of the power semiconductor device according to the present embodiment.

  As illustrated in FIG. 16, the power semiconductor device 1b includes a metal film 7a, a ceramic plate 8, a metal film 7b, a bonding layer 3, a semiconductor element 2, a heat dissipation member 4a, and a metal wire 9a. And a heat radiating member 4b, a heat radiating member 4c formed on the lower surface of the semiconductor element 2 and made of a material having a higher thermal conductivity than the bonding layer 3, and a sealing material 6 for sealing these components.

  Here, the heat dissipating member 4c is formed at a position overlapping the invalid area of the semiconductor element 2 in a plan view. On the other hand, the bonding layer 3 is formed at a position overlapping the cell region of the semiconductor element 2.

  The semiconductor element 2 is, for example, a diode. In addition, an insulative protective film 123 (see FIG. 1) made of, for example, a polyimide resin material is formed in the invalid region of the semiconductor element 2. The bonding layer 3 is, for example, solder. The sealing material 6 is, for example, an insulating silicone gel.

<About the manufacturing method of the power semiconductor device>
Next, a method for manufacturing the power semiconductor device according to the present embodiment will be described below. Here, FIGS. 17 to 23 are views showing a method of manufacturing the power semiconductor device according to the present embodiment.

  First, as shown in FIG. 17, a ceramic plate 8 is formed on the upper surface of the metal film 7a. Further, the metal film 7b is partially formed on the upper surface of the ceramic plate 8.

  Next, as illustrated in FIG. 17, the heat radiation member 4c is partially formed on the upper surface of the metal film 7b. Here, the heat radiating member 4c is formed at a position overlapping with an ineffective area of the semiconductor element 2 to be arranged in a later step in plan view. The heat radiation member 4c is formed intermittently in the circumferential direction, as shown in an example in FIG. Note that the heat dissipation member 4c in FIG. 17 has two missing portions on each side, but the number and positions of the missing portions are not limited to those shown in FIG.

  Next, as shown in FIG. 18, the bonding layer 3 is formed on the upper surface of the metal film 7b in a region surrounded by the heat radiating member 4c in plan view. Here, the bonding layer 3 is, for example, a plate solder. Further, as shown in FIG. 19, the semiconductor element 2 is arranged on the upper surface of the bonding layer 3 and the upper surface of the heat radiating member 4c.

  Next, as shown in an example in FIG. 19, the semiconductor element 2 and the metal film 7b are joined by heating the semiconductor element 2 and the bonding layer 3.

  Next, as shown in an example in FIG. 20, the heat radiating member 4a is arranged in the invalid area of the semiconductor element 2. Then, as shown in an example in FIG. 21, the heat radiating member 4b is arranged on the upper surface of the heat radiating member 4a. Here, the heat dissipating member 4 b is arranged apart from the semiconductor element 2.

  Next, as shown in FIG. 22, a metal connected to the semiconductor element 2 in order to obtain electrical continuity between the semiconductor element 2 and a main circuit for flowing a large current through the semiconductor element 2. The wire 9 is formed.

  Next, as shown in an example in FIG. 23, a power semiconductor device according to the present embodiment is manufactured by forming an insulating sealing material 6 covering the formed structure.

  When bonding the semiconductor element 2 and the metal film 7b, the bonding layer 3 (that is, solder) expands with heating. When the semiconductor element 2 is pushed up in the vertical direction by the expansion of the bonding layer 3 (that is, the solder), the lower surface of the semiconductor element 2 may be separated from the heat radiation member 4c. Therefore, in order to prevent this, the heat radiation member 4c is formed intermittently in the circumferential direction.

  In the present embodiment, a heat dissipating member 4a and a heat dissipating member 4b having higher thermal conductivity than the heat dissipating member 4a are interposed between the ineffective region of the semiconductor element 2 and the sealing material 6. Therefore, the heat dissipation of the ineffective region of the semiconductor element 2 can be improved. Then, it is possible to prevent the insulation reliability of the power semiconductor device from being lowered due to the generation of heat in the ineffective region of the semiconductor element 2.

  The heat dissipating member 4c made of a material having a higher thermal conductivity than the bonding layer 3 is formed in contact with the lower surface of the semiconductor element 2 at a position overlapping the ineffective area of the semiconductor element 2 in a plan view, so that the semiconductor element 2 The heat radiation of the ineffective region can be further improved. Then, even if there are variations in dimensions due to individual differences of the semiconductor elements 2, it is possible to suppress a decrease in insulation reliability of the power semiconductor device.

  Note that the thermal conductivity of the bonding layer 3 is, for example, 40 W / m · K or more and 60 W / m · K or less. It is preferable that the heat radiating member 4 c be made of a material having a higher thermal conductivity than the bonding layer 3. The heat dissipation member 4c is preferably made of, for example, a metal material such as gold, silver or copper, a ceramic material such as aluminum nitride or silicon nitride, or a graphite sheet.

  If the heat radiating member 4c is formed to reach a position on the lower surface of the semiconductor element 2 that overlaps the cell region of the semiconductor element 2 in plan view, contact resistance during operation of the semiconductor element 2 increases. Then, the on-resistance of the semiconductor element 2 increases, so that it is not preferable that the heat radiation member 4c is formed to reach a position on the lower surface of the semiconductor element 2 that overlaps the cell region of the semiconductor element 2 in plan view. .

  FIG. 24 is a cross-sectional view illustrating an example of an arrangement position of the heat radiation member on the lower surface of the semiconductor element. As shown in FIG. 24, the heat dissipating member 4 c has a width d in the radial direction from the outer peripheral end face of the semiconductor element 2 with respect to the radial width D of the ineffective region 102 of the semiconductor element 2 in plan view. Preferably, it is formed. Here, the width D is larger than the width d, and the smaller the difference between the width D and the width d, the better.

  In the present embodiment, a configuration in which all of the heat radiating members 4a, 4b, and 4c are provided is shown. However, for example, the heat radiating member 4b may not be provided.

<Fourth embodiment>
A power semiconductor device according to the present embodiment and a method for manufacturing the power semiconductor device will be described. In the following description, the same components as those described in the above-described embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate. .

<About the configuration of the power semiconductor device>
FIG. 25 is a sectional view schematically showing an example of the structure of the power semiconductor device according to the present embodiment.

  As shown in FIG. 25, the power semiconductor device 1c includes a metal film 7a, a ceramic plate 8, a metal film 7b, a bonding layer 3, a semiconductor element 2, a heat radiating member 4a, and a metal wire 9a. , A heat radiating member 4b, a flexible heat radiating member 4d formed on the lower surface of the semiconductor element 2, and a heat radiating member formed on the lower surface of the heat radiating member 4d and having a higher thermal conductivity than the bonding layer 3. A member 4c and a sealing material 6 for sealing these components are provided.

  Here, the heat conductivity of the heat dissipation member 4d is higher than the heat conductivity of the heat dissipation member 4c. Since the heat dissipating member 4d in contact with the lower surface of the semiconductor element 2 has flexibility, it is possible to suppress the occurrence of cracks due to thermal stress generated when joining the semiconductor element 2 and the metal film 7b.

  In addition, an insulative protective film 123 (see FIG. 1) made of, for example, a polyimide resin material is formed in the invalid region of the semiconductor element 2. The bonding layer 3 is, for example, solder. The sealing material 6 is, for example, an insulating silicone gel.

  Here, the heat radiation member 4d is, for example, a graphite sheet having a thickness of 30 μm. The graphite sheet is a material having a thermal conductivity of 400 W / m · K or more, and reduces the thermal resistance at the location while improving the adhesion between the semiconductor element 2 and the heat radiating member 4 c. can do. Therefore, heat dissipation in the ineffective region of the semiconductor element 2 can be improved.

  If the combined thickness of the heat dissipating member 4c and the heat dissipating member 4d is greater than the thickness of the bonding layer 3, the bondability between the semiconductor element 2 and the metal film 7b is reduced. Therefore, it is desirable that the combined thickness of the heat radiating member 4 c and the heat radiating member 4 d be smaller than the thickness of the bonding layer 3.

  Further, the flexibility of the heat radiation member 4d decreases as the thickness of the heat radiation member 4d increases. Therefore, as shown in the present embodiment, it is desirable that the heat radiating member 4c and the heat radiating member 4d having a smaller thickness than the heat radiating member 4c be stacked. With this configuration, the overall thickness of the heat dissipating member including the heat dissipating member 4c can be increased in accordance with the thickness of the bonding layer 3 while maintaining the flexibility of the heat dissipating member 4d.

  It is desirable that the combined thickness of the heat radiating member 4c and the heat radiating member 4d be, for example, the thickness of the joining layer ± 20 μm. The thickness of the heat radiating member 4c and the thickness of the heat radiating member 4d Is 70 μm or less, for example.

<About the manufacturing method of the power semiconductor device>
Next, a method for manufacturing the power semiconductor device according to the present embodiment will be described below. Here, FIGS. 26 to 33 are diagrams showing a method of manufacturing the power semiconductor device according to the present embodiment.

  First, as shown in FIG. 26, the ceramic plate 8 is formed on the upper surface of the metal film 7a. Further, the metal film 7b is partially formed on the upper surface of the ceramic plate 8.

  Next, as shown in FIG. 26, the heat radiating member 4c is partially formed on the upper surface of the metal film 7b. Here, the heat radiating member 4c is formed at a position overlapping with an ineffective area of the semiconductor element 2 to be arranged in a later step in plan view. The heat radiation member 4c is formed intermittently in the circumferential direction, as shown in an example in FIG. The heat radiation member 4c in FIG. 26 has one missing portion on each side, but the number and position of the missing portions are not limited to the case shown in FIG.

  Next, as shown in FIG. 27, a heat radiating member 4d is formed on the upper surface of the heat radiating member 4c. Here, the heat radiation member 4d is formed continuously in the circumferential direction.

  Next, as shown in FIG. 28, the bonding layer 3 is formed on the upper surface of the metal film 7b in a region surrounded by the heat radiating members 4c and 4d in plan view. Here, the bonding layer 3 is, for example, a plate solder. Further, as shown in FIG. 29, the semiconductor element 2 is arranged on the upper surface of the bonding layer 3 and the upper surface of the heat radiating member 4d.

  Next, as shown in FIG. 29, the semiconductor element 2 and the metal film 7b are joined by heating the semiconductor element 2 and the bonding layer 3.

  Next, as shown in an example in FIG. 30, the heat radiating member 4 a is arranged in an invalid area of the semiconductor element 2. Then, as shown in FIG. 31, the heat radiating member 4b is arranged on the upper surface of the heat radiating member 4a. Here, the heat dissipating member 4 b is arranged apart from the semiconductor element 2.

  Next, as shown in FIG. 32, in order to obtain electrical conduction between the semiconductor element 2 and a main circuit for flowing a large current through the semiconductor element 2, a metal connected to the semiconductor element 2 is used. The wire 9 is formed.

  Next, as shown in an example in FIG. 33, a power semiconductor device according to the present embodiment is manufactured by forming an insulating sealing material 6 covering the formed structure.

  In addition, the step of arranging the heat radiating member 4a in the ineffective region of the semiconductor element 2 and the step of arranging the heat radiating member 4b on the upper surface of the heat radiating member 4a are not necessarily limited to the step of arranging the semiconductor element 2 on the upper surface of the bonding layer 3 and the heat radiating member 4d. It does not have to be after the step of arranging on the upper surface. That is, the semiconductor element 2 may be arranged on the upper surface of the bonding layer 3 and the upper surface of the heat dissipation member 4d after the heat radiating members 4a and 4b are arranged in the ineffective area of the semiconductor element 2.

<Fifth embodiment>
A power semiconductor device according to the present embodiment and a method for manufacturing the power semiconductor device will be described. In the following description, the same components as those described in the above-described embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate. .

<About the configuration of the power semiconductor device>
FIG. 34 is a cross-sectional view schematically showing an example of the structure of the power semiconductor device according to the present embodiment.

  As shown in FIG. 34, the power semiconductor device 1c includes a metal film 7a, a ceramic plate 8, a metal film 7b, a bonding layer 3, a semiconductor element 2, a heat dissipation member 4a, and a metal wire 9a. And a heat dissipating member 4b, a heat dissipating member 4d, a heat dissipating member 4c, an adhesive 10, and a sealing material 6 for sealing these components.

  Here, the adhesive 10 is formed across the heat radiating member 4a, the heat radiating member 4b, the heat radiating member 4c, the heat radiating member 4d, the semiconductor element 2, and the metal film 7b, and increases the adhesion between these components. . The adhesive 10 is, for example, a heat-curable silicone adhesive.

  The adhesive 10 is provided on the upper surface of the heat dissipating member 4b, the outer peripheral side surface of the heat dissipating member 4b, the outer peripheral side surface of the heat dissipating member 4a, the side surface of the semiconductor element 2, the outer peripheral side surface of the heat dissipating member 4d, and the outer peripheral side of the heat dissipating member 4c. And the upper surface of the metal film 7b.

  As described above, by improving the adhesion between the heat radiating members 4a, 4b, 4c, 4d, the semiconductor element 2, and the metal film 7b by the adhesive 10, the ineffective area of the semiconductor element 2 is improved. Can reliably improve the heat radiation.

  The configuration having the adhesive 10 is not limited to the present embodiment, and may be any one of the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment. It may be applied to the configuration shown in FIG.

<About the manufacturing method of the power semiconductor device>
Next, a method for manufacturing the power semiconductor device according to the present embodiment will be described below. Here, FIGS. 35 to 43 are views showing a method for manufacturing the power semiconductor device according to the present embodiment.

  First, as shown in FIG. 35, a ceramic plate 8 is formed on the upper surface of the metal film 7a. Further, the metal film 7b is partially formed on the upper surface of the ceramic plate 8.

  Next, as shown in FIG. 35, the heat radiation member 4c is partially formed on the upper surface of the metal film 7b. Here, the heat radiating member 4c is formed at a position overlapping with an ineffective area of the semiconductor element 2 to be arranged in a later step in plan view. The heat radiation member 4c is formed intermittently in the circumferential direction, as shown in an example in FIG. Although the heat radiating member 4c in FIG. 35 has one missing portion on each side, the number and positions of the missing portions are not limited to those shown in FIG.

  Next, as shown in FIG. 36, a heat radiation member 4d is formed on the upper surface of the heat radiation member 4c. Here, the heat radiation member 4d is formed continuously in the circumferential direction.

  Next, as shown in FIG. 37, the bonding layer 3 is formed on the upper surface of the metal film 7b in a region surrounded by the heat radiating members 4c and 4d in plan view. Here, the bonding layer 3 is, for example, a plate solder. Further, as illustrated in FIG. 38, the semiconductor element 2 is disposed on the upper surface of the bonding layer 3 and the upper surface of the heat radiation member 4d.

  Next, as shown in FIG. 38, the semiconductor element 2 and the metal film 7b are joined by heating the semiconductor element 2 and the bonding layer 3.

  Next, as shown in an example in FIG. 39, the heat radiating member 4a is arranged in the invalid area of the semiconductor element 2. Then, as shown in FIG. 40, the heat radiating member 4b is arranged on the upper surface of the heat radiating member 4a. Here, the heat dissipating member 4 b is arranged apart from the semiconductor element 2.

  Next, as shown in FIG. 41, the upper surface of the heat radiating member 4b, the outer side surface of the heat radiating member 4b, the outer side surface of the heat radiating member 4a, the side surface of the semiconductor element 2, and the outer surface of the heat radiating member 4d. The adhesive 10 is applied to the side surface, the outer peripheral side surface of the heat radiating member 4c, and the upper surface of the metal film 7b. Then, the adhesive 10 is cured by heating the adhesive 10.

  Next, as shown in FIG. 42, in order to obtain electrical continuity between the semiconductor element 2 and a main circuit for flowing a large current through the semiconductor element 2, a metal connected to the semiconductor element 2 is used. The wire 9 is formed.

  Next, as shown in FIG. 43, the power semiconductor device according to the present embodiment is manufactured by forming an insulating sealing material 6 covering the formed structure.

  As described above, by improving the adhesiveness between the heat radiating members 4a, 4b, 4c, 4d, the semiconductor element 2, and the metal film 7b by the adhesive 10, the ineffective area of the semiconductor element 2 is improved. Can reliably improve the heat radiation.

<Sixth Embodiment>
A power converter according to the present embodiment and a method for manufacturing the power converter will be described. In the following description, the same components as those described in the above-described embodiment will be denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

<About the configuration of the power converter>
In the present embodiment, the power semiconductor device according to the embodiment described above is applied to a power converter. The power converter to be applied is not limited to a specific application, but a case where the power converter is applied to a three-phase inverter will be described below.

  FIG. 44 is a diagram conceptually illustrating an example of the configuration of a power conversion system including the power conversion device according to the present embodiment.

  As illustrated in FIG. 44, the power conversion system includes a power supply 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply and supplies DC power to power conversion device 200. The power supply 100 can be composed of various types, and for example, can be composed of a DC system, a solar cell, a storage battery, or the like. Further, the power supply 100 can be configured by a rectifier circuit or an AC-DC converter connected to an AC system. Further, the power supply 100 may be configured by a DC-DC converter that converts DC power output from a DC system into predetermined power.

  Power conversion device 200 is a three-phase inverter connected between power supply 100 and load 300. The power conversion device 200 converts the DC power supplied from the power supply 100 into AC power, and further supplies the AC power to the load 300.

  In addition, as shown in an example in FIG. 44, the power conversion device 200 converts a DC power into an AC power and outputs the converted power, and a driving signal for driving each switching element of the conversion circuit 201. The driving circuit 202 includes an output driving circuit 202 and a control circuit 203 that outputs a control signal for controlling the driving circuit 202 to the driving circuit 202.

  Load 300 is a three-phase electric motor driven by AC power supplied from power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, for example, a motor used for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner. It is.

  Hereinafter, the details of the power conversion device 200 will be described. The conversion circuit 201 includes a switching element and a free wheel diode (not shown here). When the switching element performs a switching operation, the DC power supplied from the power supply 100 is converted into AC power, and is further supplied to the load 300.

  Although there are various specific circuit configurations of the conversion circuit 201, the conversion circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and each switching element. And six freewheel diodes connected in anti-parallel.

  The power semiconductor device according to any of the embodiments described above is applied to at least one of each switching element and each freewheel diode in the conversion circuit 201. The six switching elements are connected in series every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (ie, U phase, V phase, and W phase) of the full bridge circuit. The output terminals of the upper and lower arms (that is, the three output terminals of the conversion circuit 201) are connected to the load 300.

  The drive circuit 202 generates a drive signal for driving a switching element of the conversion circuit 201, and supplies the drive signal to a control electrode of the switching element of the conversion circuit 201. Specifically, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to control electrodes of the respective switching elements based on a control signal output from a control circuit 203 described later. I do.

  When the switching element is maintained in the ON state, the drive signal is a voltage signal higher than the threshold voltage of the switching element (that is, ON signal). When the switching element is maintained in the OFF state, the drive signal is lower than the threshold voltage of the switching element. (That is, an off signal).

  The control circuit 203 controls the switching elements of the conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time during which each switching element of the conversion circuit 201 should be in the ON state (ie, the ON time) is calculated. For example, the conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching element according to the voltage to be output.

  Then, the control circuit 203 issues a control command (to the drive circuit 202) such that an ON signal is output to the switching element to be turned on at each time and an OFF signal is output to the switching element to be turned off at each time. That is, a control signal is output. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to a control electrode of each switching element based on the control signal.

  In the power conversion device 200 according to the present embodiment, since the power semiconductor device according to any of the above-described embodiments is applied as a switching element of the conversion circuit 201, the on-resistance after an energization cycle is stabilized. be able to.

  In this embodiment, an example is described in which the power semiconductor device according to any of the above-described embodiments is applied to a two-level three-phase inverter, but the application example is not limited to this. Instead, the power semiconductor device according to any of the embodiments described above can be applied to various power converters.

  Further, in the present embodiment, a two-level power converter has been described, but the power semiconductor device in any of the embodiments described above is applied to a three-level or multi-level power converter. Is also good. When power is supplied to a single-phase load, the power semiconductor device according to any of the above-described embodiments may be applied to a single-phase inverter.

  When power is supplied to a DC load or the like, the power semiconductor device according to any of the above-described embodiments can be applied to a DC-DC converter or an AC-DC converter.

  Further, the power converter to which the power semiconductor device according to any of the embodiments described above is applied is not limited to the case where the load described above is an electric motor, for example, an electric discharge machine, It can also be used as a power supply for a laser processing machine, induction heating cooker or non-contact power supply system. A power converter to which the power semiconductor device according to any of the above-described embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

<About the effect produced by the embodiment described above>
Next, examples of effects produced by the above-described embodiment will be described. In the following description, the effect is described based on the specific configuration whose example is shown in the above-described embodiment. May be replaced with another specific configuration shown.

  Further, the replacement may be performed over a plurality of embodiments. That is, a configuration in which the same effects are obtained by combining the respective configurations illustrated in the different embodiments may be employed.

  According to the embodiment described above, the power semiconductor device includes the semiconductor element 2 and the first upper surface heat radiation member. Here, the first upper surface heat dissipation member corresponds to, for example, the heat dissipation member 4a. The semiconductor element 2 is arranged on the upper surface of the insulating substrate 5 via the bonding layer 3. The heat radiating member 4 a is partially formed on the upper surface of the semiconductor element 2. The semiconductor element 2 has a cell region 101 and an invalid region 102 surrounding the cell region 101 in plan view. Further, the heat radiating member 4 a is formed on the upper surface corresponding to the invalid area 102 of the semiconductor element 2.

  According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member. Therefore, a decrease in insulation reliability of the power semiconductor device can be suppressed.

  It should be noted that other configurations whose examples are described in the specification of the present application other than these configurations can be omitted as appropriate. That is, if at least these configurations are provided, the effects described above can be produced.

  However, when at least one of the other configurations exemplified in the specification of the present application is appropriately added to the above-described configuration, that is, in the specification of the present application which is not mentioned as the above-described configuration. The same effects can be obtained even when other configurations as shown in FIG.

  Further, according to the embodiment described above, the heat radiation member 4a is an insulator. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member. Therefore, a decrease in insulation reliability of the power semiconductor device can be suppressed.

  Further, according to the embodiment described above, the power semiconductor device includes the conductive second upper surface heat radiating member formed on the upper surface of heat radiating member 4a. Here, the second upper surface heat dissipation member corresponds to, for example, the heat dissipation member 4b. According to such a configuration, the conductive heat dissipating member 4b is provided via the insulating heat dissipating member 4a, so that when a high voltage is applied to the source electrode on the drain electrode side of the semiconductor element 2, Even if there is an electrical short circuit such as electric discharge, the heat dissipating member 4b having a high thermal conductivity can improve the heat dissipating property in the ineffective region of the semiconductor element 2. Therefore, even if there is a variation in dimensions due to individual differences of the semiconductor elements 2, it is possible to suppress a decrease in insulation reliability of the power semiconductor device.

  Further, according to the embodiment described above, the power semiconductor device includes the first lower surface heat radiation member partially formed on the lower surface of the semiconductor element 2. Here, the first lower surface heat radiating member corresponds to, for example, the heat radiating member 4c. The lower surface corresponding to the cell region 101 of the semiconductor element 2 is connected to the upper surface of the insulating substrate 5 via the bonding layer 3. The lower surface corresponding to the invalid region 102 of the semiconductor element 2 is connected to the upper surface of the insulating substrate 5 via the heat radiating member 4c. The heat conductivity of the heat radiating member 4 c is higher than the heat conductivity of the bonding layer 3. According to such a configuration, the heat radiating member 4c made of a material having a higher thermal conductivity than the bonding layer 3 is formed in contact with the lower surface of the semiconductor element 2 at a position overlapping the ineffective area of the semiconductor element 2 in plan view. By doing so, the heat dissipation of the ineffective region of the semiconductor element 2 can be further improved. Then, even if there are variations in dimensions due to individual differences of the semiconductor elements 2, it is possible to suppress a decrease in insulation reliability of the power semiconductor device.

  Further, according to the embodiment described above, the heat radiation member 4c is formed intermittently in the circumferential direction. According to such a configuration, when the semiconductor element 2 is bonded to the metal film 7b, even if the bonding layer 3 (that is, the solder) expands due to heating, the lower surface of the semiconductor element 2 and the heat radiation Separation from the member 4c can be prevented.

  Further, according to the embodiment described above, the radial width d of the heat radiation member 4c in plan view is smaller than the radial width D of the invalid region 102 in plan view. According to such a configuration, the heat radiation member 4c is prevented from reaching the position on the lower surface of the semiconductor element 2 that overlaps the cell region of the semiconductor element 2 in plan view. An increase in contact resistance during operation can be prevented.

  Further, according to the embodiment described above, the power semiconductor device includes the second lower surface heat radiation member. Here, the second lower surface heat radiating member corresponds to, for example, the heat radiating member 4d. The heat radiation member 4d is partially formed on the lower surface of the semiconductor element 2 and has flexibility. The heat radiating member 4c is formed on the lower surface of the semiconductor element 2 via the heat radiating member 4d. According to such a configuration, it is possible to improve the adhesion between the heat radiating member 4d and the semiconductor element 2 and between the heat radiating member 4d and the heat radiating member 4c, and to reduce the thermal resistance at the relevant portion. . Therefore, heat dissipation in the ineffective region of the semiconductor element 2 can be improved. Moreover, the thickness of the entire heat dissipating member including the heat dissipating member 4c can be increased in accordance with the thickness of the bonding layer 3 while maintaining the flexibility of the heat dissipating member 4d.

  According to the above-described embodiment, the total thickness of the heat radiating member 4c and the heat radiating member 4d is 70 μm or less. According to such a configuration, the thickness of the entire heat dissipating member including the heat dissipating member 4c can be increased in accordance with the thickness of the bonding layer 3 while maintaining the flexibility of the heat dissipating member 4d.

  Further, according to the embodiment described above, the power semiconductor device includes at least the adhesive 10 formed over the semiconductor element 2 and the heat dissipation member 4a. According to such a configuration, by improving the adhesiveness between the semiconductor element 2, the heat radiating member 4a, the heat radiating member 4b, the heat radiating member 4c, the heat radiating member 4d, and the metal film 7b by the adhesive 10, In addition, heat dissipation in the ineffective region of the semiconductor element 2 can be reliably improved.

  Further, according to the embodiment described above, a power converter includes the power semiconductor device described above, and further includes a conversion circuit 201 that converts input power and outputs the power, and a power semiconductor device. A driving circuit 202 for outputting a driving signal for driving the driving circuit 202 to the power semiconductor device, and a control circuit 203 for outputting a control signal for controlling the driving circuit 202 to the driving circuit 202. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member.

  According to the embodiment described above, in the method for manufacturing a power semiconductor device, the semiconductor element 2 is disposed on the upper surface of the insulating substrate 5 with the bonding layer 3 interposed therebetween. Then, the heat radiation member 4 a is partially formed on the upper surface of the semiconductor element 2. The semiconductor element 2 has a cell region 101 and an invalid region 102 surrounding the cell region 101 in plan view. Then, the heat radiating member 4 a is formed on the upper surface corresponding to the invalid area 102 of the semiconductor element 2.

  According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member. Therefore, a decrease in insulation reliability of the power semiconductor device can be suppressed.

  It should be noted that other configurations whose examples are described in the specification of the present application other than these configurations can be omitted as appropriate. That is, if at least these configurations are provided, the effects described above can be produced.

  However, when at least one of the other configurations exemplified in the specification of the present application is appropriately added to the above-described configuration, that is, in the specification of the present application which is not mentioned as the above-described configuration. The same effects can be obtained even when other configurations as shown in FIG.

  If there is no particular limitation, the order in which the processes are performed can be changed.

  Further, according to the embodiment described above, in the method of manufacturing the power semiconductor device, the semiconductor element 2 is disposed on the upper surface of the insulating substrate 5 so as to be disposed on the upper surface corresponding to the invalid region 102 of the insulating substrate 5. The heat radiating member 4c having a higher thermal conductivity than the bonding layer 3 is formed. Then, the bonding layer 3 is formed in a region surrounded by the heat radiation member 4c on the upper surface of the insulating substrate 5. Then, the cell region 101 of the semiconductor element 2 is disposed on the upper surface of the bonding layer 3, and the invalid region 102 of the semiconductor element 2 is disposed on the upper surface of the heat radiation member 4c. According to such a configuration, the heat radiating member 4c made of a material having a higher thermal conductivity than the bonding layer 3 is formed in contact with the lower surface of the semiconductor element 2 at a position overlapping the ineffective area of the semiconductor element 2 in plan view. By doing so, the heat dissipation of the ineffective region of the semiconductor element 2 can be further improved.

  According to the above-described embodiment, in a method for manufacturing a power converter, the method includes a power semiconductor device manufactured by the above manufacturing method, and converts input power and outputs the converted power. A conversion circuit 201 is provided. Then, a driving circuit 202 for outputting a driving signal for driving the power semiconductor device to the power semiconductor device is provided. Further, a control circuit 203 for outputting a control signal for controlling the driving circuit 202 to the driving circuit 202 is provided. According to such a configuration, heat dissipation in the ineffective region of the semiconductor element can be improved by the heat dissipation member.

<Modifications of the above-described embodiment>
In the embodiments described above, the materials, materials, dimensions, shapes, relative arrangement relations, or implementation conditions of the respective constituent elements may be described. However, these are one example in all aspects. , And is not limited to those described in the specification of the present application.

  Thus, innumerable variations and equivalents, not shown, are envisioned within the scope of the techniques disclosed herein. For example, when modifying, adding, or omitting at least one component, further extracting at least one component in at least one embodiment, and combining it with components in other embodiments. Shall be included.

  Unless inconsistency arises, "one or more" of the components described as "one" provided in the above-described embodiment may be provided.

  Further, each component in the above-described embodiment is a conceptual unit, and one component includes a plurality of structures within the scope of the technology disclosed in this specification. And a case where one component corresponds to a part of a structure, and a case where a plurality of components are provided in one structure.

  In addition, each component in the above-described embodiments includes a structure having another structure or shape as long as the same function is exhibited.

  Further, the description in the specification of the present application is referred to for all purposes related to the present technology, and none of them is admitted to be prior art.

  In addition, in the embodiments described above, when a material name or the like is described without particular designation, unless there is a contradiction, the material includes other additives, such as an alloy. Shall be included.

  1, 1a, 1b, 1c Power semiconductor device, 2 semiconductor element, 3 bonding layer, 4a, 4b, 4c, 4d Heat radiating member, 5 insulating substrate, 6 sealing material, 7a, 7b metal film, 8 ceramic plate, 9 Metal wire, 10 adhesive, 100 power supply, 101 cell region, 102 invalid region, 110 n− type semiconductor layer, 111, 121 p− type semiconductor layer, 112, 122 n + type semiconductor layer, 113 p + type semiconductor Layers, 114 gate oxide film, 115 gate electrode, 116 insulating film, 117 emitter electrode, 123 protective film, 200 power conversion device, 201 conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims (13)

A semiconductor element arranged on the upper surface of the insulating substrate via a bonding layer,
A first upper surface heat radiation member partially formed on the upper surface of the semiconductor element,
The semiconductor element has a cell region and an ineffective region surrounding the cell region in plan view,
The first upper surface heat radiation member is formed on an upper surface corresponding to the invalid region of the semiconductor element.
Power semiconductor device. The first upper surface heat dissipation member is an insulator.
The power semiconductor device according to claim 1. Further comprising a conductive second upper surface heat radiating member formed on the upper surface of the first upper surface heat radiating member;
The power semiconductor device according to claim 2. A first lower surface heat radiation member partially formed on a lower surface of the semiconductor element;
A lower surface corresponding to the cell region of the semiconductor element is connected to an upper surface of the insulating substrate via the bonding layer,
A lower surface corresponding to the invalid region of the semiconductor element is connected to an upper surface of the insulating substrate via the first lower surface heat radiation member,
The thermal conductivity of the first lower surface heat dissipation member is higher than the thermal conductivity of the bonding layer.
The power semiconductor device according to any one of claims 1 to 3. The first lower surface heat dissipation member is formed intermittently in a circumferential direction.
The power semiconductor device according to claim 4. The radial width of the first lower surface heat dissipation member in plan view is smaller than the radial width of the ineffective area in plan view.
The power semiconductor device according to claim 4. A second lower surface heat radiation member partially formed on the lower surface of the semiconductor element and having flexibility;
The first lower surface heat dissipation member is formed on the lower surface of the semiconductor element via the second lower surface heat dissipation member.
The power semiconductor device according to any one of claims 4 to 6. The total thickness of the thickness of the first lower surface heat dissipation member and the thickness of the second lower surface heat dissipation member is 70 μm or less.
A power semiconductor device according to claim 7. At least, further comprising an adhesive formed over the semiconductor element and the first upper surface heat dissipation member,
The power semiconductor device according to any one of claims 1 to 8. A conversion circuit, comprising: the power semiconductor device according to claim 1, wherein the conversion circuit converts input power and outputs the power.
A drive circuit that outputs a drive signal for driving the power semiconductor device to the power semiconductor device;
A control circuit for outputting a control signal for controlling the drive circuit to the drive circuit,
Power converter. A semiconductor element is arranged on the upper surface of the insulating substrate via a bonding layer,
Forming a first upper surface heat radiation member partially on the upper surface of the semiconductor element;
The semiconductor element has a cell region and an ineffective region surrounding the cell region in plan view,
The first upper surface heat radiation member is formed on an upper surface corresponding to the invalid region of the semiconductor element.
A method for manufacturing a power semiconductor device. As the arrangement of the semiconductor element on the upper surface of the insulating substrate,
Forming a first lower surface heat radiation member having a higher thermal conductivity than the bonding layer on an upper surface corresponding to the ineffective region of the insulating substrate;
Forming the bonding layer in a region of the upper surface of the insulating substrate surrounded by the first lower surface heat dissipation member;
Arranging the cell region of the semiconductor element on an upper surface of the bonding layer, and arranging the invalid region of the semiconductor element on an upper surface of the first lower surface heat dissipation member;
A method for manufacturing a power semiconductor device according to claim 11. A power supply semiconductor device manufactured by the manufacturing method according to claim 11 or 12, and a conversion circuit that converts input power and outputs the converted power,
Providing a drive circuit that outputs a drive signal for driving the power semiconductor device to the power semiconductor device,
Providing a control circuit for outputting a control signal for controlling the drive circuit to the drive circuit,
A method for manufacturing a power converter.

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