CN104217949A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN104217949A
CN104217949A CN201310215728.1A CN201310215728A CN104217949A CN 104217949 A CN104217949 A CN 104217949A CN 201310215728 A CN201310215728 A CN 201310215728A CN 104217949 A CN104217949 A CN 104217949A
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fin
material layer
spacer material
side wall
layer
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殷华湘
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, comprising the following steps: a plurality of fins located on the substrate and extending along a first direction; a gate stack extending in a second direction and spanning each fin; the grid side walls are positioned on the fins, positioned on two sides of the grid stack along the first direction and comprise first side walls formed by the first side wall material layers and second side walls formed by the second side wall material layers, wherein the first side walls have L-shaped appearances; and the source and drain extension regions are positioned in the fins and positioned on two sides of the gate stack along the first direction. According to the semiconductor device and the manufacturing method thereof, the composite multi-layer grid side wall is formed on the side wall of the fin, so that the control precision of the SDE transverse width is improved, and the top of the fin can be protected to reduce defects.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of FinFET sidewall structure and manufacture method thereof.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri--gate) is main device architecture, and this structure enhances grid control ability, inhibits electric leakage and short-channel effect.
Such as, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, short-channel effect (SCE) can be suppressed and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, raceway groove light dope can be realized, adjusting threshold voltage can be carried out by the work function arranging metal gates, the drive current of about 2 times can be obtained, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, gate wraps channel region end face and two sides, grid control ability is stronger.Further, loopful has more advantage around nano wire multi-gate device.
Existing FinFET structure and manufacture method generally include: in body Si or SOI substrate, etching forms multiple parallel fin along first direction extension and groove; Ion implantation or dopant deposition layer performed to fin and anneals, in the middle part of fin, forming break-through barrier layer (PTSL) to suppress parasitic channel effect; Fill insulant in the trench, returns and carves with exposed portion fin, forms shallow trench isolation from (STI); Be generally thinner (such as only 1 ~ 5nm) false grid insulating barrier of silica at fin top and side wall deposition, on false grid insulating barrier, deposition is generally the false grid layer of polysilicon, amorphous silicon; Etching false grid layer and false grid insulating barrier, form the false grid extended along second direction stacking, wherein second direction is preferably perpendicular to first direction; Mask is stacked as with false grid, to fin carry out shallow doping formed lightly doped drain structure (LDD) particularly source and drain extend (SDE) structure with suppresses leakage cause induced barrier reduce effect, doping way can comprise high inclination-angle shallow junction tilt inject, spread or molecule deposition; Deposit in the both sides along first direction that false grid is stacking and etch and form grid curb wall; At the fin Epitaxial growth of the both sides along first direction of grid curb wall, identical or similar materials formation source-drain area, preferably adopts SiGe, SiC etc. higher than the material of Si stress to improve carrier mobility; Preferably, source-drain area is formed contact etching stop layer (CESL); At deposition on wafer interlayer dielectric layer (ILD); It is stacking that etching removes false grid, in ILD, leave gate trench; The gate insulator of deposited high-k material (HK) and the grid conducting layer of metal/metal alloy/metal nitride (MG) in gate trench, and the gate cap preferably including nitride material is to protect metal gates.Further, mask etching ILD is utilized to form source and drain contact hole, source of exposure drain region; Alternatively, in order to reduce source-drain contact resistance, in source and drain contact hole, form metal silicide.Fill metal/metal nitride and form contact plug, preferably filling rate is higher usually metal W, Ti.Due to the existence of CESL, grid curb wall, the metal W of filling, Ti meeting auto-alignment source-drain area, finally form contact plug.
Usually; before formation LDD/SDE structure; such as by the insulating dielectric materials layer of the good depositing operation of conformality such as PECVD, HDPCVD first cvd silicon oxide or nitrogen oxide material; then using plasma dry etching or reactive ion etching (RIE) technique etching form the first thinner side wall or interim side wall; so that the protection channel region when LDD, SDE or Halo doping after a while, reduces inevitable side direction doping diffusion as far as possible.Subsequently, the second thicker side wall can be formed using as final grid curb wall after LDD doping.
In the process of above-mentioned etching first side wall, need strict control etch process parameters accurately to control the bottom width of fin top grid side wall, because this have impact on the position of LDD, SDE or Halo doped structure after a while to a great extent, the interface location particularly and between channel region and extension area transverse width.But when characteristic size is low to moderate below 22nm, the accurate control difficulty etching particularly side wall bottom width is increased suddenly.On the other hand, when removing most of dielectric material to form the first side wall, needing again the medium guaranteeing to remove completely on false grid insulating barrier and the fin top of simultaneously guaranteeing below it is injury-free, which further increases the difficulty of technology controlling and process.
Summary of the invention
From the above mentioned; the object of the invention is to overcome above-mentioned technical difficulty; a kind of new FinFET structure particularly grid curb wall structure and manufacture method thereof is proposed, by Simplified flowsheet low cost realization for SDE transverse width accurate control and simultaneously fin top can be protected to reduce defect.
For this reason, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: along multiple fins that first direction extends on substrate; Fin is formed the gate stack extended along second direction; Whole device is formed the first spacer material layer; Light dope is carried out to fin, in the formation source and drain extension, side along first direction of gate stack; Whole device is formed the second spacer material layer; Etch the second spacer material layer and the first spacer material layer, form grid curb wall in the side along first direction of gate stack.
Wherein, formation taking a step forward of gate stack comprise: in fin and/or bottom formed break-through barrier layer.
Wherein, the thickness of the first spacer material layer is adjusted to control the transverse width of source and drain extension.
Wherein, the thickness of the first spacer material layer is 1 ~ 5nm.
Wherein, the material of the first and/or second spacer material layer be selected from silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC), air and combination thereof.
Wherein, grid curb wall comprises the first side wall of the first spacer material layer formation and the second side wall of the second spacer material layer formation, and wherein the first side wall has L-type pattern.
Wherein, the second spacer material layer is multilayer laminate constructions.
Present invention also offers a kind of semiconductor device, comprising: multiple fin, to be positioned on substrate and to extend along first direction; Gate stack, extends along second direction and spans each fin; Grid curb wall, is positioned on fin, and is positioned at the both sides along first direction of gate stack, and comprise the first side wall of the first spacer material layer formation and the second side wall of the second spacer material layer formation, wherein the first side wall has L-type pattern; Source and drain extension, is arranged in fin, and is positioned at the both sides along first direction of gate stack.
Wherein, in fin and/or bottom comprise break-through barrier layer further.
Wherein, the thickness of the first spacer material layer is 1 ~ 5nm.
Wherein, the material of the first and/or second spacer material layer be selected from silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC), air and combination thereof.
Wherein, the second spacer material layer is multilayer laminate constructions.
According to semiconductor device of the present invention and manufacture method thereof, define the stacked gate side wall of compound in fin sidewall, improve the control precision of SDE transverse width and fin top can be protected to reduce defect simultaneously.
Accompanying drawing explanation
Technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 13 is the generalized section according to each step of FinFET manufacture method of the present invention;
Figure 14 is the perspective schematic view according to FinFET of the present invention; And
Figure 15 is the indicative flowchart according to FinFET manufacture method of the present invention.
Embodiment
Describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing, disclosing can effectively accurate control SDE transverse width and simultaneously fin top can be protected to reduce three-dimensional multi-gate FinFET and the manufacture method thereof of defect.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process.These modify the space of not hint institute's modification device architecture or manufacturing process unless stated otherwise, order or hierarchical relationship.
It should be noted that, each accompanying drawing middle and upper part part is that device is along (the fin bearing of trend of first direction in Figure 14 below, source and drain bearing of trend, also i.e. Y--Y ' axis) cutaway view, mid portion is that device is along second direction (gate stack bearing of trend, perpendicular to first direction, also i.e. X--X ' axis) the cutaway view of gate stack center line, low portion is device along being parallel to second direction and being positioned at the cutaway view that the position that (first direction has certain distance) outside gate stack (also i.e. X1--X1 ' axis) obtains.
As shown in Figure 1, form the groove 1G between multiple fin structure 1F and fin structure extended along first direction on substrate 1, wherein first direction is future device channel region bearing of trend (Y--Y ' axis in Figure 14).Substrate 1 is provided, substrate 1 needs and choose reasonable according to device application, monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (Strained Si), germanium silicon (SiGe) can be comprised, or compound semiconductor materials, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc.For the consideration with CMOS technology compatibility, substrate 1 is preferably body Si.Preferably, form hard mask 2 on substrate 1 by process deposits such as LPCVD, PECVD, material is such as silica, silicon nitride, silicon oxynitride and combination thereof.With hard mask 2 for mask, photoetching/etched substrate 1, forms the fin 1F that between multiple groove 1G along the parallel distribution of first direction and groove 1G, remaining substrate 1 material is formed in substrate 1.Etch preferred anisotropic etching, such as plasma dry etch, reactive ion etching (RIE) or Tetramethylammonium hydroxide (TMAH) wet etching, make the depth-to-width ratio of groove 1G be preferably more than 5:1.
As shown in Figure 2, by PECVD, HDPCVD, RTO(rapid thermal oxidation in the groove 1G between fin 1F), spin coating, the process deposits such as FlowCVD fill the separator 3 that material is such as silica, silicon oxynitride, silicon hydroxide, organic substance etc.Preferably, after Fig. 2, taking a step forward of Fig. 3 perform CMP, return the flatening process such as quarters, to separator 3 planarization until exposure hard mask layer 2.
As shown in Figure 3, in fin 1F and/or bottom form break-through barrier layer (PTSL) 4.After hard mask layer 2 is exposed in the planarization of structure shown in Fig. 2, perform ion implantation, N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge etc. and combination thereof can be comprised.Perform annealing subsequently, such as at 500 ~ 1200 degrees Celsius of lower heat treatment 1ms ~ 10min, the element of injection and fin 1F are reacted, forms the break-through barrier layer 4 of (such as doped with the silica of above-mentioned element) of highly doped (Si of doping above-mentioned material) or insulating material.In an embodiment of the invention, control Implantation Energy and dosage, only in fin 1F, define channel punchthrough barrier layer 4B, as shown in Figure 3, with the leakage suppressing channel region to pass through STI side.But, in another preferred embodiment of the present invention, control Implantation Energy and dosage, make break-through barrier layer 4 to be also distributed in bottom fin 1F with substrate 1 interface as STI break-through barrier layer 4A, with channel region in effectively isolated fin 1F, leakage current between source-drain area and adjacent fin active area.Layer 4B material can be identical with layer 4A material, also can comprise the different component (but at least comprising oxygen) in above-mentioned element.Layer 4B can be formed (it is different that different element injects the degree of depth) from layer 4A simultaneously disposable injection, also can the injection of successively twice different depth, dosage, and such as can first dark distance inject and form layer 4A, rear shallow distance injection formation layer 4B, vice versa.In addition, except above-mentioned highly doped break-through barrier layer, a large amount of oxygen (O) can also be injected to form the silica-based insulating barrier of oxidation using as break-through barrier layer (also can adulterate in this silicon oxide layer above-mentioned impurity further).It should be noted that the height of channel punchthrough barrier layer 4B distance fin 1F top (or bottom) can set arbitrarily, be preferably 1/3 ~ 1/2 of fin 1F oneself height in an embodiment of the invention.STI break-through barrier layer 4A and channel punchthrough barrier layer 4B thickness are such as 5 ~ 30nm.The width of layer 4A (along first and/or second direction) set according to whole device active region width, namely the width of layer 4B is then identical with fin 1F, and also the width of layer 4A is obviously greater than the width of layer 4B.
As shown in Figure 4, selective etch separator 3, forms groove 1G again, exposes a fin 1F part.Can adopt photoetching offset plate figure or other hard mask graphs, select anisotropic lithographic method, such as plasma dry etch, RIE, etching separator 3, makes remaining separator 3 constitute shallow trench isolation from (STI) 3.Preferably, the degree of depth of groove 1G, is also the distance at STI3 distance from top fin 1F top, is more than or equal to the distance at 4B distance from top fin 1F top, channel punchthrough barrier layer, to suppress the break-through between channel region completely.Subsequently, wet etching eliminates hard mask 2.
As shown in Figure 5, the false grid stacked structure 5 extended along second direction is formed at fin 1F top.Whole device forms false grid insulating barrier 5A and false grid material layer 5B by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputterings, and preferably comprises hard mask layer 5C further.Layer 5A is such as silica, and layer 5B is such as polysilicon, amorphous silicon, amorphous carbon, silicon nitride etc., and layer 5C is such as silicon nitride.To have the mask plate of the rectangular aperture of the second direction perpendicular to first direction, photoetching/etching (similarly successively, etching is anisotropic, preferred plasma dry etch, RIE) hard mask layer 5C, false grid material layer 5B and false grid insulating barrier 5A, the false grid stacking 5 extended along second direction is formed at fin 1F top.As shown in Fig. 5 top and middle part, the stacking 5(5C/5B/5A of false grid) be only distributed in along within the scope of the one fixed width of X--X ' axis, X1--X1 ' the axis place outside certain distance does not distribute.
As shown in Figure 6, whole device is formed the first spacer material layer 6A.Whole device passes through LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, the techniques such as (magnetic control) sputtering form the first spacer material layer 6A, its material such as silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC) etc. and combination thereof, wherein low-k materials such as includes, but are not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).In an embodiment of the invention, preferred nitrogen SiClx.
It should be noted that, from deposited in the past after etch that to form side wall different immediately, after sedimentary deposit 6A, etching does not form side wall immediately, but is remained to the step of Fig. 9, and after doping forms SDE and the second thicker spacer material layer 6B, unified etching forms grid curb wall again.Now the thickness of layer 6A determines the SDE transverse width interface location of shallow, lightly doped source-drain area and channel region (also i.e.).In a preferred embodiment of the invention, the thickness of layer 6A such as only 1 ~ 5nm, preferably 2 ~ 4nm the best is 3nm.Now, as in fig. 6 upper, layer 6A covers the stacking 5(5C of false grid) top and sidewall, and cover the top of fin 1F; As shown in the lower part of Figure 6, layer 6A covers top and the sidewall of fin 1F, and covers the top of STI3.In other words, layer 6A at least has the Part I of level and vertical Part II.Layer 6A defines the width of horizontal proliferation and protects fin top to reduce defect in SDE doping process after a while.
As shown in Figure 7, penetrate the first spacer material layer 6A, light dope is carried out to fin 1F, comprising multi-angle (can be vertical and/or inclination, inclination angle can such as 80 ~ 90 ± 0.5 degree) shallow injection or molecular dopant, diffusing, doping etc., lightly-doped source drain region (LDD structure or SDE structure) 1LS and 1LD is defined at fin 1F top and lateral wall circumference.As in the middle part of Fig. 7 and shown in bottom, SDE structure 1LS/1LD is around fin 1F top and sidewall.In the process, because layer 6A is thinner, a part of dopant that energy/dosage is higher substantially can not stopped or is subject to less stop and penetrated bed 6A enters in fin 1F.Simultaneously, because layer 6A has certain thickness, energy/dosage then cannot penetrated bed 6A stop or be retained in layer 6A lower than the dopant of certain threshold value, thus reduce (except vertical direction) horizontal proliferation, improve the accuracy of the transverse width thickness of 1LS (in the middle part of such as Fig. 7 and in the bottom) of SDE or LDD structure, be conducive to the homogenizing of technique and reduce the difficulty of process parameter control.
As shown in Figure 8, whole device is formed the second spacer material layer 6B.Similar to layer 6A, such as pass through LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, the techniques such as (magnetic control) sputtering form the second spacer material layer 6B, its material is such as also selected from silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC) etc. and combination thereof, wherein low-k materials such as includes, but are not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).In an embodiment of the invention, layer 6B material is preferably different from a layer 6A material.Layer 6B is for realizing the insulation isolation of grid, and therefore its thickness is obviously greater than a layer 6A, such as, be 5 ~ 20nm and preferred 10nm.In a preferred embodiment of the invention, layer 6B has stress, and the size of its stress (absolute value) is greater than the stress intensity of layer 6A, be such as 1 ~ 4GPa(can obtain different stress silicon nitride or DLC iso-stress material by the technological parameter of control PECVD or magnetron sputtering), so as to fin top channel region stress application thus increase carrier mobility.
In addition, it should be noted that, although only show single layer 6B in Fig. 8 and subsequent drawings, but actual upper strata 6B can be the stacking of medium material, such as above-mentioned silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC) material stacking (depositing multiple layers of constituting layer stack structure successively).In addition, layer 6B can further include air-gap (the such as NON structure (or ONO structure) of deposited silicon nitride lower floor--silica middle level--silicon nitride overlayer successively on layer 6A, the upper strata at etching top forms the opening exposing middle level, part middle level is removed to form hole with HF base corrosive liquid) to improve insulation isolation effect, also namely layer 6B material can comprise air.
As shown in Figure 9, etch the second spacer material layer 6B and the first spacer material layer 6A, until expose the stacking 5(5C of false grid), at the both sides formation grid curb wall 6 of false grid stacking 5 along first direction.Preferred anisotropic etching technics, such as plasma dry etch or RIE, etching gas is such as carbon fluorine base gas, the etch rate for different materials is controlled, so that the pattern of accurate control gate side wall 6 by adjustment etching gas proportioning (such as adjusting C and F atom number ratio in carbon fluorine base gas).As shown in Fig. 9 top, grid curb wall 6 at least comprises the first side wall 6A and the second side wall 6B, wherein the first side wall 6A has the Part I of level and vertical Part II thus forms " L " type, above the Part I that second side wall 6B is positioned at the first side wall and Part II sidewall thus pattern has triangle (shown in Fig. 9), trapezoidal (top is etched and has platform, not shown in Fig. 9), polygon (parallelogram etc.), part elliptical (such as 1/4 is oval) etc. and combination thereof.Preferably, passable
As shown in Figure 10, fin 1F is promoted source and drain 1HS and 1HD by the region Epitaxial growth outside stacking 5 cover parts of false grid.Such as by techniques such as PECVD, MOCVD, MBE, ALD, thermal decomposition, evaporation, sputterings, above light doping section 1LS and 1LD of fin 1F top, epitaxial growth promotes drain region 1HD and promotes source region 1HS.Wherein, promoting source-drain area 1HS/1HD material can be identical with substrate 1, fin 1F, such as, be Si, also can material different, such as there is more heavily stressed SiGe, Si:C, Si:H, SiSn, GeSn, SiGe:C etc. and combination thereof.Preferably, epitaxial growth promote carry out in-situ doped or extension while source and drain after carry out ion implantation and heavy doping, make to promote source and drain 1HD/1HS and there is impurity concentration higher than light dope source and drain 1LD/1LS.Subsequently, the impurity activating doping is annealed.
As shown in figure 11, whole device is formed contact etching stop layer (CESL) 7A and interlayer dielectric layer (ILD) 7B.Preferably, first can be omitted by the contact etching stop layer 7A(of the technique formation silicon nitrides such as PECVD, HDPCVD, sputtering on device).Subsequently, pass through spin coating, spraying, silk screen printing, CVD, the techniques such as PVD form silica, the ILD7B of low-k materials, wherein low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silex glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).Subsequently, adopt CMP, return the technique planarization ILD 7B and hard mask layer 5C such as quarter until expose the false grid material layer 5B of false grid stacking 5.
As shown in figure 12, remove false grid stacking 5, form gate trench 7C.Remove false grid stacking 5, wet etching can be adopted, such as hot phosphoric acid is for silicon nitride, TMAH is for polysilicon, amorphous silicon, and strong acid (sulfuric acid, nitric acid) and strong oxidizer (ozone, hydrogen peroxide) combination are for amorphous carbon, DLC, HF base corrosive liquid (dilution HF or BOE, BOE is slowly-releasing etching agent, NH4F and HF mixed solution) for silica, remove false grid material layer 5B and false grid insulating barrier 5A thus, until expose fin 1F top.In addition, also anisotropic dry etching (only along the X--X ' axis of second direction) can be adopted, regulate the proportioning of carbon fluorine base gas, make bottom etch rate be greater than sidewall etch rate (etching ratio is such as greater than 5:1 and preferred 10 ~ 15:1), etching forms the gate trench 7C of vertical sidewall pattern thus.
As shown in figure 13, in gate trench 7C, final gate stack 8 is formed.Such as, adopt the techniques such as PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, in gate trench, define gate stack 8.Gate stack 8 at least comprises the gate insulator 8A of high-g value and the grid conducting layer 10B of metal_based material.High-g value includes but not limited to comprise and is selected from HfO 2, HfSiO x, HfSiON, HfAlO x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO xhafnium sill (wherein, each material is different according to multi-element metal component proportion and chemical valence, and oxygen atom content x can Reasonable adjustment, such as, can be 1 ~ 6 and be not limited to integer), or comprise and be selected from ZrO 2, La 2o 3, LaAlO 3, TiO 2, Y 2o 3rare earth based high K dielectric material, or comprise Al 2o 3, with the composite bed of its above-mentioned material.Grid conducting layer 8B then can be polysilicon, poly-SiGe or metal, wherein metal can comprise the alloy of the metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals and the nitride of these metals, also can doped with elements such as C, F, N, O, B, P, As with regulatory work function in grid conducting layer 10B.Also form the barrier layer (not shown) of nitride between grid conducting layer 8B and gate insulator 8A preferably by conventional methods such as PVD, CVD, ALD, barrier layer material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.
Common process can be adopted afterwards to complete device interconnection.Such as, etch ILD 7B, contact etching stop layer 7A successively, until source of exposure drain region 1HS/1HD, form contact hole.The preferred anisotropic dry etching of lithographic method, such as dry plasma etch or RIE.Preferably, the source-drain area of contact holes exposing is formed metal silicide (not shown) to reduce contact resistance.Such as, evaporate in the contact hole, sputter, MOCVD, MBE, ALD form metal level (not shown), metal and the metal alloys such as its material such as Ni, Pt, Co, Ti, W.Anneal 1ms ~ 10min under 250 ~ 1000 degrees Celsius, makes Si element reaction contained in metal or metal alloy and source-drain area form metal silicide, to reduce contact resistance.Fill contact metal layer in the contact hole subsequently, such as by techniques such as MOCVD, MBE, ALD, evaporation, sputterings, define contact metal layer, the preferred ductility of its material is better, filling rate is higher and the material of relatively low cost, such as, comprise the metals such as W, Ti, Pt, Ta, Mo, Cu, Al, Ag, Au, the alloy of these metals and the corresponding nitride of these metals.Subsequently, adopt CMP, return the technique planarized contact metal levels such as quarter, until expose CESL layer 7A.
The device architecture perspective view of final formation as shown in figure 14, cutaway view as shown in figure 13, device comprises: along multiple fins that first direction extends on substrate, extend (crossing with first direction and preferably vertical) along second direction and span the grid of each fin, be positioned at grid along the source-drain area on the fin of the both sides of first direction, grid curb wall is positioned at the side of grid along first direction, and wherein, grid curb wall comprises first grid side wall and second grid side wall.First grid side wall has the Part I of level and vertical Part II, has L-type pattern.Above the Part I that second grid side wall is positioned at the level of first grid side wall and the sidewall of vertical Part II, there is the pattern of triangle, trapezoidal, polygon, part elliptical etc. and combination thereof.Second grid side wall preferably includes sandwich construction, such as, comprise air-gap.First and/or the material of second grid side wall be selected from silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC), air etc. and combination thereof.In addition, in fin and/or fin and substrate interface place has break-through barrier layer.All the other all parts structures and parameter, material all describe in detail in method, do not repeat them here.
According to semiconductor device of the present invention and manufacture method thereof, define the stacked gate side wall of compound in fin sidewall, improve the control precision of SDE transverse width and fin top can be protected to reduce defect simultaneously.
Although the present invention is described with reference to one or more exemplary embodiment, those skilled in the art can know without the need to departing from the scope of the invention and make various suitable change and equivalents to device architecture.In addition, can be made by disclosed instruction and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention.Therefore, object of the present invention does not lie in and is limited to as realizing preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments fallen in the scope of the invention.

Claims (12)

1. a method, semi-conductor device manufacturing method, comprising:
Along multiple fins that first direction extends on substrate;
Fin is formed the gate stack extended along second direction;
Whole device is formed the first spacer material layer;
Light dope is carried out to fin, in the formation source and drain extension, side along first direction of gate stack;
Whole device is formed the second spacer material layer;
Etch the second spacer material layer and the first spacer material layer, form grid curb wall in the side along first direction of gate stack.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, comprises taking a step forward of gate stack of formation: in fin and/or bottom form break-through barrier layer.
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, adjusts the thickness of the first spacer material layer to control the transverse width of source and drain extension.
4. method, semi-conductor device manufacturing method as claimed in claim 3, wherein, the thickness of the first spacer material layer is 1 ~ 5nm.
5. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the material of the first and/or second spacer material layer be selected from silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC), air and combination thereof.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, grid curb wall comprises the first side wall of the first spacer material layer formation and the second side wall of the second spacer material layer formation, and wherein the first side wall has L-type pattern.
7. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the second spacer material layer is multilayer laminate constructions.
8. a semiconductor device, comprising:
Multiple fin, to be positioned on substrate and to extend along first direction;
Gate stack, extends along second direction and spans each fin;
Grid curb wall, is positioned on fin, and is positioned at the both sides along first direction of gate stack, and comprise the first side wall of the first spacer material layer formation and the second side wall of the second spacer material layer formation, wherein the first side wall has L-type pattern;
Source and drain extension, is arranged in fin, and is positioned at the both sides along first direction of gate stack.
9. semiconductor device as claimed in claim 8, wherein, in fin and/or bottom comprise break-through barrier layer further.
10. semiconductor device as claimed in claim 8, wherein, the thickness of the first spacer material layer is 1 ~ 5nm.
11. semiconductor device as claimed in claim 8, wherein, the material of the first and/or second spacer material layer be selected from silicon nitride, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, low-k materials, diamond like carbon amorphous carbon (DLC), air and combination thereof.
12. semiconductor device as claimed in claim 8, wherein, the second spacer material layer is multilayer laminate constructions.
CN201310215728.1A 2013-05-31 2013-05-31 Semiconductor device and method for manufacturing the same Pending CN104217949A (en)

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Cited By (2)

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CN105489651A (en) * 2014-09-19 2016-04-13 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN110660672A (en) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 Method for forming semiconductor structure

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US20120068268A1 (en) * 2010-09-22 2012-03-22 Hsiao Tsai-Fu Transistor structure and method of fabricating the same

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US20060244051A1 (en) * 2005-04-27 2006-11-02 Kabushiki Kaisha Toshiba Semiconductor manufacturing method and semiconductor device
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Publication number Priority date Publication date Assignee Title
CN105489651A (en) * 2014-09-19 2016-04-13 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN105489651B (en) * 2014-09-19 2019-02-01 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
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Application publication date: 20141217