CN114256350A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114256350A CN114256350A CN202011018886.4A CN202011018886A CN114256350A CN 114256350 A CN114256350 A CN 114256350A CN 202011018886 A CN202011018886 A CN 202011018886A CN 114256350 A CN114256350 A CN 114256350A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and a first type doped semiconductor layer is formed in fin parts on two sides of a grid structure in the first device area; forming a protective layer covering a part of the first type doped semiconductor layer, wherein the protective layer exposes a part of the side wall of the first type doped semiconductor layer facing the second device region; and forming a second type doped semiconductor layer in the fin parts at two sides of the grid electrode structure of the second device area by utilizing an epitaxial growth process, and forming a connecting layer for connecting the second type doped semiconductor layer and the first type doped semiconductor layer in the process of the epitaxial growth process. The connecting layer fills a gap between the first type doped semiconductor layer and the second type doped semiconductor layer, and reduces parasitic capacitance between the source drain plug and the grid structure, so that the electrical performance of the semiconductor is improved.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.
Therefore, in order to better accommodate the reduction of feature size, Semiconductor processes are gradually starting to transition from planar-Oxide-Semiconductor Field-Effect transistors (MOSFETs) to three-dimensional transistors with higher performance, such as fin Field Effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
The epitaxial (Epi for short) process is to grow a layer of single crystal material with the same lattice arrangement as the substrate on a single crystal substrate, wherein the epitaxial layer can be a homogeneous epitaxial layer (Si/Si) or a heterogeneous epitaxial layer (SiGe/S or SiC/Si, etc.); there are also many methods for achieving epitaxial growth including Molecular Beam Epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHV/CVD), atmospheric and reduced pressure epitaxy (ATM & RP Epi), etc.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts located on the substrate, an isolation layer is formed on the substrate exposed out of the fin parts, the isolation layer covers partial side walls of the fin parts, a gate structure crossing the fin parts is formed on the isolation layer, the substrate comprises a first device area and a second device area which are adjacent to each other along the extension direction of the gate structure, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different; forming a first type doped semiconductor layer in the fin parts at two sides of the grid electrode structure in the first device area; forming a protective layer covering a part of the first type doped semiconductor layer, wherein the protective layer exposes a part of the side wall of the first type doped semiconductor layer facing the second device region; after the protective layer is formed, forming a second type doped semiconductor layer in fin parts on two sides of the grid electrode structure of the second device area by utilizing an epitaxial growth process, and forming a connecting layer for connecting the second type doped semiconductor layer and the first type doped semiconductor layer in the epitaxial growth process; forming an interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the interlayer dielectric layer covers the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer; and forming source and drain plugs in the interlayer dielectric layer above the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer, wherein the source and drain plugs are connected with the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the semiconductor device comprises a substrate and a fin part protruding out of the substrate, wherein the substrate comprises a first device region and a second device region which are adjacent; the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different; the device grid structure is positioned on the substrate, and the extending direction of the device grid structure is the same as the arrangement direction of the first device area and the second device area; a first type doped semiconductor layer in the fin portion at both sides of the device gate structure in the first device region; a second type doped semiconductor layer located in the fin portions at two sides of the device gate structure in the second device region; the connecting layer is positioned between the first type doped semiconductor layer and the second type doped semiconductor layer, is used for connecting the second type doped semiconductor layer and the first type doped semiconductor layer, and is made of the same material as the second type doped semiconductor layer; the interlayer dielectric layer is positioned on the substrate exposed out of the grid structure and covers the first type doped semiconductor layer, the second type doped semiconductor layer and the connecting layer; and the source drain plug penetrates through the interlayer dielectric layer above the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer, and is connected with the tops of the first type doped semiconductor layer, the second type doped semiconductor layer and the connecting layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided in the embodiment of the present invention, in a first device region, a first type doped semiconductor layer is formed in fins on both sides of a gate structure, a protection layer covering a part of the first type doped semiconductor layer is formed, the protection layer exposes a part of a sidewall of the first type doped semiconductor layer facing a second device region, and then, by using an epitaxial growth process, a second type doped semiconductor layer is formed in fins on both sides of the gate structure in the second device region, wherein since the protection layer exposes a part of a sidewall of the first type doped semiconductor layer facing the second device region, in the process of the epitaxial growth process, an epitaxial growth is also performed on the basis of a surface of the first type doped semiconductor layer exposed by the protection layer, and therefore, in the process of the epitaxial growth process, and correspondingly, the second type doped semiconductor layer is connected with the first type doped semiconductor layer through the connecting layer, the connecting layer fills a gap between the first type doped semiconductor layer and the second type doped semiconductor layer, and then in the process of forming a source drain plug at the top of the second type doped semiconductor layer and the first type doped semiconductor layer, the connecting layer can be used for defining the etching stop position of an interlayer dielectric layer, the probability that the bottom of the source drain plug extends into the isolating layer is reduced, correspondingly, the parasitic capacitance existing between the source drain plug and the grid structure is reduced, and therefore the electrical property of the semiconductor is improved.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 6-13 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 14 to 15 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention.
Detailed Description
Currently, the electrical performance of semiconductor structures is still to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure. Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, and includes a substrate 10 and a plurality of discrete fins 12 located on the substrate 10, where an isolation layer 11 is formed on the substrate 10 where the fins 12 are exposed, the isolation layer 11 covers a portion of a sidewall of the fin 12, a gate structure (not shown) crossing the fin 12 is formed on the isolation layer 11, and the substrate includes an adjacent PMOS device region 100A and an NMOS device region 100B along a direction perpendicular to an extending direction of the fin 12.
Referring to fig. 2, P-type doped semiconductor layers 14 are formed in the fin portions 12 at both sides of the gate structure of the PMOS device region 100A; and covering a protective layer 13 on the surface of the P-type doped semiconductor layer 14 and the surface of the fin portion 12 of the NMOS device region 100B.
Referring to fig. 3, a mask layer 15 is formed on the PMOS device region 100A, and the mask layer 15 covers the top and the sidewalls of the protection layer 13; in the NMOS device region 100B, the isolation layer 11 is used as an etching stop layer, the protection layer 13 and the fin portion 12 with a partial thickness on both sides of the gate structure are etched, and a groove (not shown) is formed in the fin portion 12.
Referring to fig. 4, an N-type doped semiconductor layer 16 is formed in the recess.
After the N-type doped semiconductor layer 16 is formed, the method further includes: the masking layer 15 is removed.
Referring to fig. 5, an interlayer dielectric layer 17 covering the N-type doped semiconductor layer 16 and the P-type doped semiconductor layer 14 is formed on the substrate; and forming a source drain plug 18 connected with the P-type doped semiconductor layer 14 and the N-type doped semiconductor layer 16 in the interlayer dielectric layer 17.
Specifically, the step of forming the source drain plug 18 includes: etching the interlayer dielectric layer 17 to form contact holes exposing the P-type doped semiconductor layer 14 and the N-type doped semiconductor layer 16 at the same time; source drain plugs 18 are formed in the contact holes.
Researches show that a certain distance is reserved between the adjacent P-type doped semiconductor layer 14 and the adjacent N-type doped semiconductor layer 16 at the boundary between the PMOS device region 100A and the NMOS device region 100B, and accordingly, in the process of etching the interlayer dielectric layer 17 to form a contact hole, the etching depth is not easy to be grasped due to the distance between the P-type doped semiconductor layer 14 and the N-type doped semiconductor layer 16, so that the interlayer dielectric layer 17 between the adjacent P-type doped semiconductor layer 14 and the N-type doped semiconductor layer 16 is easily etched by mistake, and even the isolation layer 11 at the boundary between the PMOS device region 100A and the NMOS device region 100B is etched by mistake, so that the bottom of the source/drain plug 18 extends into the isolation structure 11 (as shown by a dotted line circle in fig. 5), and further parasitic capacitance exists between the source/drain plug 18 and the gate structure, and accordingly, the electrical performance of the semiconductor structure is easily degraded.
In order to solve the technical problem, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts located on the substrate, an isolation layer is formed on the substrate exposed out of the fin parts, the isolation layer covers partial side walls of the fin parts, a gate structure crossing the fin parts is formed on the isolation layer, the substrate comprises a first device area and a second device area which are adjacent to each other along the extension direction of the gate structure, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different; forming a first type doped semiconductor layer in the fin parts at two sides of the grid electrode structure in the first device area; forming a protective layer covering a part of the first type doped semiconductor layer, wherein the protective layer exposes a part of the side wall of the first type doped semiconductor layer facing the second device region; after the protective layer is formed, forming a second type doped semiconductor layer in fin parts on two sides of the grid electrode structure of the second device area by utilizing an epitaxial growth process, and forming a connecting layer for connecting the second type doped semiconductor layer and the first type doped semiconductor layer in the epitaxial growth process; forming an interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the interlayer dielectric layer covers the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer; and forming source and drain plugs in the interlayer dielectric layer above the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer, wherein the source and drain plugs are connected with the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer.
In the solution disclosed in the embodiment of the present invention, in a first device region, a first type doped semiconductor layer is formed in fin portions on both sides of a gate structure, a protective layer covering a part of the first type doped semiconductor layer is formed, the protective layer exposes a part of a sidewall of the first type doped semiconductor layer facing a second device region, and then a second type doped semiconductor layer is formed in the fin portions on both sides of the gate structure in the second device region by using an epitaxial growth process, wherein since the protective layer exposes a part of a sidewall of the first type doped semiconductor layer facing the second device region, in the process of the epitaxial growth process, an epitaxial growth is also performed on the basis of a surface of the first type doped semiconductor layer exposed by the protective layer, and therefore, in the process of the epitaxial growth process, a connection layer connecting the second type doped semiconductor layer and the first type doped semiconductor layer is also formed, correspondingly, the second type doped semiconductor layer is connected with the first type doped semiconductor layer through the connecting layer, the connecting layer fills a gap between the first type doped semiconductor layer and the second type doped semiconductor layer, and then in the process that the second type doped semiconductor layer and the top of the first type doped semiconductor layer form a source drain plug, the connecting layer can be used for defining the etching stop position of an interlayer dielectric layer, the probability that the bottom of the source drain plug extends into the isolating layer is reduced, correspondingly, the parasitic capacitance existing between the source drain plug and the grid structure is reduced, and therefore the electrical performance of the semiconductor is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 6 and 7 in combination, fig. 6 is a top view, fig. 7 is a cross-sectional view taken along a cut line a1a2 in fig. 6, a base (not shown) is provided, the base includes a substrate 100 and a plurality of discrete fins 102 on the substrate 100, an isolation layer 101 is formed on the substrate 100 exposed by the fins 102, the isolation layer 101 covers a portion of a sidewall of the fin 102, a gate structure 135 crossing the fin 102 is formed on the isolation layer 101, and the base includes a first device region 100A and a second device region 100B adjacent to each other along an extending direction of the gate structure 135, the first device region 100A is used for forming a first-type transistor, the second device region 100B is used for forming a second-type transistor, and the first type and the second type are different.
Fig. 6 only illustrates the fin 102 and the gate structure 135 for convenience of illustration.
The substrate is used for providing a process platform for subsequent process procedures. In this embodiment, the substrate is used to form a fin field effect transistor (FinFET). The base includes a substrate 100 and a fin portion protruding from the substrate 100. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 includes a first device region 100A and a second device region 100B, the first device region 100A is used to form a first type transistor, the second device region 100B is used to form a second type transistor, and the first type and the second type are different. Specifically, the first type and the second type are different and refer to: the first type and the second type have different conductivity types. In this embodiment, the first type is a P type, and the second type is an N type. That is, the first device region 100A is a PMOS device region, and the first type transistor is a PMOS transistor; the second device area 100B is an NMOS device area, and the second-type transistor is an NMOS transistor.
In other embodiments, the first type is N-type and the second type is P-type.
In this embodiment, the first device region 100A and the second device region 100B are adjacent regions.
In this embodiment, the substrate 100 of each of the first device region 100A and the second device region 100B has a plurality of discrete fins 102 thereon. In this embodiment, the material of the fin portion 102 is the same as that of the substrate 100, and the material of the fin portion 102 is silicon.
In this embodiment, the method for forming the semiconductor structure further includes: after the fin portion 102 is formed, an isolation layer 101 is formed on the substrate 100 exposed by the fin portion, and the isolation layer 101 covers a part of the sidewall of the fin portion 102. The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 101 is made of silicon nitride.
In this embodiment, the gate structure 135 is a dummy gate structure, and is used to occupy a space for a gate structure of a device to be formed later. Specifically, the material of the gate structure 135 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials.
In this embodiment, the gate structure 135 is located on the substrate 100, and the gate structure 135 crosses over the fin 102 and covers a portion of the top surface and a portion of the sidewall of the fin 102. The gate structures 135 are formed on the substrate in the first device region 100A and the second device region 100B.
In other embodiments, the gate structure may also be a device gate structure for turning on or off a conduction channel during device operation. Specifically, the device gate structure is a metal gate structure and comprises a high-k gate dielectric layer, a work function layer located on the high-k gate dielectric layer, and a gate electrode layer located on the work function layer.
Referring to fig. 8, in the first device region 100A, a first-type doped semiconductor layer 104 is formed in the fin 102 on both sides of the gate structure 135.
The first type doped semiconductor layer 104 serves as a source region or a drain region of a device, and when the semiconductor structure works, the first type doped semiconductor layer 104 provides stress for a channel below the gate structure 135, so that the mobility of carriers is improved.
In this embodiment, the first device region 100A is used to form a PMOS transistor, and the first type doped semiconductor layer 104 is a semiconductor layer doped with P-type ions. The semiconductor layer can be made of silicon or silicon germanium, and the P-type ions are B ions, Ga ions or In ions. By doping the semiconductor layer with P-type ions, the P-type ions substitute for the silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the material of the first-type doped semiconductor layer 104 is SiGeB.
In this embodiment, the first-type doped semiconductor layer 104 is formed by an epitaxial process. In this embodiment, the first-type doped semiconductor layer 104 has a sigma shape.
With combined reference to fig. 8 to 9, a protection layer 103 (as shown in fig. 9) is formed to cover a portion of the first-type doped semiconductor layer 104, and the protection layer 103 exposes a portion of the sidewall of the first-type doped semiconductor layer 104 facing the second device region 100B.
The protection layer 103 is used for protecting the first-type doped semiconductor layer 104 and the fin portion 102, so as to prevent epitaxial growth on the entire surfaces of the first-type doped semiconductor layer 104 and the fin portion 102 when a second-type doped semiconductor layer is formed in the second device region 100B.
The protective layer 103 exposes a portion of a sidewall of the first type doped semiconductor layer 104 facing the second device region 100B, so that when a second type doped semiconductor layer is subsequently formed in fins on both sides of the gate structure of the second device region, epitaxial growth can be performed on the surface of the first type doped semiconductor layer 104 exposed by the protective layer 103 as a base, and thus a connection layer connecting the second type doped semiconductor layer and the first type doped semiconductor layer can be formed.
The material of the protective layer 103 is a dielectric material, so that the protective layer is compatible with a subsequent epitaxial process, and a machine for performing the epitaxial process is prevented from being polluted. The material of the protective layer 103 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, and boron nitride silicon carbide. In this embodiment, the material of the protection layer 103 is silicon nitride.
In this embodiment, the step of forming the protection layer 103 includes: as shown in fig. 8, forming a protective material layer 103a conformally covering the first-type doped semiconductor layer 104, the fin 102 and the isolation layer 101; as shown in fig. 9, a mask layer 105 is formed on the protective material layer 103a, at a boundary between the second device region 100B and the first device region 100A, the mask layer 105 exposes the protective material layer 103a on a partial sidewall of the first type doped semiconductor layer 104, and in the second device region 100B, the mask layer 105 exposes partial protective material layers 103a on two sides of the gate structure 135; and etching a part of the protective material layer 103a by using the mask layer 105 as a mask to expose a part of the fin portion 102 of the second device region 100B and expose a part of the sidewall of the first type doped semiconductor layer 104, wherein the rest of the protective material layer 103a is used as a protective layer 103.
In this embodiment, an anisotropic dry etching process is used to etch part of the protective material layer 103 a. The anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and quite accurate pattern conversion can be obtained, so that the anisotropic dry etching process is favorable for accurately controlling the appearance of the protective layer 103.
After the protective layer 103 is formed, the method further includes: the mask layer 105 is removed.
It should be noted that the thickness of the protective layer 103 is not too small, nor too large. If the thickness of the protective layer 103 is too small, the protective effect of the protective layer 103 on the first-type doped semiconductor layer 104 is easily reduced; if the thickness of the protection layer 103 is too large, a large volume space is occupied, which not only affects the formation quality of the protection layer 103, but also easily affects the volume of the subsequent second type doped semiconductor layer, and affects the stability of the device. For this reason, in the present embodiment, the thickness of the protective layer 103 is in the range of 2 nm to 10 nm.
The mask layer 105 is used as a mask for etching the protective material layer 103a, and is also used as a mask in a subsequent etching process of the fin portion 102 and the protective layer 103 in the second device region 100B.
In this embodiment, the mask layer 105 is made of photoresist.
In this embodiment, after the mask layer 105 is formed, the mask layer 105 covers the top of the protection layer 103, and at the boundary between the second device region 100B and the first device region 100A, the mask layer 105 exposes the protection material layer 103a on the partial side wall of the first type doped semiconductor layer 104.
Since the mask layer 105 does not cover the entire first device region 100A, the protective material layer 103a on the partial sidewall of the first type doped semiconductor layer 104 is exposed at the boundary between the first device region 100A and the second device region 100B, and therefore, after the mask layer 105 is used as a mask and a part of the protective material layer 103a is etched, a part of the sidewall of the first type doped semiconductor layer 104 facing the second device region 100B is exposed (as shown by a dashed circle in fig. 9).
With reference to fig. 9, after exposing a portion of the fin 102 in the second device region 100B and before removing the mask layer 105, the forming method further includes: and etching the fin part 102 with partial thickness at two sides of the gate structure 135 in the second device region 100B by using the mask layer 105 as a mask, and forming a groove 136 in the fin part 102.
The recess 136 provides a spatial location for subsequent epitaxial growth of the second type doped semiconductor layer.
It should be noted that, in the second device region 100B, during the process of etching the fin 102 with a partial thickness on both sides of the gate structure 135, the protective layer 103 on the sidewall of the fin 102 is also etched, and at the position of the groove 136, the top of the remaining protective layer 103 on the sidewall of the fin 102 is flush with the bottom of the groove 136.
The top of the remaining protection layer 103 is flush with the bottom of the recess 136, thereby facilitating an increase in the volume of the second-type doped semiconductor layer 106 subsequently formed in the recess 136.
In this embodiment, in the step of etching the fin portion 102 with the thickness of the two sides of the gate structure 135, a portion of the first-type doped semiconductor layer 104 is also etched, so that the surface of the first-type doped semiconductor layer 104 exposed by the protection layer 103 is a plane.
The surface of the first type doped semiconductor layer 104 exposed by the protective layer 103 is a plane, and provides a good interface foundation for forming a connection layer by using an epitaxial growth process.
In this embodiment, the fin portion 102 is etched by using an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and quite accurate pattern conversion can be obtained, so that the depth, the opening size and the side wall morphology of the groove 136 can be accurately controlled. Moreover, by using an anisotropic dry etching process, after a portion of the first-type doped semiconductor layer 104 is etched, the surface of the first-type doped semiconductor layer 104 exposed by the protective layer 103 is easily made to be a plane.
In this embodiment, the mask layer 105 is made of photoresist, so that after the groove 136 is formed, the mask layer 105 is removed, thereby preventing the mask layer 105 from contaminating a machine for performing an epitaxial process.
Referring to fig. 10, after the protection layer 103 is formed, a second type doped semiconductor layer 106 is formed in the fin 102 on both sides of the gate structure 135 of the second device region 100B by using an epitaxial growth process, and a connection layer 132 connecting the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104 is formed during the epitaxial growth process.
In the process of the epitaxial growth process, a part of the sidewall of the first type doped semiconductor layer 104 of the first device region 100A is exposed in an epitaxial growth environment, and epitaxial growth is performed on the fin portion 102 exposed by the groove 136 as a growth basis, and simultaneously epitaxial growth is performed on the surface of the first type doped semiconductor layer 104 exposed by the protection layer 103 as a growth basis, so that after the second type doped semiconductor layer 106 is formed in the groove 136, the connection layer 132 is further formed between the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104, so that the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104 are connected through the connection layer 132, and the connection layer 132 fills a gap between the first type doped semiconductor layer 104 and the second type doped semiconductor layer 106. The subsequent process further includes forming an interlayer dielectric layer covering the second type doped semiconductor layer 106, the first type doped semiconductor layer 104 and the connecting layer 132, and forming source drain plugs 108 in the interlayer dielectric layer at two sides of the device gate structure, wherein the source drain plugs 108 are connected with the tops of the second type doped semiconductor layer 106, the first type doped semiconductor layer 104 and the connecting layer 132. The connecting layer 132 fills a gap between the first type doped semiconductor layer 104 and the second type doped semiconductor layer 106, so that in the process of forming the source-drain plug 108 on the top of the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104, the connecting layer 132 can be used for defining an etching stop position of an interlayer dielectric layer, the probability that the bottom of the source-drain plug 108 extends into the isolation layer 101 is reduced, correspondingly, the parasitic capacitance between the source-drain plug 108 and the device gate structure is reduced, and the electrical performance of the semiconductor is improved.
Moreover, compared with the solution of forming the connection layer between the second type doped semiconductor layer and the first type doped semiconductor layer by using a deposition process, in the embodiment, the connection layer 132 connecting the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104 is formed during the epitaxial growth process, and the epitaxial growth process only grows in a specific region, thereby having a feature of region selectivity.
In this embodiment, the second device region 100B is used to form an NMOS transistor, the second type doped semiconductor layer 106 is a semiconductor layer doped with N-type ions, the material of the semiconductor layer may be SiP or SiC, and the N-type ions are P ions, As ions, or Sb ions. By doping N-type ions in the semiconductor layer, the N-type ions replace the positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the material of the second type doped semiconductor layer 106 is SiP.
In this embodiment, the semiconductor layer is formed by epitaxial growth, and during the epitaxial growth, the second type doped semiconductor layer 106 is formed by in-situ self-doping N-type ions. In this embodiment, the second type doped semiconductor layer 106 is formed in the groove 136.
It should be noted that, since a part of the sidewall of the first-type doped semiconductor layer 104 in the first device region 100A loses the protection of the protection layer 103, during the process of forming the second-type doped semiconductor layer 106 in the groove, the first-type doped semiconductor layer 104 exposed by the protection layer 103 is also used as a growth basis for performing epitaxial growth, so as to form a connection layer between the second-type doped semiconductor layer 106 and the first-type doped semiconductor layer 104, where the connection layer fills up a gap between the second-type doped semiconductor layer 106 and the first-type doped semiconductor layer 104.
Referring to fig. 12, an interlayer dielectric layer 107 is formed on the substrate 100 where the gate structure 135 is exposed, and the interlayer dielectric layer 107 covers the second type doped semiconductor layer 106, the first type doped semiconductor layer 104 and the connection layer 132.
The interlayer dielectric layer 107 is used for realizing electrical isolation between subsequently formed source and drain plugs, and simultaneously provides a spatial position for the subsequently formed source and drain plugs.
Therefore, the material of the interlayer dielectric layer 107 is a dielectric material. In this embodiment, the material of the interlayer dielectric layer 107 includes SiO2SiN, SiON, SiOC, SiOCH, SiC, SiCN, AlN and Al2O3One or more of (a). In this embodiment, the interlayer dielectric layer 107 is made of SiO2。
Specifically, the step of forming the interlayer dielectric layer 107 includes: forming a dielectric material layer (not shown) covering the second type doped semiconductor layer 106, the first type doped semiconductor layer 104, the connection layer 132 and the gate structure 135; and with the top of the gate structure 135 as a stop position, performing planarization processing on the dielectric material layer, and using the remaining dielectric material layer as the interlayer dielectric layer 107.
In this embodiment, a deposition process (e.g., a chemical vapor deposition process) is used to form the dielectric material layer. In this embodiment, a chemical mechanical polishing process is used to planarize the dielectric material layer.
It should be noted that the gate structure 135 is a dummy gate structure, and therefore, after the interlayer dielectric layer 107 is formed, the forming method further includes: removing the gate structure 135, and forming a gate opening (not shown) in the interlayer dielectric layer 107; a device gate structure (not shown) is formed in the gate opening.
Correspondingly, by forming the connecting layer 132, the parasitic capacitance existing between the subsequent source-drain plug and the device gate structure is reduced, so that the electrical performance of the semiconductor is improved.
The device gate structure is used for conducting on or off of a conducting channel when the device works. Specifically, the device gate structure is a metal gate structure and comprises a high-k gate dielectric layer, a work function layer located on the high-k gate dielectric layer, and a gate electrode layer located on the work function layer.
The high-k gate dielectric layer is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In particular, the material of the high-k gate dielectric layer may be selected from HfO2、ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TiAl, Mo, MoN, AlN and TiAl C.
The gate electrode layer is used for leading out the electrical property of the device gate structure. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W.
With reference to fig. 12 and fig. 13, a source/drain plug 108 is formed in the interlayer dielectric layer 107 above the tops of the second type doped semiconductor layer 106, the first type doped semiconductor layer 104 and the connection layer 132, and the source/drain plug 108 is connected to the tops of the second type doped semiconductor layer 106, the first type doped semiconductor layer 104 and the connection layer 132.
The source-drain plugs 108 are used for electrically connecting the second-type doped semiconductor layer 106 and the first-type doped semiconductor layer 104 with other interconnect structures or external circuits.
In this embodiment, according to the process requirement, the source-drain plug 108 is simultaneously in contact with the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104, so that the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104 are electrically connected.
Specifically, the step of forming the source drain plug 108 includes: as shown in fig. 12, the top portions of the second type doped semiconductor layer 106, the first type doped semiconductor layer 104 and the connection layer 132 are used as etching stop positions, and the interlayer dielectric layer 107 is etched to form a source drain contact hole 131 exposing the second type doped semiconductor layer 106, the connection layer 132 and the first type doped semiconductor layer 104; as shown in fig. 13, a conductive material layer (not shown) is filled in the source drain contact hole 131, and the conductive material layer also covers the top of the interlayer dielectric layer 107; and with the top of the interlayer dielectric layer 107 as a stop position, performing planarization treatment on the conductive material layer, and taking the residual conductive material in the source-drain contact hole 131 as a source-drain plug 108.
Specifically, the source drain contact hole provides a spatial location for forming the source drain plug 108.
In this embodiment, the interlayer dielectric layer 107 is etched by using a dry etching process. Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has a longitudinal etching rate far greater than a transverse etching rate, can obtain quite accurate pattern conversion, and has relatively small damage to the side wall of the interlayer dielectric layer 107, the top of the connecting layer 132, and the tops of the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104.
The connecting layer 132 fills a gap between the second type doped semiconductor layer 106 and the first type doped semiconductor layer 104, so that in the step of etching the interlayer dielectric layer 107 to form the source/drain contact hole 131, the connecting layer 132 protects the interlayer dielectric layer 107 and the isolation structure 101 below the connecting layer, and thus the bottom position of the source/drain plug 108 can be accurately controlled.
In this embodiment, the planarization process is performed by using a chemical mechanical polishing process, which is beneficial to improving the flatness of the top surface of the source/drain plug 108.
In this embodiment, the source/drain plug 108 is made of copper. The resistivity of copper is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the source-drain plug 108, and correspondingly reducing the power consumption. In other embodiments, the material of the source and drain plugs may also be tungsten or cobalt.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 14 to fig. 15, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.
Fig. 14 is a top view, fig. 15 is a cross-sectional view taken along a line b1b2 in fig. 14, and fig. 14 only illustrates the fin and the device gate structure for convenience of illustration.
The semiconductor structure includes: a base (not shown) including a substrate 200 and a fin 202 protruding from the substrate 200, the base including a first device region 200A and a second device region 200B adjacent to each other; the first device region 200A is used to form a first type transistor, the second device region 200B is used to form a second type transistor, the first and second types are different; a device gate structure 235 located on the substrate, wherein an extending direction of the device gate structure 235 is the same as an arrangement direction of the first device region 200A and the second device region 200B; a first type doped semiconductor layer 204 in the fin 202 on both sides of the device gate structure 235 in the first device region 200A; a second type doped semiconductor layer 206 in the fin 202 on both sides of the device gate structure 235 in the second device region 200B; the connecting layer 232 is positioned between the first type doped semiconductor layer 204 and the second type doped semiconductor layer 206, and connects the second type doped semiconductor layer 206 and the first type doped semiconductor layer 204, and the materials of the connecting layer 232 and the second type doped semiconductor layer 206 are the same; an interlayer dielectric layer 207, which is located on the substrate 200 exposed by the device gate structure 235 and covers the first type doped semiconductor layer 204, the second type doped semiconductor layer 206 and the connecting layer 232; and the source-drain plug 208 penetrates through the interlayer dielectric layer 207 above the tops of the second type doped semiconductor layer 206, the first type doped semiconductor layer 204 and the connecting layer 232, and the source-drain plug 208 is connected with the tops of the first type doped semiconductor layer 204, the second type doped semiconductor layer 206 and the connecting layer 232.
In the present embodiment, the semiconductor structure is a fin field effect transistor (FinFET), and the base includes a substrate 200 and a fin 202 located on the substrate 200. In other embodiments, when the semiconductor structure is a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the substrate 200 includes a first device region 200A and a second device region 200B, the first device region 200A is used to form a first type transistor, the second device region 200B is used to form a second type transistor, and the first type and the second type are different. Specifically, the first type and the second type are different and refer to: the first type and the second type have different conductivity types.
In this embodiment, the first type is a P type, and the second type is an N type. That is, the first device region 200A is a PMOS device region, and the first type transistor is a PMOS transistor; the second device region 200B is an NMOS device region, and the second-type transistor is an NMOS transistor. In other embodiments, the first type is N-type and the second type is P-type.
In this embodiment, the substrate 200 of each of the first device region 200A and the second device region 200B has a plurality of discrete fins 202 thereon. In this embodiment, the material of the fin portion 202 is the same as that of the substrate 200, and the material of the fin portion 202 is silicon.
The semiconductor structure further includes: an isolation layer 201 is disposed on the substrate 200 where the fin 202 is exposed. The isolation layer 201 is used to isolate adjacent devices. The material of the isolation layer 201 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 201 is made of silicon nitride.
The device gate structure 235 is used to turn the conduction channel on or off during device operation. Specifically, the device gate structure is a metal gate structure and comprises a high-k gate dielectric layer, a work function layer located on the high-k gate dielectric layer, and a gate electrode layer located on the work function layer.
The high-k gate dielectric layer is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In particular, the material of the high-k gate dielectric layer may be selected from HfO2、ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TiAl, Mo, MoN, AlN and TiAl C.
The gate electrode layer is used to electrically conduct out the device gate structure 235. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W.
The first type doped semiconductor layer 204 serves as a source region and a drain region of the first type transistor, and provides stress for a channel below a gate structure of a device when the semiconductor structure works, so that the mobility of carriers is improved. As an example, the material of the first-type doped semiconductor layer 204 is SiGeB.
In this embodiment, the surface of the first-type doped semiconductor layer 204 in contact with the connection layer 232 is a plane. The connection layer 232 is formed by an epitaxial process, and a plane is formed on a surface of the first-type doped semiconductor layer 204 in contact with the connection layer 232, so that a good interface foundation is provided for the epitaxial process when the connection layer 232 is formed.
The first type doped semiconductor layer 204 serves as a source region and a drain region of the second type transistor, and provides stress for a channel below a gate structure of the device when the semiconductor structure works, so that the mobility of carriers is improved.
The second type doped semiconductor layer 206 is a semiconductor layer doped with N type ions, the material of the semiconductor layer may be Si or SiC, and the N type ions are P ions, As ions, or Sb ions. By doping N-type ions in the semiconductor layer, the N-type ions replace the positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the material of the second type doped semiconductor layer 206 is SiP.
In this embodiment, the connection layer 232 is located between the first type doped semiconductor layer 204 and the second type doped semiconductor layer 206, and connects the second type doped semiconductor layer 206 and the first type doped semiconductor layer 204.
The connecting layer 232 enables the second type doped semiconductor layer to be connected with the first type doped semiconductor layer 204 through the connecting layer, the connecting layer 232 fills a gap between the first type doped semiconductor layer 204 and the second type doped semiconductor layer, and further in the process that the source drain plug 208 is formed at the top of the second type doped semiconductor layer and the top of the first type doped semiconductor layer 204, the connecting layer 232 can be used for defining an etching stop position of the interlayer dielectric layer 207, the probability that the bottom of the source drain plug 208 extends into the isolation layer 201 is reduced, correspondingly, parasitic capacitance existing between the source drain plug 208 and the device grid structure 235 is reduced, and therefore electrical performance of a semiconductor is improved.
Specifically, in the formation process of the semiconductor structure, when the second type doped semiconductor layer 206 is formed, epitaxial growth is further performed based on a portion of the sidewall of the first type doped semiconductor layer facing the second device region as a growth basis, so as to form a connection layer connecting the second type doped semiconductor layer and the first type doped semiconductor layer. Therefore, in the present embodiment, the material of the connection layer 232 is the same as that of the second type doped semiconductor layer 206.
The interlayer dielectric layer 207 is used for electrical isolation between adjacent source drain plugs 208.
Therefore, the material of the interlayer dielectric layer 207 is a dielectric material. In this embodiment, the material of the interlayer dielectric layer 207 includes SiO2SiN, SiON, SiOC, SiOCH, SiC, SiCN, AlN and Al2O3One or more of (a).
The source-drain plugs 208 are used to electrically connect the second-type doped semiconductor layer 206 and the first-type doped semiconductor layer 204 with other interconnect structures or external circuits. In this embodiment, the source-drain plug 208 is simultaneously in contact with the second type doped semiconductor layer 206 and the first type doped semiconductor layer 204, so that the second type doped semiconductor layer 206 and the first type doped semiconductor layer 204 are electrically connected.
In this embodiment, the source-drain plug 208 is made of copper. The resistivity of copper is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the source-drain plug 208, and correspondingly reducing the power consumption. In other embodiments, the material of the source and drain plugs may also be tungsten or cobalt.
In this embodiment, the semiconductor structure further includes: and the protective layer 203 is positioned between the first-type doped semiconductor layer 204 and the interlayer dielectric layer 207, between the interlayer dielectric layer 207 and the isolation layer 201 of the first device region 200A, and between the side wall of the fin 202 of the second device region 200B and the interlayer dielectric layer 207.
The protection layer 203 serves to protect the first-type doped semiconductor layer 204 and the fin portion, so that during the formation of the second-type doped semiconductor layer 206 and the connection layer 232, epitaxial growth at an undesired position is prevented during an epitaxial process. That is, during the process of forming the second-type doped semiconductor layer 206 and the connection layer 232, the first-type doped semiconductor layer 204 and the fin 202 exposed by the protection layer 203 are used as a growth base for epitaxial growth.
The material of the protective layer 203 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride silicon and boron nitride silicon carbide. In this embodiment, the material of the protection layer 203 is silicon nitride.
Note that the thickness of the protective layer 203 is not too small and is not too large. If the thickness of the protective layer 203 is too small, the protective effect of the protective layer 203 on the first-type doped semiconductor layer 204 is easily reduced; if the thickness of the protection layer 203 is too large, a large volume space is occupied, which not only affects the formation quality of the protection layer 203, but also easily affects the volume of the subsequent second type doped semiconductor layer, and affects the stability of the device. For this reason, in the present embodiment, the thickness of the protective layer 203 is in the range of 2 nm to 10 nm.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts located on the substrate, an isolation layer is formed on the substrate exposed out of the fin parts, the isolation layer covers partial side walls of the fin parts, a gate structure crossing the fin parts is formed on the isolation layer, the substrate comprises a first device area and a second device area which are adjacent to each other along the extension direction of the gate structure, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different;
forming a first type doped semiconductor layer in the fin parts at two sides of the grid electrode structure in the first device area;
forming a protective layer covering a part of the first type doped semiconductor layer, wherein the protective layer exposes a part of the side wall of the first type doped semiconductor layer facing the second device region;
after the protective layer is formed, forming a second type doped semiconductor layer in fin parts on two sides of the grid electrode structure of the second device area by utilizing an epitaxial growth process, and forming a connecting layer for connecting the second type doped semiconductor layer and the first type doped semiconductor layer in the epitaxial growth process;
forming an interlayer dielectric layer on the substrate exposed out of the grid structure, wherein the interlayer dielectric layer covers the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer;
and forming source and drain plugs in the interlayer dielectric layer above the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer, wherein the source and drain plugs are connected with the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer.
2. The method of forming a semiconductor structure of claim 1, wherein forming the protective layer comprises: forming a protective material layer which conformally covers the first type doped semiconductor layer, the fin portion and the isolation layer;
forming a mask layer on the protective material layer, wherein the mask layer exposes the protective layer on part of the side wall of the first type doped semiconductor layer at the junction of the second device area and the first device area, and the mask layer exposes the part of the protective layer on two sides of the gate structure in the second device area;
etching part of the protective material layer by taking the mask layer as a mask, exposing part of the fin part of the second device region, exposing part of the side wall of the first type doped semiconductor layer, and taking the rest protective material layer as a protective layer;
the forming method further includes: and removing the mask layer.
3. The method of forming a semiconductor structure of claim 2, wherein after exposing the portion of the fin in the second device region and before removing the mask layer, the method further comprises: etching fin parts with partial thicknesses on two sides of the grid structure in the second device area by taking the mask layer as a mask, and forming grooves in the fin parts;
in the step of forming the second type doped semiconductor layer, the second type doped semiconductor layer is formed in the groove.
4. The method for forming the semiconductor structure according to claim 3, wherein in the second device region, during etching of the fin portion with the partial thickness on both sides of the gate structure, the protective layer on the sidewall of the fin portion is also etched, and at the position of the groove, the top of the remaining protective layer on the sidewall of the fin portion is flush with the bottom of the groove.
5. The method of claim 3, wherein the first-type doped semiconductor layer is sigma-shaped;
and in the step of etching the fin parts with partial thicknesses on two sides of the grid structure, etching partial first type doped semiconductor layer, so that the surface of the first type doped semiconductor layer exposed out of the protective layer is a plane.
6. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the source and drain plugs comprises: etching the interlayer dielectric layer by taking the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer as etching stop positions to form source drain contact holes exposing the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer;
filling a conductive material layer in the source drain contact hole, wherein the conductive material layer also covers the top of the interlayer dielectric layer;
and flattening the conductive material layer by taking the top of the interlayer dielectric layer as a stop position, wherein the residual conductive material in the source and drain contact hole is taken as a source and drain plug.
7. The method of forming a semiconductor structure of claim 2, wherein an anisotropic dry etch process is used to etch a portion of the protective material layer.
8. The method for forming the semiconductor structure according to claim 3 or 5, wherein the fin portions with the partial thickness on the two sides of the gate structure are etched by an anisotropic dry etching process.
9. The method of claim 1, wherein the material of the protective layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride boron silicon nitride, and boron carbon silicon nitride.
10. The method of forming a semiconductor structure of claim 1, wherein a thickness of the protective layer is in a range of 2 nanometers to 10 nanometers.
11. A semiconductor structure, comprising:
the semiconductor device comprises a substrate and a fin part protruding out of the substrate, wherein the substrate comprises a first device region and a second device region which are adjacent; the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different;
the device grid structure is positioned on the substrate, and the extending direction of the device grid structure is the same as the arrangement direction of the first device area and the second device area;
a first type doped semiconductor layer in the fin portion at both sides of the device gate structure in the first device region;
a second type doped semiconductor layer located in the fin portions at two sides of the device gate structure in the second device region;
the connecting layer is positioned between the first type doped semiconductor layer and the second type doped semiconductor layer, is used for connecting the second type doped semiconductor layer and the first type doped semiconductor layer, and is made of the same material as the second type doped semiconductor layer;
the interlayer dielectric layer is positioned on the substrate exposed out of the grid structure and covers the first type doped semiconductor layer, the second type doped semiconductor layer and the connecting layer;
and the source drain plug penetrates through the interlayer dielectric layer above the tops of the second type doped semiconductor layer, the first type doped semiconductor layer and the connecting layer, and is connected with the tops of the first type doped semiconductor layer, the second type doped semiconductor layer and the connecting layer.
12. The semiconductor structure of claim 11, wherein the semiconductor structure further comprises: and the protective layers are positioned between the first type doped semiconductor layer and the interlayer dielectric layer, between the interlayer dielectric layer and the isolation layer of the first device area, and between the fin part side wall of the second device area and the interlayer dielectric layer.
13. The semiconductor structure of claim 11, wherein a surface of the first-type doped semiconductor layer in contact with the connection layer is planar.
14. The semiconductor structure of claim 12, wherein the protective layer has a thickness in a range from 2 nanometers to 10 nanometers.
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