CN109545734A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109545734A CN109545734A CN201710866764.2A CN201710866764A CN109545734A CN 109545734 A CN109545734 A CN 109545734A CN 201710866764 A CN201710866764 A CN 201710866764A CN 109545734 A CN109545734 A CN 109545734A
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 239000000463 material Substances 0.000 claims description 128
- 239000002019 doping agent Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 150000002500 ions Chemical class 0.000 claims description 29
- 229910021332 silicide Inorganic materials 0.000 claims description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 4
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 303
- 229920002120 photoresistant polymer Polymers 0.000 description 28
- 230000015572 biosynthetic process Effects 0.000 description 27
- 238000010586 diagram Methods 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 238000002955 isolation Methods 0.000 description 12
- 238000001039 wet etching Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- -1 for example Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of semiconductor structure and forming method thereof, wherein method includes: offer substrate, and the substrate includes area of grid, has source and drain doping area in the substrate between the area of grid；Electric connection layer is formed in the source and drain doping area；It forms gate structure on the substrate and dielectric layer, the gate structure is located in area of grid substrate, part of grid pole structure dielectric layer covering electric connection layer and be exposed；The dielectric layer in the source and drain doping area is removed, until exposing electric connection layer, forms contact hole, the side wall of the contact hole exposes gate structure.The method can reduce the difficulty to form contact hole.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
MOS (Metal-oxide-semicondutor) transistor is a kind of important semiconductor devices, the basic knot of MOS transistor
Structure includes: semiconductor substrate；Positioned at the gate structure of semiconductor substrate surface；In the semiconductor substrate of gate structure side
Source region and the gate structure other side semiconductor substrate in drain region.
With further decreasing for characteristic size, the distance between neighboring gate structures reduce, so that in above-mentioned grid knot
Being formed in gap between structure becomes more difficult to connect the technique of the contact hole of source region, drain region and upper layer metal wire, therefore
Introduce the formation process of self-aligned contact hole.
Currently, the preparation method of more common self-aligned contact hole includes: to form grid knot in semiconductor substrate surface
Structure；Side wall is formed on gate structure sidewall surface；Protective layer is formed in gate structure top surface；Form covering semiconductor lining
Bottom, protective layer and side wall interlayer dielectric layer；The contact hole for running through interlayer dielectric layer thickness is formed in interlayer dielectric layer, it is described
Contact hole is between adjacent gate structure.
However, the formation difficulty of self-aligned contact hole is larger.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, to improve semiconductor devices
Performance.
In order to solve the above technical problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided,
The substrate includes area of grid, has source and drain doping area in the substrate between the area of grid；In the source and drain doping area
Upper formation electric connection layer；It forms gate structure on the substrate and dielectric layer, the gate structure is located at area of grid substrate
On, part of grid pole structure dielectric layer covering electric connection layer and be exposed；Remove Jie in the source and drain doping area
Matter layer forms contact hole until exposing electric connection layer, and the side wall of the contact hole exposes gate structure.
Optionally, the thickness of the electric connection layer are as follows: 20 nanometers~50 nanometers.
Optionally, the height ratio of the thickness of the electric connection layer and gate structure are as follows: 1:3~1:2.
Optionally, the depth-to-width ratio of the contact hole are as follows: 3:1~8:1.
Optionally, the dielectric layer includes first medium layer and the second dielectric layer on first medium layer；It is described
First medium floor, second dielectric layer, gate structure and the forming step in source and drain doping area include: in the area of grid substrate
Form pseudo- grid structure；The source and drain doping area is formed in the substrate of dummy gate structure two sides；It is mixed in the substrate and source and drain
The first medium floor is formed in miscellaneous area, the first medium layer covers the side wall of pseudo- grid structure, and exposes pseudo- grid structure
Top surface；Dummy gate structure is removed, forms pseudo- grid opening in the first medium layer；It is formed in the pseudo- grid opening
Gate structure；Second dielectric layer is formed on the first medium layer and gate structure.
Optionally, it is formed before the first medium layer, forms the electric connection layer；The substrate includes fin, described
Gate structure is across the fin.
Optionally, when the material of the electric connection layer is metal, the forming step of the electric connection layer includes: in the base
On bottom and source and drain doping area and the side wall of pseudo- grid structure and top surface form initial electrical connection film；The initial electricity in removal part
Junctional membrane, forms electrical connection film, and the top surface of the electrical connection film is lower than the top surface of pseudo- grid structure；Along perpendicular to described
On fin extending direction, the electrical connection film between source and drain doping area is removed, the electric connection layer is formed；The metal include: tungsten,
Aluminium or copper.
Optionally, described when the electric connection layer includes doped layer and metal silicide layer on doped layer
The forming step of electric connection layer includes: in the substrate and source and drain doping area and the side wall and top surface of pseudo- grid structure
Form initial dopant material layer；Part initial dopant material layer is removed, initial dopant film, the top of the initial dopant film are formed
Surface is lower than the top surface of pseudo- grid structure；Removal is perpendicular between source and drain doping area on the fin extending direction in substrate
Initial dopant film forms the doping；Metalized is carried out the part doping, the doped layer is formed and is located at
Metal silicide layer on doped layer.
Optionally, the material of the doped layer is semiconductor material；The material of the doped layer includes silicon, the doped layer
In have Doped ions.
Optionally, the concentration of the Doped ions are as follows: 1.0e14atm/cm2~1e20atm/cm2。
Optionally, the gate structure includes: gate dielectric layer and the grid layer on gate dielectric layer；The contact hole
Forming step further include: the dielectric layer on removal gate structure, until exposing grid layer.
Optionally, it is formed after the contact hole, the forming method further include: the electric connection layer in the contact hole
Upper formation plug.
The present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate include area of grid；Positioned at the grid
Gate structure on the substrate areas of pole has source and drain doping area in the substrate between the gate structure；It is mixed positioned at the source and drain
Electric connection layer in miscellaneous area；Dielectric layer in substrate and electric connection layer, the dielectric layer is interior to have contact hole, the contact
Hole bottom exposes the top surface of electric connection layer, and the side wall of the contact hole exposes gate structure.
Optionally, the thickness of the electric connection layer are as follows: 20 nanometers~50 nanometers.
Optionally, the height ratio of the thickness of the electric connection layer and gate structure are as follows: 1:3~1:2.
Optionally, the depth-to-width ratio of the contact hole are as follows: 3:1~8:1.
Optionally, when the material of the electric connection layer is metal, the material of the electric connection layer includes: tungsten, aluminium or copper.
Optionally, the electric connection layer includes doped layer and the metal silicide layer on doped layer；The doping
The material of layer is semiconductor material；The material of the doped layer includes silicon, has Doped ions in the doped layer；The metal
The material of silicide layer includes: titanium-silicon compound or nickel-silicon compound.
Optionally, the concentration of the Doped ions are as follows: 1.0e14atm/cm2~1e20atm/cm2。
Optionally, the semiconductor structure further include: the plug in contact hole.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
It in the forming method for the semiconductor structure that technical solution of the present invention provides, is formed before the dielectric layer, forms electricity
Articulamentum, the electric connection layer for realizing source and drain doping area be subsequently formed being electrically connected between plug.It is electrically connected due to described
Floor is connect to be located in source and drain doping area, therefore, the depth-to-width ratio of the groove between source and drain doping area two sides gate structure compared with
Small, the amount for enabling etching gas to arrive at channel bottom is more, then less in the by-product of channel bottom accumulation, so that institute's shape
It is easier to be opened at the bottom of contact hole.It is subsequent that plug is formed in contact hole, enable plug and source and drain doping area real
It is now electrically connected, is conducive to the performance for improving semiconductor devices.
Detailed description of the invention
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure；
Fig. 4 to Figure 32 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
As described in background, the formation difficulty of the self-aligned contact hole is larger.
Fig. 1 to Fig. 3 is a kind of structural schematic diagram of each step of forming method of semiconductor structure.
Referring to FIG. 1, providing substrate 100, the substrate 100 includes area of grid A；In the area of grid A substrate 100
The pseudo- grid structure (not shown) of upper formation；Source and drain doping area 102 is formed in substrate 100 between dummy gate structure；?
First medium floor 103 is formed in the substrate 100 and source and drain doping area 102, the first medium layer 103 covers pseudo- grid structure
Side wall, and expose the top surface of pseudo- grid structure；Dummy gate structure is removed, is formed in the first medium layer 103 pseudo-
Grid opening (not shown)；Gate structure 101 is formed in the pseudo- grid opening；In the first medium layer 103 and grid
Second dielectric layer 104 is formed in structure 101.
Referring to FIG. 2, forming photoresist 105 in the second dielectric layer 104, there is exposure mask in the photoresist 105
It is open (not marked in figure), the mask open is located in source and drain doping area 102, and mask open edge is parallel to substrate
Size in 100 surface directions is greater than the spacing between neighboring gate structures 101.
Referring to FIG. 3, being exposure mask with the photoresist 105, the first medium layer 103 and second dielectric layer 104 are etched,
Until exposing the top surface in source and drain doping area 102, is formed and connect in the first medium layer 103 and second dielectric layer 104
Contact hole 106, the contact hole 106 expose the side wall of gate structure 101；It is formed after the contact hole 106, removes photoresist
105。
In the above method, with the continuous improvement of semiconductor devices integrated level, the spacing between neighboring gate structures 101 is not
It is disconnected to reduce, so that the depth-to-width ratio of the groove constituted between neighboring gate structures 101 is increasing.The depth-to-width ratio of the groove
It is increasing, so that it is more and more difficult to form contact hole 106.Specifically, be exposure mask with the photoresist 105, described the is etched
The technique of one dielectric layer 103 and second dielectric layer 104 includes: dry etch process, the etching gas in the dry etch process
Body includes carbon fluorine gas and oxygen.The carbon fluorine gas easily generates polymer during the dry etch process, and oxygen
Gas can consume the polymer.As the depth-to-width ratio of groove between neighboring gate structures 101 constantly increases, so that oxygen arrives at
The amount of the channel bottom is less, so that oxygen is smaller to the consumption ability of polymer, then remaining polymer is deposited in groove
Bottom so that the bottom of formed contact hole 106 is unopened.It is subsequent to form plug in contact hole 106 so that plug with
Source and drain doping area 102 is difficult to realize be electrically connected, and is unfavorable for improving the performance of semiconductor devices.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: the grid
There is in substrate source and drain doping area between region；Gate structure is formed in the area of grid substrate；In the source and drain doping
Electric connection layer is formed in area；The dielectric layer in the source and drain doping area is removed, until exposing electric connection layer, forms contact hole,
The contact hole side wall exposes gate structure.The method can reduce the difficulty to form contact hole, is conducive to improve and partly lead
The performance of body device.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 4 to Figure 32 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Fig. 4 and Fig. 5 are please referred to, Fig. 4 is the top view that Fig. 5 ignores isolation structure, and Fig. 5 is that Fig. 4 shows along the section of A-A1 line
It is intended to, substrate 200 is provided, the substrate 200 includes several area of grid I；It is formed in I substrate 200 of area of grid pseudo-
Grid structure 203 has side wall 206 on the side wall of dummy gate structure 203；In 206 two sides of dummy gate structure 203 and side wall
Source and drain doping area is formed in substrate 200.
In the present embodiment, the substrate 200 includes the first area B and the second area C, and the firstth area B is used to form NMOS
Transistor, the secondth area C are used to form PMOS transistor.Several puppet grid structures 203 are located in the first area B and the 2nd C
I substrate 200 of area of grid on.
In other embodiments, the substrate only includes the firstth area, and firstth area is used to form NMOS transistor；Or
Person, firstth area are used to form PMOS transistor.
In the present embodiment, the substrate 200 includes: substrate 201 and the fin 202 on the substrate 201.At it
In his embodiment, the substrate can also be planar substrates, for example, silicon base, germanium substrate or silicon-Germanium base.
In the present embodiment, the material of the fin 202 and substrate 201 is silicon.In other embodiments, the fin and
The material of substrate includes germanium or SiGe.
In the present embodiment, the step of forming substrate 200 includes: offer initial substrate；To the initial substrate into
Row is graphical, forms substrate 201 and the fin 202 on the substrate 201.
Also there is isolation structure (not marking in figure) in the substrate, the isolation structure covers the portion of the fin 202
Divide side wall, and the top surface of the isolation structure is lower than the top surface of the fin 202.
In the present embodiment, the material of the isolation structure is silica.In other embodiments, the isolation structure
Material can also be silicon oxynitride.
Dummy gate structure 203 includes: the pseudo- gate dielectric layer of the partial sidewall and top surface positioned at the fin 202
(not marked in figure) and the dummy gate layer (not marked in figure) on pseudo- gate dielectric layer.
The material of the puppet gate dielectric layer includes: silica, and the material of the dummy gate layer includes: silicon.
In the present embodiment, it is three with the number of dummy gate structure 203 to be illustrated.
The top of dummy gate structure 203 has mask layer (not marking in figure), the material of the mask layer are as follows: nitridation
Silicon.In other embodiments, the material of the mask layer includes: silicon oxynitride.
The formation process of the mask layer includes: chemical vapor deposition process.
The mask layer is used to be formed the exposure mask of dummy gate structure 203 as etching.
There is side wall 206 on the side wall of dummy gate structure 203.The material of the side wall 206 includes: silicon nitride.It is described
Side wall 206 protects the side wall of pseudo- grid structure 203 for defining the position for being subsequently formed source and drain doping area.
In the present embodiment, the source and drain doping area in the 203 two sides fin 202 of the firstth area B puppet grid structure is the first source
Doped region 204 is leaked, the source and drain doping area in the 203 two sides fin 202 of the secondth area C puppet grid structure is the second source and drain doping area
205。
The forming step in first source and drain doping area 204 includes: the fin in 203 two sides of the firstth area B puppet grid structure
The first source and drain opening is formed in portion 202；The first epitaxial layer is formed in first source and drain is open；In first epitaxial layer
The first source and drain ion is mixed, first source and drain doping area 204 is formed.
The material of first epitaxial layer and the conduction type of the first source and drain ion are related with the type of transistor.
In the present embodiment, the firstth area B is used to form NMOS transistor, and the material of first epitaxial layer includes:
Silicon carbide or silicon, the first source and drain ion are N-type ion, such as: phosphonium ion or arsenic ion.
In other embodiments, firstth area is used to form PMOS transistor, and the material of first epitaxial layer includes:
SiGe or silicon, first ion are P-type ion, such as: boron ion.
The forming step in second source and drain doping area 205 includes: the fin in 203 two sides of the secondth area C puppet grid structure
The second source and drain opening is formed in portion 202；The second epitaxial layer is formed in second source and drain is open；In second epitaxial layer
The second source and drain ion is mixed, second source and drain doping area 205 is formed.
The material of second epitaxial layer and the conduction type of the second source and drain ion are related with the type of transistor.
In the present embodiment, the secondth area C is used to form PMOS transistor, and the material of second epitaxial layer includes:
SiGe or silicon, the second source and drain ion are P-type ion, such as: boron ion.
In other embodiments, secondth area is used to form NMOS transistor, and the material of second epitaxial layer includes:
Silicon carbide or silicon, the second source and drain ion are N-type ion, such as: phosphonium ion or arsenic ion.
Referring to FIG. 6, in the substrate 200, in source and drain doping area and pseudo- grid structure 203 and the side wall of side wall 206
The first stop-layer 207 of upper formation.
It should be noted that Fig. 6 is structural schematic diagram on the basis of Fig. 5.
The material of first stop-layer 207 includes: silicon nitride, the including: of formation process of first stop-layer 207
Learn gas-phase deposition.
In the present embodiment, first stop-layer 207 covers the first source and drain doping area 204 and the second source and drain doping area
205 top surface.
First stop-layer 207 for it is subsequent in source and drain doping area formed contact hole when, as etching stop layer.
Referring to FIG. 7, the first stop-layer 207 at the top of removal source and drain doping area, exposes the top table in source and drain doping area
Face.
It should be noted that Fig. 7 is structural schematic diagram on the basis of Fig. 6.
In the present embodiment, it removes the first stop-layer 207 at the top of source and drain doping area to refer specifically to: the first source and drain of removal
First stop-layer 207 at 205 top of doped region 204 and the second source and drain doping area.
In the present embodiment, first stop-layer at 205 top of the first source and drain doping area 204 and the second source and drain doping area is removed
207, it exposes the top surface in the first source and drain doping area 204 and the second source and drain doping area 205, is advantageously implemented and is subsequently formed
Electric connection layer is realized with the second source and drain doping area 205 with the first source and drain doping area 204 and electric connection layer and is electrically connected.
The technique for removing the first stop-layer 207 at the top of source and drain doping area includes: dry etch process and wet etching work
The combination of one or both of skill.
Remove the first stop-layer 207 at the top of source and drain doping area, comprising: electrical connection is formed in the source and drain doping area
Layer.In the present embodiment, the electric connection layer includes: doped layer and the metal silicide layer on doped layer.Specifically ask
With reference to Fig. 8 to Figure 31.
Referring to FIG. 8, forming initial dopant material layer 208 in the substrate 200 and source and drain doping area.
It should be noted that Fig. 8 is structural schematic diagram on the basis of Fig. 7.
In the present embodiment, the material of the initial dopant material layer 208 is semiconductor material, the initial dopant material
Layer 208 includes silicon, has Doped ions in the initial dopant material layer 208.
In the present embodiment, the material of the initial dopant material layer 208 be semiconductor material so that metallic pollution compared with
It is small, be conducive to the performance for improving semiconductor devices.
The formation process of the initial electrical connection material membrane 208 includes: doping process in situ.
The concentration of the Doped ions are as follows: 1.0e14atm/cm2~1e20atm/cm2。
The incorporation ion makes the electric conductivity for being formed by initial electrical connection film 208 stronger, is conducive to improve subsequent shape
At electric connection layer and source and drain doping area electrology characteristic.
In the present embodiment, positioned at the first area B and the Doped ions in the initial dopant material layer 208 of the second area C
It is identical, the complexity of technique is advantageously reduced, cost is reduced.
In other embodiments, the conduction type and first of the Doped ions in the initial dopant material layer in the firstth area
The conduction type of the first source and drain ion in source and drain doping area is identical；The Doped ions in the initial dopant material layer in the secondth area
Conduction type it is identical as the conduction type of the second source and drain ion in the second source and drain doping area.
The thickness of the initial dopant material layer 208 are as follows: 150 nanometers~250 nanometers, the initial dopant material layer 208
Thickness determine the thickness of initial dopant film being subsequently formed.
The initial dopant material layer 208 is for being subsequently formed initial dopant film.
Referring to FIG. 9, removal part initial dopant material layer 208, forms initial dopant film 258, the initial dopant film
258 top is lower than the top surface of pseudo- grid structure 203.
It should be noted that Fig. 9 is structural schematic diagram on the basis of Fig. 8.
The technique of removal part initial dopant material layer 208 includes: one in dry etch process and wet-etching technology
Kind or two kinds of combinations.
Initial dopant film 258 in source and drain doping area is for being subsequently formed doping.
The top of the initial dopant film 258 is lower than the top surface of pseudo- grid structure 203, is conducive to be subsequently formed contact
Hole.
The ratio of 203 height of 258 thickness of initial dopant film and pseudo- grid structure are as follows: 1:3~1:2.The initial dopant film
The ratio of 203 height of 258 thickness and pseudo- grid structure determines the ratio of the electric connection layer thickness being subsequently formed and gate structure height.
Figure 10 to Figure 12 is please referred to, Figure 10 is the top view that Figure 11 and Figure 12 ignores isolation structure, and Figure 11 is Figure 10 along A-
The diagrammatic cross-section of A1 line, Figure 12 are diagrammatic cross-section of the Figure 10 along B-B1 line, are formed after initial dopant film 258, described
First material layer 209 is formed on initial dopant film 258；The first bottom anti-reflection layer (figure is formed in the first material layer 209
In do not mark)；It is formed after the first bottom anti-reflection layer, forms the first photoresist 210 in source and drain doping area.
It should be noted that the profile direction of Figure 11 is consistent with the profile direction of Fig. 5.
The material of the first material layer 209 includes: amorphous carbon, and the formation process of the first material layer 209 includes:
Spin coating proceeding.The first material layer 209 is used for the subsequent pattern transfer by photoresist to first material layer 209, and as rear
The mask layer of continuous etching technics.
The material of first bottom anti-reflection layer includes: bottom anti-reflective material.First bottom anti-reflection layer is used
The refraction and reflection of light are reduced when post-exposure development.
First photoresist 210 is located in source and drain doping area, is conducive to initial between subsequent removal source and drain doping area
Doping 258.
Figure 13 and Figure 14 are please referred to, is exposure mask with first photoresist 210, etches the first bottom anti-reflection layer, first
Material layer 209 (see Figure 12) and initial dopant film 258 (see Figure 12), until isolation structure (not marking in figure) is exposed, in source
It leaks and forms doping 211 on doped region；It is formed after the doping 211, removes the first photoresist 210 (see Figure 11), first
Bottom anti-reflection layer and first material layer 209 (see Figure 11), expose the top surface of electric connection layer 211.
It should be noted that Figure 13 is structural schematic diagram on the basis of Figure 11, Figure 14 is structure on the basis of Figure 12
Schematic diagram.
It is exposure mask with first photoresist 210, etches the first bottom anti-reflection layer, first material layer 209 and initially mix
The technique of miscellaneous film 258 includes: one of dry etch process and wet-etching technology or two kinds of combinations.
The thickness of the doping 211 is determined by the thickness of initial dopant film 208.
The thickness of the doping 211 are as follows: 20 nanometers~50 nanometers, the meaning of the thickness of the doping 211 is selected to exist
In: if the thickness of the doping 211 less than 20 nanometers so that the depth for the groove that the neighboring gate structures being subsequently formed are constituted
Width is bigger, so that the difficulty for being subsequently formed contact hole is larger；If the thickness of the doping 211 is greater than 50 nanometers, described to mix
The too high in resistance of miscellaneous film 211 is unfavorable for improving the performance of semiconductor devices.
The ratio of 203 height of 211 thickness of doping and pseudo- grid structure is by 258 thickness of initial dopant film and pseudo- grid
The ratio of 203 height of structure is determined.The ratio of 203 height of 211 thickness of doping and pseudo- grid structure are as follows: 1:3~1:2.
The meaning of the ratio of 203 height of 211 thickness of doping and pseudo- grid structure is selected to be: if the doping 211
Thickness and the ratio of pseudo- 203 height of grid structure are less than 1:3 so that the depth-to-width ratio for the groove that subsequent neighboring gate structures are constituted still compared with
Greatly, so that the difficulty for being subsequently formed contact hole is still larger；If the ratio of 203 height of 211 thickness of doping and pseudo- grid structure is big
It is excessive in the resistance of 1:2, the doping 211, it is unfavorable for improving the performance of semiconductor devices.
Along perpendicular on 202 extending direction of fin, the initial dopant film 258 between source and drain doping area is removed, after being conducive to
Continue and form dielectric layer on doping 211, the dielectric layer is for realizing the electric isolution between doping 211.
The technique for removing the first photoresist 209, the first bottom anti-reflection layer and first material layer 209 includes: cineration technics.
The first photoresist 209, the first bottom anti-reflection layer and first material layer 209 are removed, the top of doping 211 is exposed
Portion is conducive to the subsequent formation first medium layer on doping 211.
Figure 15 is please referred to, in the substrate 200 and doping 211 and the side wall and top surface of pseudo- grid structure 203
Form first medium film 212.
It should be noted that Figure 15 is structural schematic diagram on the basis of Figure 13.
The material of the first medium film 212 includes: silica, the including: of formation process of the first medium film 212
Learn gas-phase deposition.The first medium film 212 formed using chemical vapor deposition process is between adjacent pseudo- grid structure 203
The filling capacity of groove is stronger, and the isolation performance of first medium film 212 is preferable.
The first medium film 212 is for being subsequently formed first medium layer.
Figure 16 is please referred to, the first medium film 212 is planarized, until exposing covering for pseudo- 203 top surface of grid structure
Film layer (not shown) forms first medium layer 213.
It should be noted that Figure 16 is structural schematic diagram on the basis of Figure 15.
The technique for planarizing the first medium film 212 includes: chemical mechanical milling tech.
The first medium film 212 is planarized, the mask layer at pseudo- 203 top of grid structure is exposed, is conducive to subsequent removal
Pseudo- grid structure 203.
Figure 17 is please referred to, pseudo- grid structure 203 is removed, pseudo- grid opening is formed in the first medium layer 213 and (does not show in figure
Out)；Initial gate structure (not shown) is formed in the pseudo- grid opening；Part initial gate structure is removed, grid are formed
Pole structure 214 and the first opening (not marked in figure) on gate structure 214；It is described first opening in and first medium
Protective film 215 is formed on layer 213.
The step of removing pseudo- grid structure 203 includes: to remove pseudo- gate dielectric layer；After removing pseudo- gate dielectric layer, pseudo- grid are removed
Pole layer.
The technique for removing pseudo- gate dielectric layer includes: one of dry etch process and wet-etching technology or two kinds of groups
It closes.
The technique for removing dummy gate layer includes: one of dry etch process and wet-etching technology or two kinds of groups
It closes.
Initial gate structure includes: gate dielectric layer and the initial gate layer on gate dielectric layer.
The material of the gate dielectric layer includes high K dielectric material, and high K dielectric material refers to that dielectric constant is greater than 3.9
Material, such as: HfO2、HfSiON、HfAlO2、ZrO2Or Al2O3.The material of the initial gate layer is metal, such as: tungsten.
The forming step of the gate structure 214 includes: removal part initial gate layer, forms grid layer.The grid
Structure 214 includes: the gate dielectric layer and the grid layer on gate dielectric layer.
The technique for removing part initial gate layer includes: wet-etching technology.
The material of the protective film 215 includes: silicon nitride, and the formation process of the protective film 215 includes: chemical vapor deposition
Product technique or physical gas-phase deposition.
The protective film 215 is for being subsequently formed protective layer.
Figure 18 is please referred to, the protective film 215 (see Figure 17) is planarized, until exposing the top of first medium layer 213
Surface forms protective layer 216 on gate structure 214.
The technique for planarizing the protective film 215 includes: chemical mechanical milling tech.
The material of the protective layer 216 includes: silicon nitride, and the protective layer 216 is used to protect the top of gate structure 214
Surface.
Figure 19 to Figure 21 is please referred to, Figure 19 is the top view that Figure 20 and Figure 21 ignores isolation structure, and Figure 20 is Figure 19 along A-
The diagrammatic cross-section of A1 line, Figure 21 is diagrammatic cross-section of the Figure 19 along B-B1 line, in the substrate 200, protective layer 216 and first
Second dielectric layer 217 is formed on dielectric layer 213；The second stopper film 218 is formed in the second dielectric layer 217；Described
Second material layer 219 is formed on two stopper films 218；The second bottom anti-reflection layer is formed in the second material layer (in figure not
It marks)；The second photoresist 220 is formed in the second bottom anti-reflection layer between the source and drain doping area.
The material of the second dielectric layer 217 includes: silica, the including: of formation process of the second dielectric layer 217
Learn gas-phase deposition.
The dielectric layer includes: first medium layer 213 and the second dielectric layer 217 on first medium layer 213.
The material of second stopper film 218 includes: titanium nitride, the including: of formation process of second stopper film 218
Learn gas-phase deposition.
Second stopper film 218 is for being subsequently formed the second stop-layer.
Material, formation process and the work of the material of second material layer 219, formation process and effect and first material layer 209
With identical, this will not be repeated here.
The material of second bottom anti-reflection layer is identical as the material of the first bottom anti-reflection layer, and this will not be repeated here.
Second photoresist 220 is used to be subsequently formed the mask layer of the second stop-layer.
Please referring to Figure 22 to 24, Figure 22 is the top view that Figure 23 and Figure 24 ignores isolation structure, and Figure 23 is Figure 22 along AA1 line
Diagrammatic cross-section, it is exposure mask with second photoresist 220 that Figure 24, which is diagrammatic cross-section of the Figure 22 along BB1 line, etching second
Bottom anti-reflection layer, second material layer 219 and the second stopper film 218, until exposing the top table of second dielectric layer 217
Face forms the second stop-layer 221 in the second dielectric layer 217 between the source and drain doping area；Form second stop-layer
After 221, the second photoresist 220 of removal, the second bottom anti-reflection layer and second material layer 219 expose the second stop-layer 221
Top surface.
It should be noted that Figure 22 is structural schematic diagram on the basis of Figure 19, Figure 23 is structure on the basis of Figure 20
Schematic diagram, Figure 24 are structural schematic diagrams on the basis of Figure 21.
The formation process of second stop-layer 221 include: one of dry etch process and wet-etching technology or
Two kinds of person combinations.
The technique for removing the second photoresist 220, the second bottom anti-reflection layer and second material layer 219 includes: cineration technics.
Etching stop layer when second stop-layer 221 is open for subsequent shape second.
Figure 25 to Figure 27 is please referred to, Figure 25 is the top view that Figure 26 and Figure 27 ignores isolation structure, and Figure 26 is Figure 25 along AA1
The diagrammatic cross-section of line, Figure 27 is diagrammatic cross-section of the Figure 25 along BB1 line, in the second dielectric layer 217 and the second stop-layer
Third material layer 222 is formed on 221；Third bottom anti-reflection layer (not marking in figure) is formed in the third material layer 222；
Third photoresist 223 is formed in the third bottom anti-reflection layer.
It should be noted that Figure 25 is structural schematic diagram on the basis of Figure 22, Figure 26 is structure on the basis of Figure 23
Schematic diagram, Figure 27 are structural schematic diagrams on the basis of Figure 24.
Material, formation process and the work of the material of third material layer 222, formation process and effect and first material layer 209
With identical, this will not be repeated here.
The material of third bottom anti-reflection layer is identical as the material of the first bottom anti-reflection layer, and this will not be repeated here.
The third photoresist 223 is used to be subsequently formed the mask layer of the second opening.
Figure 28 is please referred to, is exposure mask with the third photoresist 223, etches the third bottom anti-reflection layer, third material
The bed of material 222, second dielectric layer 217 and first medium layer 213 form the second opening 224 until exposing doping 211；It is formed
After second opening 224, removal third photoresist 223, third bottom anti-reflection layer and third material layer 222 expose
The top of second dielectric layer 217.
It should be noted that Figure 28 is structural schematic diagram on the basis of Figure 26.
It is described second opening 224 formation process include: one of dry etch process and wet-etching technology or
Two kinds of combinations.
In the present embodiment, it is located at positioned at second opening 224 of the first area B for being subsequently formed the first contact hole
Second opening 224 of second area C is for the second contact hole as the second area C.
In other embodiments, second opening positioned at the firstth area is the first contact hole, the institute positioned at the secondth area
Stating the second opening is the second contact hole.
Due to having doping 211 in the source and drain doping area, so that the dielectric layer in removal source and drain doping area, is formed
Second opening 224 depth-to-width ratio it is smaller, specifically, it is described second opening 224 depth-to-width ratio be 3:1~8:1.Select described
The meaning of the depth-to-width ratio of two openings 224 is: if the depth-to-width ratio of second opening 224 is less than 3:1, so that doping 211
Thickness is blocked up, and the thickness of the doping 211 is blocked up, so that the resistance of doping 211 is larger, is unfavorable for improving semiconductor devices
Electric property；If the depth-to-width ratio of second opening 224 is greater than 8:1, so that the difficulty of the dielectric layer in removal source and drain doping area
It spends larger.
The technique for removing third photoresist 223, third bottom anti-reflection layer and third material layer 222 includes: cineration technics.
It is formed after second opening 224, further includes: the second dielectric layer on removal I gate structure 214 of the firstth area
217, the first contact hole is formed, the bottom-exposed of first contact hole goes out I gate structure 214 of the firstth area and the first source and drain
The top surface of doping 211 on doped region 204.The forming step of first contact hole is specifically shown in Figure 29 to Figure 30.
Figure 29 is please referred to, forms the 4th material layer in second opening, 224 (see Figure 28) and in second dielectric layer 217
225；The 4th bottom anti-reflection layer (not marking in figure) is formed in the 4th material layer 225；In the 4th bottom anti-reflective
The 4th photoresist 226 of formation on layer is penetrated, there is mask open (not marking in figure) in the 4th photoresist 226, the exposure mask
Opening is located in I gate structure 214 of the firstth area and the first source and drain doping area 204 and on II gate structure 214 of the secondth area.
Material, formation process and the work of the material of 4th material layer 225, formation process and effect and first material layer 209
With identical, this will not be repeated here.
The material of 4th bottom anti-reflection layer is identical as the material of the first bottom anti-reflection layer, and this will not be repeated here.
4th photoresist 226 is used to be subsequently formed mask layer when the first contact hole.
The mask open is used to define size and the position of the first contact hole and third contact hole.
Figure 30 is please referred to, with the 4th photoresist 226 for exposure mask, etches the 4th bottom anti-reflection layer, the 4th material layer
225, second dielectric layer 217 and mask layer form the first contact hole 227 until exposing the top surface of grid layer；Form institute
After stating the first contact hole 227, the 4th photoresist 226 of removal, the 4th bottom anti-reflection layer and the 4th material layer 225 expose
The side wall and bottom surface of second opening 224.
The formation process of first contact hole 227 includes: one of wet-etching technology and dry etch process.
First contact hole 227 is located in I gate structure 214 of the firstth area and the first source and drain doping area 204, and described first
Contact hole 227 is used for the first conductive plunger of subsequent receiving.
During forming the first contact hole 227, the second dielectric layer at II gate structure of the secondth area, 214 top
217 are also removed, and third contact hole 250 is formed in the dielectric layer 217 on II gate structure 214 of the secondth area, and the third connects
Contact hole 250 is used for subsequent receiving third conductive plunger.
Second opening 224 is used for the second conductive plunger of subsequent receiving.
Figure 31 is please referred to, is metallized to the doping 211 of first contact hole 227 and the second 224 bottoms of opening,
Form doped layer (not shown) and the metal silicide layer 228 on doped layer.
In the present embodiment, metalizeds are carried out to all dopings 211, it may be assumed that metal silicide layer 228 is
Electric connection layer 270.In other embodiments, metalized is carried out the part electric connection layer, the electric connection layer includes:
Doped layer and the metal silicide layer on doped layer.
In the present embodiment, metalized is carried out to all dopings 211, is conducive to the resistance for avoiding doped layer
Larger problem, and then be conducive to improve the electric property of semiconductor devices.
The forming step of the metal silicide layer 228 includes: in the second dielectric layer 217 and first contacts
Metal layer is formed in the opening of hole 227, second 224 and third contact hole 250；The metal layer is made annealing treatment；It is described to move back
After fire processing, the metal layer not reacted with source and drain doping area is removed, in first contact hole 227 and the second 224 bottoms of opening
Portion forms metal silicide layer 228.
The material of the metal layer includes: titanium or nickel.Correspondingly, the material of the metal silicide layer 228 includes: titanium
Silicon compound or nickel-silicon compound.
Positioned at 227 bottom of the first contact hole the metal silicide layer 228 for reducing the first source and drain doping area 204 with
The contact resistance between the first conductive plunger being subsequently formed.The metal silicide layer 228 positioned at the second 224 bottoms of opening
For reducing the contact resistance in the second source and drain doping area 205 and the second conductive plunger being subsequently formed.
In other embodiments, the material of the electric connection layer be metal, the forming step of the electric connection layer include:
In the substrate and source and drain doping area and the side wall of pseudo- grid structure and top surface form initial electrical connection film；Remove part
Initial electrical connection film, forms electrical connection film, and the top surface of the electrical connection film is lower than the top surface of pseudo- grid structure；Removal is hung down
Directly in the electrical connection film on the fin extending direction between source and drain doping area in substrate, the electric connection layer is formed.
Figure 32 is please referred to, is formed after the electric connection layer 270, it is conductive slotting to form first in first contact hole 227
Plug 229；The second conductive plunger 230 is formed in second opening 224；The is formed in the third contact hole 250 (see Figure 30)
Three plugs 231.
In the present embodiment, first conductive plunger 229, the second conductive plunger 230 and third conductive plunger 231 are same
When formed.In other embodiments, first conductive plunger, the second conductive plunger and third conductive plunger are not formed simultaneously.
In the present embodiment, the shape of first conductive plunger 229, the second conductive plunger 230 and third conductive plunger 231
At step include: first contact hole 227, second opening 224 and third contact hole 250 in and second dielectric layer 217
Upper formation plug material layer；The plug material layer is planarized, until the top surface of second dielectric layer 217 is exposed, in institute
It states in the first contact hole 227 and forms the first conductive plunger 229, form the second conductive plunger 230 in second opening 224,
Third conductive plunger 231 is formed in third contact hole 250.
The material of the plug material layer is metal, such as: tungsten.
The technique for planarizing the plug material layer includes: chemical mechanical milling tech.
Correspondingly, the embodiment of the present invention also provides one kind is formed by semiconductor structure in aforementioned manners, Figure 31 is please referred to,
Include:
Substrate 200, substrate described in the substrate 200 includes area of grid I；
Gate structure 214 in I substrate 200 of area of grid, tool in the substrate 200 between the gate structure 214
There is source and drain doped region；
Electric connection layer 270 in source and drain doping area；
Dielectric layer in substrate 200 and electric connection layer 270, the dielectric layer is interior to have contact hole, the contact hole
Bottom-exposed goes out the top surface of electric connection layer 270.
The thickness of the electric connection layer 270 are as follows: 20 nanometers~50 nanometers.
The thickness of the electric connection layer 270 and the height ratio of gate structure 214 are as follows: 1:3~1:2.
The depth-to-width ratio of second opening are as follows: 3:1~8:1.
When the material of the electric connection layer 270 is metal, the material of the electric connection layer 270 includes: tungsten, aluminium or copper.
The electric connection layer 270 includes doped layer and the metal silicide layer 228 on doped layer；The doped layer
Material be semiconductor material；The material of the doped layer includes silicon, has Doped ions in the doped layer；The metallic silicon
The material of compound layer 228 includes: titanium-silicon compound or nickel-silicon compound.
The semiconductor structure further include: the plug in contact hole.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, the substrate includes area of grid, has source and drain doping area in the substrate between the area of grid；
Electric connection layer is formed in the source and drain doping area；
It forms gate structure on the substrate and dielectric layer, the gate structure is located in area of grid substrate, the medium
Part of grid pole structure layer covering electric connection layer and be exposed；
The dielectric layer in the source and drain doping area is removed, until exposing electric connection layer, forms contact hole, the side of the contact hole
Wall exposes gate structure.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of the electric connection layer are as follows:
20 nanometers~50 nanometers.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness and grid of the electric connection layer
The height ratio of pole structure are as follows: 1:3~1:2.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the depth-to-width ratio of the contact hole are as follows:
3:1~8:1.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the dielectric layer includes first medium
Layer and the second dielectric layer on first medium layer；The first medium layer, second dielectric layer, gate structure and source and drain are mixed
The forming step in miscellaneous area includes: that pseudo- grid structure is formed in the area of grid substrate；Substrate in dummy gate structure two sides
It is interior to form the source and drain doping area；The first medium floor, the first medium are formed in the substrate and source and drain doping area
Layer covers the side wall of pseudo- grid structure, and exposes the top surface of pseudo- grid structure；Dummy gate structure is removed, is situated between described first
Pseudo- grid opening is formed in matter layer；Gate structure is formed in the pseudo- grid opening；On the first medium layer and gate structure
Form second dielectric layer.
6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that formed the first medium layer it
Before, form the electric connection layer；The substrate includes fin, and the gate structure is across the fin.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the material of the electric connection layer is gold
When category, the forming step of the electric connection layer include: in the substrate and source and drain doping area and the side wall of pseudo- grid structure and
Top surface forms initial electrical connection film；The initial electrical connection film in removal part forms electrical connection film, the top of the electrical connection film
Surface is lower than the top surface of pseudo- grid structure；Removal is perpendicular between source and drain doping area on the fin extending direction in substrate
It is electrically connected film, forms the electric connection layer；The metal includes: tungsten, aluminium or copper.
8. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that when the electric connection layer includes doping
When layer and metal silicide layer on doped layer, the forming step of the electric connection layer includes: in the substrate and source
It leaks on doped region and the side wall of pseudo- grid structure and top surface forms initial dopant material layer；Remove part initial dopant material
The bed of material, forms initial dopant film, and the top surface of the initial dopant film is lower than the top surface of pseudo- grid structure；Along perpendicular to institute
It states on fin extending direction, removes the initial dopant film between source and drain doping area, form the doping；The doping described part
Film carries out metalized, forms the doped layer and the metal silicide layer on doped layer.
9. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the material of the doped layer is partly to lead
Body material；The material of the doped layer includes silicon, has Doped ions in the doped layer.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the concentration of the Doped ions are as follows:
1.0e14atm/cm2~1e20atm/cm2。
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the gate structure includes: that grid are situated between
Matter layer and the grid layer on gate dielectric layer；The forming step of the contact hole further include: the medium on removal gate structure
Layer, until exposing grid layer.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that formed after contact hole, the shape
At method further include: form plug on the electric connection layer in the contact hole.
13. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include area of grid；
Gate structure in area of grid substrate has source and drain doping area in the substrate between the gate structure；
Electric connection layer in the source and drain doping area；
Dielectric layer in substrate and electric connection layer, the dielectric layer is interior to have contact hole, and the contact hole bottom-exposed goes out
The top surface of electric connection layer, and the side wall of the contact hole exposes gate structure.
14. semiconductor structure as claimed in claim 13, which is characterized in that the thickness of the electric connection layer are as follows: 20 nanometers~
50 nanometers.
15. semiconductor structure as claimed in claim 13, which is characterized in that the thickness of the electric connection layer and gate structure
Height ratio are as follows: 1:3~1:2.
16. semiconductor structure as claimed in claim 13, which is characterized in that the depth-to-width ratio of the contact hole are as follows: 3:1~8:1.
17. semiconductor structure as claimed in claim 13, which is characterized in that when the material of the electric connection layer is metal, institute
The material for stating electric connection layer includes: tungsten, aluminium or copper.
18. semiconductor structure as claimed in claim 13, which is characterized in that the electric connection layer includes doped layer and is located at
Metal silicide layer on doped layer；The material of the doped layer is semiconductor material；The material of the doped layer includes silicon, institute
Stating has Doped ions in doped layer；The material of the metal silicide layer includes: titanium-silicon compound or nickel-silicon compound layer.
19. semiconductor structure as claimed in claim 18, which is characterized in that the concentration of the Doped ions are as follows:
1.0e14atm/cm2~1e20atm/cm2。
20. semiconductor structure as claimed in claim 13, which is characterized in that the semiconductor structure further include: be located at contact
Plug in hole.
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| CN113555436A (en) * | 2020-04-26 | 2021-10-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN114068395A (en) * | 2020-07-31 | 2022-02-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN114068395A (en) * | 2020-07-31 | 2022-02-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN114068395B (en) * | 2020-07-31 | 2024-03-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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