CN114068394A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114068394A
CN114068394A CN202010760778.8A CN202010760778A CN114068394A CN 114068394 A CN114068394 A CN 114068394A CN 202010760778 A CN202010760778 A CN 202010760778A CN 114068394 A CN114068394 A CN 114068394A
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layer
source
drain
gate
forming
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CN114068394B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate comprising a shared contact region, wherein a grid structure is arranged on the substrate, a grid cap layer is arranged at the top of the grid structure, source drain doped regions are arranged at two sides of the grid structure, and a stacked source drain interconnection layer and a stacked source drain cap layer are arranged at the top of the source drain doped region; etching the source drain cap layer or the grid cap layer of the shared contact region to form a first groove penetrating through the source drain cap layer or the grid cap layer; forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer; forming a top dielectric layer covering the sacrificial layer, the grid electrode cap layer and the source drain cap layer; etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure or the top dielectric layer, the sacrificial layer and the source drain cap layer in the shared contact area to form a second groove communicated with the first groove; a shared contact plug is formed in the first trench and the second trench. The invention improves the performance of the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming higher, which makes the wafer surface unable to provide enough area to make the required interconnection lines.
In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize connection between the contact hole plugs, thereby forming a circuit.
The contact hole plug in the transistor structure comprises a grid contact hole plug positioned on the surface of the grid structure and used for realizing the connection between the grid structure and an external circuit, a source drain contact hole plug positioned on the surface of a source drain doped region and used for realizing the connection between the source drain doped region and the external circuit, and a shared contact plug (share contact) used for electrically connecting the grid and the source drain doped region.
Currently, in order to further reduce the area of the transistor, a Contact Over Active Gate (COAG) process is introduced. Compared with the conventional gate contact hole plug located above the gate structure of the isolation region, the COAG process can make the gate contact hole plug above the gate structure of the Active Area (AA), thereby further saving the Area of the chip.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which improves the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure extending along a first direction is formed on the substrate, a gate cap layer is formed at the top of the gate structure, source and drain doped regions located in the substrate are formed at two sides of the gate structure, a source and drain interconnection layer is formed at the top of the source and drain doped region, and a source and drain cap layer is formed at the top of the source and drain interconnection layer, wherein a region for forming a shared contact plug electrically connected with the gate structure and the source and drain doped region on the substrate is used as a shared contact region; etching the source-drain cap layer or the gate cap layer in the shared contact region to form a first groove penetrating through the source-drain cap layer or the gate cap layer; forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer; forming a top dielectric layer covering the sacrificial layer, the grid electrode cap layer and the source drain cap layer; etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure in the shared contact region, or etching the top dielectric layer, the sacrificial layer and the source drain cap layer on the top of the gate structure, and forming a second groove communicated with the first groove in the top dielectric layer and the gate cap layer; and forming a shared contact plug in the first groove and the second groove, wherein the shared contact plug is electrically connected with the grid structure and the source-drain doped region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, in the shared contact region, the source-drain cap layer or the gate cap layer is etched to form a first groove penetrating the source-drain cap layer or the gate cap layer, and a sacrificial layer is formed in the first groove and used for occupying the space of the first groove, the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer, then, in the shared contact region, the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure are etched, or the top dielectric layer, the sacrificial layer and the source-drain cap layer on the top of the gate structure are etched, a second groove communicated with the first groove is formed in the top dielectric layer, and the gate cap layer and the source-drain cap layer are usually materials with etching selectivity, so that by pre-etching the source-drain cap layer or the gate cap layer in the shared contact region, the first trench is formed, correspondingly, when the second trench is formed subsequently, only the gate cap layer or the source drain cap layer which is not etched in the shared contact region needs to be etched, namely, one of the gate cap layer and the source drain cap layer is etched before the top dielectric layer is formed, so that the gate cap layer and the source drain cap layer are respectively etched in different processes, the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer, the sacrificial layer is easy to etch in the process of forming the second trench subsequently, therefore, the influence of transverse etching on the top dielectric layer is favorably reduced in the process of forming the second trench, the section shape and the opening size of the second trench are ensured, the probability that the second trench exposes out of adjacent gate structures or source drain interconnection layers in other regions except the shared contact region is correspondingly reduced, and the probability that the shared contact plug is short-circuited with adjacent other gate structures or source drain interconnection layers is reduced, thereby improving the performance of the semiconductor structure.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to respective steps in an embodiment of a method for forming a semiconductor structure;
fig. 5 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
After an Active Gate Contact (COAG) process is introduced at present, the forming difficulty of the shared Contact plug is high, and the process risk is high. The reason why the formation difficulty of the shared contact plug is higher and the process risk is higher is analyzed by combining a semiconductor structure.
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, a gate structure 20 is formed on the substrate 10, a gate capping layer 21 is formed at the top of the gate structure 20, active drain doping regions 30 are formed in the substrate 10 at two sides of the gate structure 20, a bottom dielectric layer (not shown) is formed on the substrate 10 at the side of the gate structure 20, the bottom dielectric layer covers the sidewalls of the gate structure 20 and the gate capping layer 21, and an active drain interconnection layer 31 and a source drain capping layer 32 located at the top of the source drain interconnection layer 31 are formed in the bottom dielectric layer at the top of the source drain doping region 30.
A region on the substrate 10 for forming a shared contact plug (share contact) electrically connecting the gate structure 20 and the source-drain doped region 30 is used as a shared contact region (not shown).
With continued reference to fig. 1, a top dielectric layer 40 is formed overlying the gate capping layer 21 and the source drain capping layer 32.
And forming a Gate plug penetrating through the top dielectric layer 40 and the Gate cap layer 21 on the top of the Gate structure 20, wherein the Gate plug is formed on the Active region and is an Active Gate Contact (COAG) plug. And, source and drain plugs penetrating through the top dielectric layer 30 and the source and drain capping layer 32 are formed on top of the source and drain interconnection layer 31 subsequently.
In the COAG process, in order to reduce the probability of bridging between the source-drain plug and the gate structure 20 and bridging between the gate plug and the source-drain interconnection layer 31, a higher etching selection ratio is provided between the gate cap layer 21 and the source-drain cap layer 32, so that the source-drain cap layer 32 can protect the source-drain interconnection layer 31 in the process of forming the gate plug, and the gate cap layer 21 can protect the gate structure 20 in the process of forming the source-drain plug.
With combined reference to fig. 2 to 4, a shared contact plug 60 (as shown in fig. 4) is formed in the shared contact region, and penetrates through the top dielectric layer 40, the gate capping layer 21 and the source drain capping layer 32, and the shared contact plug 60 is in contact with the gate structure 20 and the source drain interconnection layer 31.
Specifically, the step of forming the shared contact plug 50 includes: as shown in fig. 2, etching the top dielectric layer 40 of the shared contact region to form an opening 41 exposing the gate capping layer 21 and the source drain capping layer 32; as shown in fig. 3, etching the gate cap layer 21 and the source-drain cap layer 32 at the bottom of the opening 41 to form a shared contact hole 50 penetrating through the top dielectric layer 40, the gate cap layer 21 and the source-drain cap layer 32, wherein the shared contact hole 50 exposes the gate structure 20 and the source-drain interconnection layer 31; as shown in fig. 4, a shared contact plug 60 is formed in the shared contact hole 50.
Because the gate capping layer 21 and the source-drain capping layer 32 have a higher etching selection ratio, after the top dielectric layer 40 is etched, different etching processes are required to be used for etching the gate capping layer 21 and the source-drain capping layer 32 respectively, and in the process of etching the gate capping layer 21 and the source-drain capping layer 32, the opening 41 in the top dielectric layer 40 is easily affected by transverse etching, so that adverse effects are caused on the profile morphology of the opening 41, and even the problem that the size of the opening 41 is increased occurs, further, false etching is easily caused to other adjacent gate capping layers 21 or source-drain capping layers 32, and accordingly, the probability that the shared contact plug 60 is short-circuited with other adjacent gate structures 20 or source-drain interconnection layers 31 is increased.
Therefore, the formation of the common contact plug 60 is difficult and the performance of the semiconductor structure is easily degraded.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure extending along a first direction is formed on the substrate, a gate cap layer is formed at the top of the gate structure, source and drain doped regions located in the substrate are formed at two sides of the gate structure, a source and drain interconnection layer is formed at the top of the source and drain doped region, and a source and drain cap layer is formed at the top of the source and drain interconnection layer, wherein a region for forming a shared contact plug electrically connected with the gate structure and the source and drain doped region on the substrate is used as a shared contact region; etching the source-drain cap layer or the gate cap layer in the shared contact region to form a first groove penetrating through the source-drain cap layer or the gate cap layer; forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer; forming a top dielectric layer covering the sacrificial layer, the grid electrode cap layer and the source drain cap layer; etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure in the shared contact region, or etching the top dielectric layer, the sacrificial layer and the source drain cap layer on the top of the gate structure, and forming a second groove communicated with the first groove in the top dielectric layer and the gate cap layer; and forming a shared contact plug in the first groove and the second groove, wherein the shared contact plug is electrically connected with the grid structure and the source-drain doped region.
In the forming method provided by the embodiment of the invention, in the shared contact region, the source-drain cap layer or the gate cap layer is etched to form a first groove penetrating the source-drain cap layer or the gate cap layer, and a sacrificial layer is formed in the first groove and used for occupying the space of the first groove, the etching resistance of the sacrificial layer is smaller than that of the source-drain cap layer, then, in the shared contact region, the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure are etched, or the top dielectric layer, the sacrificial layer and the source-drain cap layer on the top of the gate structure are etched, a second groove communicated with the first groove is formed in the top dielectric layer, and the gate cap layer and the source-drain cap layer are usually materials with etching selectivity, so that by pre-etching the source-drain cap layer or the gate cap layer in the shared contact region, the first trench is formed, correspondingly, when the second trench is formed subsequently, only the gate cap layer or the source drain cap layer which is not etched in the shared contact region needs to be etched, namely, one of the gate cap layer and the source drain cap layer is etched before the top dielectric layer is formed, so that the gate cap layer and the source drain cap layer are respectively etched in different processes, the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer, the sacrificial layer is easy to etch in the process of forming the second trench subsequently, therefore, the influence of transverse etching on the top dielectric layer is favorably reduced in the process of forming the second trench, the section shape and the opening size of the second trench are ensured, the probability that the second trench exposes out of adjacent gate structures or source drain interconnection layers in other regions except the shared contact region is correspondingly reduced, and the probability that the shared contact plug is short-circuited with adjacent other gate structures or source drain interconnection layers is reduced, thereby improving the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 5 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
With reference to fig. 5 to 7, fig. 5 is a top view, fig. 6 is a cross-sectional view of fig. 5 along a cut line A1a2, fig. 7 is a cross-sectional view of fig. 5 along a cut line B1B2, a substrate (not labeled) is provided, a gate structure 200 extending along a first direction (as shown in a Y direction in fig. 5) is formed on the substrate, a gate capping layer 240 is formed on the top of the gate structure 200, source and drain doped regions 210 located in the substrate are formed on two sides of the gate structure 200, an active and drain interconnection layer 220 is formed on the top of the source and drain doped regions 210, an active and drain capping layer 230 is formed on the top of the source and drain interconnection layer 220, wherein a region on the substrate for forming a shared contact plug electrically connecting the gate structure 200 and the source and drain doped regions 210 serves as a shared contact region 100S.
For ease of illustration, fig. 5 only illustrates fin 110, gate cap 240, and source drain cap 230.
The substrate is used for providing a process platform for subsequent process procedures.
In the present embodiment, the base is used to form a fin field effect transistor (FinFET), and therefore, the base includes a substrate 100 and a fin 110 protruding from the substrate 100. In other embodiments, when the base is used to form a planar field effect transistor, the base is correspondingly a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate.
In other embodiments, the substrate may also be a substrate of other material types. For example, the material of the substrate may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
In this embodiment, the material of the fin 110 is the same as the material of the substrate 100.
In this embodiment, a region on the substrate for forming a shared contact plug electrically connected to the gate structure 200 and the source-drain doped region 210 is used as the shared contact region 100S.
Specifically, the direction parallel to the substrate surface and perpendicular to the first direction is a second direction (as shown by the X direction in fig. 5), and the shared contact region 100S extends along the second direction.
As an example, the substrate is used to form an SRAM (Static Random Access Memory) device. According to the design requirement of the SRAM device, a part of the gate structure 200 and the source-drain doped region 210 need to be electrically connected through a shared contact plug.
In this embodiment, the method for forming the semiconductor structure further includes: after the fin portion 110 is formed, an isolation layer 101 is formed on the substrate 100 exposed by the fin portion 110, and the isolation layer 101 covers a portion of the sidewall of the fin portion 110.
The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 101 is made of silicon nitride.
The gate structure 200 is used to control the conduction channel to be turned on or off during device operation.
In this embodiment, the gate structure 200 is located on the isolation layer 101, and the gate structure 200 crosses over the fin 110 and covers a portion of the top surface and a portion of the sidewall of the fin 110.
In this embodiment, the gate structure 110 is a metal gate structure, and the gate structure 200 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.
The high-k gate dielectric layer is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In particular, the material of the high-k gate dielectric layer may be selected from HfO2、ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TiAl, Mo, MoN, AlN and TiAl C.
The gate electrode layer is used to electrically lead out the gate structure 200. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W.
In this embodiment, the source-drain doped regions 210 are located in the fin portions 110 on two sides of the gate structure 200.
Specifically, adjacent gate structures 200 share a source drain doped region 210.
In this embodiment, the source/drain doped region 210 is formed in the substrate of the shared contact region 100S.
When an NMOS transistor is formed, the source/drain doped region 210 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, thereby facilitating improvement of carrier mobility of the NMOS transistor, where the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the source/drain doped region 210 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.
In this embodiment, a sidewall 205 is further formed on the sidewall of the gate structure 200.
The sidewall spacers 205 are used to define a formation region of the source-drain doped region 210, and the sidewall spacers 205 are also used to protect sidewalls of the gate structure 200. The sidewall 205 may be a single-layer structure or a stacked structure, and the material of the sidewall 205 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the sidewall spacers 205 have a single-layer structure, and the material of the sidewall spacers 205 is silicon nitride.
It should be further noted that a bottom dielectric layer (not shown) is further formed on the substrate at the side of the gate structure 200, and the top of the bottom dielectric layer is flush with the tops of the gate capping layer 240 and the source drain capping layer 230.
The bottom dielectric layer is used to isolate adjacent devices and also to achieve electrical isolation between the source-drain interconnect layers 220. In this embodiment, the bottom Dielectric Layer is an Inter Layer Dielectric (ILD).
The bottom dielectric layer is made of an insulating material and comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the bottom dielectric layer is made of silicon nitride.
The source-drain interconnection layer 220 is in contact with the source-drain doped region 210, and is used for electrically connecting the source-drain doped region 210 with an external circuit or other interconnection structures.
In this embodiment, a source-drain plug and a shared contact plug which are in contact with the source-drain interconnection layer 220 are formed on the source-drain interconnection layer 220 in the following step, and the source-drain plug and the shared contact plug are electrically connected with the source-drain doped region 210 through the source-drain interconnection layer 220.
In this embodiment, the source-drain interconnection layer 220 is made of copper. The resistivity of copper is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the source-drain interconnection layer 220, and correspondingly reducing the power consumption. In other embodiments, the source-drain interconnection layer may also be made of a conductive material such as tungsten or cobalt.
After a top dielectric layer is formed on a bottom dielectric layer, a gate plug in contact with the gate structure 200 is formed on the top of the gate structure 200 in an Active Area (AA), and the source-drain cap layer 230 is located on the top surface of the source-drain interconnection layer 220, so that the source-drain interconnection layer 220 is protected in the process of forming the gate plug, and the probability that the source-drain interconnection layer 220 is damaged and the gate plug and the source-drain interconnection layer 220 are short-circuited is favorably reduced.
The source-drain capping layer 230 is made of a material having a high etching selectivity with the gate capping layer 240, the sidewall 205, the bottom dielectric layer and the subsequently formed top dielectric layer, so that the source-drain capping layer 230 can be protected from the source-drain interconnection layer 220.
In this embodiment, the material of the source-drain cap layer 230 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Specifically, the source drain capping layer 230 and the sidewall spacer 205 are made of different materials.
As an example, the material of the source drain capping layer 230 is silicon carbide.
And after a top dielectric layer is formed on the bottom dielectric layer, a source-drain plug in contact with the source-drain interconnection layer 220 is formed on the top of the source-drain interconnection layer 220, and the gate cap layer 240 is located on the top surface of the gate structure 200, and is used for protecting the gate structure 200, so that the probability that the gate structure 200 is damaged and the source-drain plug and the gate structure 200 are short-circuited is favorably reduced.
The gate capping layer 240 is made of a material having etching selectivity with the source-drain capping layer 230, the bottom dielectric layer, and the subsequently formed top dielectric layer, so as to be beneficial to ensuring that the source-drain capping layer 230 can protect the gate structure 200.
In this embodiment, the material of the gate capping layer 240 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Specifically, the gate capping layer 240 and the source drain capping layer 230 are made of different materials.
As an example, the material of the gate capping layer 240 is silicon nitride.
The gate cap layer 240 and the sidewall 205 are made of the same material, so that when the shared contact hole is formed subsequently, the sidewall 205 can be etched while the gate cap layer 240 is etched, thereby reducing the complexity of the etching process. Moreover, the forming process of the semiconductor structure adopts less film materials, which is beneficial to reducing the process complexity.
In other embodiments, the gate capping layer and the sidewall spacers may also be made of different materials.
As an example, the gate structure 200 is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate last), so that the sidewall spacers 205 cover sidewalls of the gate structure 200 and the gate capping layer 240.
Specifically, after the gate structure 200 is formed in the bottom dielectric layer, the gate structure 200 with a part of thickness is etched back; after etching back the gate structure 200 with a part of the thickness, a gate cap layer 240 is formed in the region surrounded by the bottom dielectric layer and the remaining gate structure 200.
The step of forming the gate capping layer 240 includes the steps of sequentially depositing a gate capping material layer and planarizing the gate capping material layer (e.g., a chemical mechanical polishing process).
In this embodiment, after the gate capping layer 240 is formed, the source-drain interconnection layer 220 and the source-drain capping layer 230 are formed.
Specifically, the step of forming the source-drain interconnection layer 220 includes: etching the bottom dielectric layer above the source-drain doped region 210 to form an opening exposing the source-drain doped region 210; forming an initial source-drain interconnection layer (not shown) in the opening, wherein the top surface of the initial source-drain interconnection layer is flush with the top surface of the gate capping layer 240; the initial source drain interconnect layer of a portion of the thickness is etched back to form source drain interconnect layer 220.
Correspondingly, a source-drain capping material layer is filled in a region surrounded by the source-drain interconnection layer 220 and the side wall 205, the top surface of the gate capping layer 240 is used as a stop position, the source-drain capping material layer is subjected to planarization processing, and the rest of the source-drain capping material layer after the planarization processing is used as the source-drain capping layer 230.
With combined reference to fig. 8 to 10, fig. 8 is a top view, fig. 9 is a cross-sectional view taken along a line A1a2 in fig. 8, fig. 10 is a cross-sectional view taken along a line B1B2 in fig. 8, and in the shared contact region 100S, the source/drain capping layer 230 or the gate capping layer 240 is etched to form a first trench 310 penetrating through the source/drain capping layer 230 or the gate capping layer 240.
The first trench 310 is used to provide a spatial location for a subsequent formation of a sacrificial layer.
After a top dielectric layer is formed on a bottom dielectric layer, a shared contact plug is formed in the shared contact region 100S, and the shared contact plug is electrically connected with the gate structure 200 and the source-drain doped region 210, so that, in order to form the shared contact plug, after the top dielectric layer is etched, not only the source-drain cap layer 230 of the shared contact region 100S but also the gate cap layer 240 of the shared contact region 100S need to be etched, so that a shared contact trench penetrating through the source-drain cap layer 230 and the gate cap layer 240 of the shared contact region 100S is formed, wherein a high etching selection ratio is provided between the source-drain cap layer 230 and the gate cap layer 240, and therefore, the difficulty of an etching process in forming the shared contact trench is high.
Therefore, in this embodiment, before forming the top dielectric layer, the source/drain cap layer 230 or the gate cap layer 240 is etched first, so that the drain cap layer 230 and the gate cap layer 240 are etched in different processes, and accordingly, after the top dielectric layer is subsequently etched, only one of the drain cap layer 230 and the gate cap layer 240 needs to be etched, thereby reducing the influence of the lateral etching on the subsequent top dielectric layer.
In this embodiment, the first trench 310 is formed by etching the source/drain capping layer 230.
Specifically, the step of forming the first trench 310 includes: in the shared contact region 100S, the source-drain cap layer 230 and the source-drain interconnection layer 220 are sequentially etched to form a first trench 310 penetrating through the source-drain cap layer 230 and the source-drain interconnection layer 220.
Wherein the step of forming the first trench 310 further comprises: before etching, the first mask layer of the gate capping layer 240, the sidewall spacer 205, the source/drain capping layer 230 and the bottom dielectric layer has a first mask opening exposing the source/drain capping layer 230 of the shared contact region 100S.
Correspondingly, the first mask layer is used as a mask, and etching is carried out along the first mask opening, so that a first groove 310 is formed; after the first trench 310 is formed, the method further includes: and removing the first mask layer.
As an example, the material of the first mask layer is photoresist.
It should be noted that the source/drain capping layer 230 is made of a material having an etching selectivity with the gate capping layer 240, the sidewall spacer 205 and the bottom dielectric layer, so that the probability of damage to the gate capping layer 240, the sidewall spacer 205 and the bottom dielectric layer is low in the process of forming the first trench 310, which correspondingly increases a process window for forming the first mask opening.
For example, along the second direction, the first mask opening may further expose the sidewall spacers 205 on two sides of the source/drain capping layer 230 or the gate capping layer 240 of the shared contact region 100S.
In the forming process of the semiconductor structure, according to design requirements, the step of performing cutting processing on the source-drain interconnection layer 220 along the first direction is included, so that the first trench 310 is formed by etching the source-drain cap layer 230 and the source-drain interconnection layer 220, and thus the same photomask (mask) can be used for cutting processing on the source-drain interconnection layer 220 and forming the first trench 310, and further the process cost is favorably reduced.
Specifically, the source/drain doped region 210 is formed in the substrate of the shared contact region 100S, and therefore, the source/drain doped region 210 is exposed by the first trench 310.
In other embodiments, according to process requirements, only the source-drain cap layer may be etched to form a first trench exposing the source-drain interconnection layer.
In this embodiment, an anisotropic dry etching process is used to perform etching, so as to form the first trench 310.
The dry etching process has higher process controllability, and the etching selection ratio among different film layers is easy to adjust. In addition, in the dry etching process, the source-drain cap layer 230 and the source-drain interconnection layer 220 can be etched in the same etching device in sequence by adjusting the etching gas and the etching parameters, and the process is simple and does not need to convert a machine. In addition, the anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate of the etching process is greater than the transverse etching rate thereof, so that the opening size of the first trench 310 along the first direction can be accurately controlled, the sidewall morphology quality of the first trench 310 can be improved, and the probability of damage to the sidewall 205 can be reduced.
Along the first direction, the opening size of the first trench 310 should not be too small, and should not be too large. If the opening size of the first trench 310 is too small, this not only increases the difficulty of the etching process for forming the first trench 310, but also easily causes the aspect ratio of the first trench 310 to be too large, thereby increasing the difficulty of forming the sacrificial layer in the first trench 310. For this reason, in the present embodiment, the opening size of the first trench 310 is 16 nm to 30 nm along the first direction. For example, the opening size of the first trench 310 along the first direction is 20 nm or 25 nm.
As an example, in the shared contact region 100S, two source/drain doped regions 210 are formed on one side of the gate structure 200, and the first trench 310 exposes the top and the sidewall of one source/drain doped region 210 and exposes the sidewall of the other source/drain doped region 210. In other embodiments, when the opening size of the first trench along the first direction is larger, the first trench exposes the tops of the two source/drain doped regions.
Referring to fig. 11 to 13 in combination, fig. 11 is a top view, fig. 12 is a cross-sectional view taken along line A1a2 in fig. 11, and fig. 13 is a cross-sectional view taken along line B1B2 in fig. 11, wherein a sacrificial layer 320 is formed in the first trench 310, and the etching resistance of the sacrificial layer 320 is less than that of the source-drain capping layer 230.
The sacrificial layer 320 occupies the space of the first trench 310, thereby providing a process foundation for subsequent processes.
Specifically, a top dielectric layer covering the sacrificial layer 320, the gate capping layer 240 and the source drain capping layer 230 is formed subsequently, and the top dielectric layer, the gate capping layer 240 and the sacrificial layer 320 on the top of the gate structure 200 are etched in the shared contact region 100S, or the top dielectric layer, the sacrificial layer 320 and the source drain capping layer 230 on the top of the gate structure 200 are etched, and a second trench communicated with the first trench 310 is formed in the top dielectric layer. In this embodiment, before forming the top dielectric layer, one of the gate capping layer 240 and the source drain capping layer 230 is etched, therefore, the gate cap layer 240 and the source/drain cap layer 230 are etched in different processes, and the etching resistance of the sacrificial layer 320 is less than that of the source/drain cap layer 230, the sacrificial layer 320 is easily etched in the subsequent process of forming the second trench, so that the influence of the lateral etching on the top dielectric layer is favorably reduced in the process of forming the second trench, so that the cross-sectional shape and the opening size of the second trench are ensured, the probability that the second trench exposes the adjacent gate structure 200 or the source-drain interconnection layer 220 in the other region except the shared contact region 100S is correspondingly reduced, therefore, the probability of short circuit between the shared contact plug and other adjacent gate structures 200 or source-drain interconnection layers 220 is reduced, and the performance of the semiconductor structure is improved.
Correspondingly, the sacrificial layer 320 is made of a material having a higher etching selectivity with the gate cap layer 240 and the source drain cap layer 230, so that damage to the gate cap layer 240 or the source drain cap layer 230 in other regions is reduced when the sacrificial layer 320 is etched subsequently.
In addition, in this embodiment, the material of the sacrificial layer 320 is selected as follows: and when the top dielectric layer is etched subsequently, the etching selection ratio between the top dielectric layer and the sacrificial layer 320 is less than 3: 1. The etch rates of the top dielectric layer and the sacrificial layer 320 are close to each other, thereby further facilitating the etching of the sacrificial layer 320. For example, during the etching of the top dielectric layer, the sacrificial layer 320 is etched.
Specifically, the materials of the sacrificial layer 320, the gate capping layer 240 and the source drain capping layer 230 are different from each other.
In this embodiment, the material of the sacrificial layer 320 is a dielectric material. By selecting the dielectric material, when the second trench is formed subsequently, it is convenient to retain the sacrificial layer 320 with a partial width according to the process requirement, which is correspondingly beneficial to improve the process window when the second trench is formed.
Specifically, the dielectric material includes one or more of silicon oxide, aluminum oxide, and titanium dioxide. As an example, the dielectric material is silicon oxide. The cost of silicon oxide is low and the process compatibility is high.
Specifically, the step of forming the sacrificial layer 320 includes: filling a sacrificial material layer (not shown) in the first trench 310; and with the top of the gate capping layer 240 or the source-drain capping layer 230 as a stop position, performing planarization processing on the sacrificial material layer, and reserving the remaining sacrificial material layer in the first trench 310 as a sacrificial layer 320.
In this embodiment, a chemical vapor deposition process may be used to fill the first trench 310 with a sacrificial material layer, and a chemical mechanical polishing process is used to planarize the sacrificial material layer.
The hardness and density of the gate cap layer 240 and the source drain cap layer 230 are high, so that the gate cap layer 240 and the source drain cap layer 230 can both better define the stop position of the planarization process.
Referring to fig. 14 and 15 in combination, fig. 14 is a cross-sectional view based on fig. 12, and fig. 15 is a cross-sectional view based on fig. 13, and a top dielectric layer 103 covering the sacrificial layer 320, the gate capping layer 240 and the source drain capping layer 230 is formed.
The top dielectric layer 103 is used for realizing electrical isolation between the subsequent gate plug, the source drain plug and the shared contact plug together with the bottom dielectric layer.
The top dielectric layer 103 is made of a dielectric material, and the top dielectric layer 103 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, a deposition process (e.g., a chemical vapor deposition process) is used to form the material of the top dielectric layer 103.
The first trench 310 is filled with a sacrificial layer 320, so that the top surface of the top dielectric layer 103 has a high flatness.
Referring to fig. 16 and 17 in combination, fig. 16 is a cross-sectional view based on fig. 14, fig. 17 is a cross-sectional view based on fig. 15, the top dielectric layer 103, the gate capping layer 240 and the sacrificial layer 320 on top of the gate structure 200 are etched in the shared contact region 100S, and a second trench 330 communicating with the first trench 310 is formed in the top dielectric layer 103 and the gate capping layer 240.
The second trench 330 and the first trench 310 form a shared contact trench (not labeled) to provide a spatial location for the subsequent formation of a shared contact plug.
Specifically, the step of forming the second trench 330 further includes: before etching, a second mask layer is formed on the top dielectric layer 103, where the second mask layer has a second mask opening (not shown), and the second mask opening exposes the top dielectric layer 103 of the shared contact region 100S.
Correspondingly, the second mask layer is used as a mask, and etching is performed along the second mask opening, so that a second groove 330 is formed; after the second trench 330 is formed, the method further includes: and removing the second mask layer.
In the process of forming the second trench 330, the sidewall spacers 205 in the shared contact region 100S are also etched. By etching the sidewall spacers 205, the remaining sidewall spacers 205 in the shared contact region 100S are flush with the top of the gate structure 200, so that the material of the shared contact plug is easily filled into the second trench 330 and the first trench 310.
As an example, the material of the second mask layer is photoresist.
It should be noted that the gate capping layer 240 is made of a material having an etching selectivity with respect to the source-drain capping layer 230, the bottom dielectric layer, and the top dielectric layer 103, so that the probability of damage to the source-drain capping layer 230, the bottom dielectric layer, and the top dielectric layer 103 is low during the process of forming the second trench 330, which correspondingly increases a process window for forming the second mask opening.
For example, along the second direction, the second trench 330 may also expose a portion of the top of the source drain capping layer 230 adjacent to the shared contact region 100S.
In this embodiment, the etching resistance of the sacrificial layer 320 is less than the etching resistance of the source/drain cap layer 230, and after etching the top dielectric layer, the gate cap layer and the source/drain cap layer are etched respectively, compared with the scheme of forming the shared contact groove penetrating through the top dielectric layer, the grid electrode cap layer and the source drain cap layer, the sacrificial layer 320 is easily etched during the formation of the second trench 330, which is beneficial to reduce the influence of the lateral etching on the top dielectric layer 103, so that the cross-sectional shape and the opening size of the second trench 330 are ensured, and accordingly the probability that the second trench 330 exposes the adjacent gate structure 200 or the source/drain interconnection layer 220 in the other region except the shared contact region 100S is reduced, therefore, the probability of short circuit between the subsequent shared contact plug and other adjacent gate structures 200 or source-drain interconnection layers 220 is reduced, and the performance of the semiconductor structure is improved.
It should be noted that, in the embodiment, in the process of forming the second trench 330, since the top dielectric layer 103 is less affected by the lateral etching, a mask (mask) can be used to define the shape and the position of the second trench 330, thereby avoiding the increase of the number of masks.
In this embodiment, an anisotropic dry etching process is used to perform etching, so as to form the second trench 330.
The dry etching process has higher process controllability, and the etching selection ratio among different film layers is easy to adjust. In addition, in the dry etching process, the top dielectric layer 103, the gate cap layer 240 and the sacrificial layer 320 can be etched in the same etching device by adjusting etching gas and etching parameters, and the process is simple without converting a machine. In addition, the anisotropic dry etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate of the etching process is greater than the transverse etching rate thereof, so that the opening sizes of the second trench 330 along the first direction and the second direction can be accurately controlled, and the sidewall morphology quality of the second trench 330 can be improved.
In this embodiment, in the step of forming the second trench 330, an etching selection ratio of the sacrificial layer 320 to the gate capping layer 240 is greater than 5:1, and an etching selection ratio of the sacrificial layer 320 to the source drain capping layer 230 is greater than 5:1, so as to reduce etching damage to the gate capping layer 240 or the source drain capping layer 230 in other regions except the shared contact region 100S.
In this embodiment, along the first direction, the opening size of the second trench 330 is larger than the opening size of the first trench 310.
The first trench 310 and the second trench 330 are formed in different processes, and the opening size of the second trench 330 is larger than the opening size of the first trench 310, so that the requirement on overlay accuracy can be reduced in the process of forming the second trench 330, and the bottom of the second trench 330 and the top of the first trench 310 can be easily communicated.
In this embodiment, after the second trench 320 is formed, in the second direction, the sacrificial layer 320 with a partial width remains on the sidewall of the second trench 320 facing the boundary of the shared contact region 100S (as shown in fig. 8).
By reserving the sacrificial layer 320 with a partial width, the risk of the process for forming the second trench 320 is reduced, that is, the probability that the gate capping layer 240 or the sidewall spacer 205 adjacent to the shared contact region 100S in the second direction is damaged is reduced, so that the probability that the shared contact plug subsequently formed in the second trench 320 is shorted with the adjacent gate structure 200 is reduced.
Note that the width of the remaining sacrificial layer 320 is not too small, and is not too large. If the width of the remaining sacrificial layer 320 is too small, the probability that the gate cap layer 240 or the sidewall spacer 205 adjacent to the shared contact region 100S in the second direction is damaged is easily increased, so that the probability that the subsequent shared contact plug is shorted with the adjacent gate structure 200 is increased; if the width of the remaining sacrificial layer 320 is too large, the remaining space of the first trench 310 is smaller, so as to reduce the contact area between the subsequent common contact plug and the source/drain doped region 210, which may result in an increase in contact resistance. For this reason, in the present embodiment, the width of the residual sacrificial layer 320 is 2 nm to 10 nm. For example, the width of the remaining sacrificial layer 320 is 3 nm, 5 nm, 7 nm, or 9 nm.
It should be further noted that, in this embodiment, the first trench 310 is formed by etching the source/drain capping layer 230.
In other embodiments, the first trench may also be formed by etching the gate capping layer of the shared contact region.
Specifically, in this embodiment, the step of forming the first trench includes: and sequentially etching the gate cap layer, the side wall and the gate structure in the shared contact region to form a first groove penetrating through the gate cap layer and the gate structure.
In the forming process of the semiconductor structure, according to design requirements, the step of cutting off the gate structure along the first direction is included, so that the first groove is formed by etching the gate cap layer and the gate structure, the gate structure can be cut off and the first groove can be formed by using the same photomask (mask), and the process cost is further reduced.
Correspondingly, a second groove is formed by etching the top dielectric layer, the sacrificial layer and the source-drain cap layer on the top of the grid structure.
With combined reference to fig. 18 and fig. 19, fig. 18 is a cross-sectional view based on fig. 16, and fig. 19 is a cross-sectional view based on fig. 17, a shared contact plug 340 is formed in the first trench 310 and the second trench 330, and the shared contact plug 340 electrically connects the gate structure 200 and the source-drain doped region 210.
The shared contact plug 340 is electrically connected with the gate structure 200 and the source-drain doped region 210, so that the gate structure 200 and the source-drain doped region 210 can be connected with a common potential, and the working requirement of the device can be further met.
Specifically, the step of forming the shared contact plug 340 includes: filling a conductive material in the first trench 310 and the second trench 330, wherein the conductive material also covers the top dielectric layer 103; and with the top surface of the top dielectric layer 103 as a stop position, performing planarization treatment on the conductive material, and using the remaining conductive material as a shared contact plug 340.
In this embodiment, the process of filling the first trench 310 and the second trench 330 with the conductive material includes one or more of an electrochemical plating process, a physical vapor deposition process, and a chemical vapor deposition process.
In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.
In this embodiment, the material of the common contact plug 340 is copper. The lower resistivity of copper is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the shared contact plug 340, and correspondingly reduces the power consumption. In other embodiments, the material of the shared contact plug may also be tungsten or cobalt.
In addition, the forming method further includes: forming a gate plug (not shown) penetrating the top dielectric layer 103 and the gate capping layer 240 above the top of the gate structure 200 in the other region except the shared contact region 100S, the gate plug contacting the gate structure 200; in other regions except the shared contact region 100S, source-drain plugs (not shown) penetrating the source-drain capping layer 230 above the source-drain interconnect layer 220 are formed, and the source-drain plugs are in contact with the source-drain interconnect layer 220. .
The gate plug is used to electrically connect the gate structure 200 to an external circuit or other interconnect structure, and the source and drain plugs are used to electrically connect the source and drain doped regions 210 to an external circuit or other interconnect structure.
In this embodiment, the Gate plug is formed above the Gate structure 200 in the Active region, that is, the Gate plug is an Active Gate Contact hole plug (COAG), and compared with the scheme that the Gate plug is in Contact with the Gate structure in the isolation region, the embodiment omits a portion of the Gate structure 200 in the isolation region, which is beneficial to saving the area of the chip and further reducing the size of the chip.
Specifically, the step of forming the gate plug includes: etching the top dielectric layer 103 and the gate capping layer 240 in the non-shared contact region (i.e., in the region other than the shared contact region 100S) to form a gate contact hole (not shown) exposing the top of the gate structure 200; and forming a gate plug in the gate contact hole.
The gate capping layer 240 and the source-drain capping layer 230 have a high etching selection ratio, so that the source-drain capping layer 230 protects the source-drain interconnection layer 220 in the process of forming the gate contact hole, thereby reducing the probability of short circuit between the gate plug and the source-drain interconnection layer 220.
Specifically, the step of forming the source-drain plug includes: etching the top dielectric layer 103 and the source-drain capping layer 230 in a non-shared contact region (i.e., in a region other than the shared contact region 100S) to form a source-drain contact hole (not shown) exposing the top of the source-drain interconnection layer 220; and forming source and drain plugs in the source and drain contact holes.
Similarly, a higher etching selection ratio exists between the gate cap layer 240 and the source-drain cap layer 230, so that the gate cap layer 240 protects the gate structure 200 in the process of forming the source-drain contact hole, thereby reducing the probability of short circuit between the source-drain plug and the gate structure 200.
The specific description of the gate plug and the source-drain plug is not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a gate structure extending along a first direction is formed on the substrate, a gate cap layer is formed at the top of the gate structure, source and drain doped regions located in the substrate are formed at two sides of the gate structure, a source and drain interconnection layer is formed at the top of the source and drain doped region, and a source and drain cap layer is formed at the top of the source and drain interconnection layer, wherein a region for forming a shared contact plug electrically connected with the gate structure and the source and drain doped region on the substrate is used as a shared contact region;
etching the source-drain cap layer or the gate cap layer in the shared contact region to form a first groove penetrating through the source-drain cap layer or the gate cap layer;
forming a sacrificial layer in the first groove, wherein the etching resistance of the sacrificial layer is smaller than that of the source drain cap layer;
forming a top dielectric layer covering the sacrificial layer, the grid electrode cap layer and the source drain cap layer;
etching the top dielectric layer, the gate cap layer and the sacrificial layer on the top of the gate structure in the shared contact region, or etching the top dielectric layer, the sacrificial layer and the source drain cap layer on the top of the gate structure, and forming a second groove communicated with the first groove in the top dielectric layer and the gate cap layer;
and forming a shared contact plug in the first groove and the second groove, wherein the shared contact plug is electrically connected with the grid structure and the source-drain doped region.
2. The method for forming a semiconductor structure according to claim 1, wherein the first trench is formed by etching the source-drain cap layer;
the step of forming the first trench includes: and sequentially etching the source-drain cap layer and the source-drain interconnection layer in the shared contact region to form a first groove penetrating through the source-drain cap layer and the source-drain interconnection layer.
3. The method for forming a semiconductor structure according to claim 2, wherein in the step of providing the substrate, the source-drain doped region is formed in the substrate of the shared contact region;
in the step of forming the first trench, the first trench exposes the source-drain doped region.
4. The method of forming a semiconductor structure of claim 1, wherein the first trench is formed by etching the gate capping layer;
the step of forming the first trench includes: and sequentially etching the grid electrode cap layer and the grid electrode structure in the shared contact region to form a first groove penetrating through the grid electrode cap layer and the grid electrode structure.
5. The method for forming the semiconductor structure according to claim 1, wherein in the step of etching the sacrificial layer, an etching selection ratio of the sacrificial layer to the gate cap layer is greater than 5:1, and an etching selection ratio of the sacrificial layer to the source drain cap layer is greater than 5: 1.
6. The method for forming a semiconductor structure according to claim 1, wherein the sacrificial layer, the gate capping layer, and the source drain capping layer are made of different materials.
7. The method of claim 1, wherein in the step of etching the top dielectric layer, an etch selectivity ratio between the top dielectric layer and the sacrificial layer is less than 3: 1.
8. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer is a dielectric material.
9. The method of forming a semiconductor structure of claim 8, wherein the dielectric material comprises one or more of silicon oxide, aluminum oxide, and titanium dioxide.
10. The method of claim 8, wherein a direction parallel to the substrate surface and perpendicular to the first direction is a second direction;
in the step of forming the second trench, a partial width of the sacrificial layer remains on a sidewall of the second trench facing the boundary of the shared contact region in the second direction.
11. The method of claim 9, wherein the width of the remaining sacrificial layer is between 2 nm and 10 nm.
12. The method of forming a semiconductor structure of claim 1, wherein an opening size of the second trench is larger than an opening size of the first trench along the first direction.
13. The method of forming a semiconductor structure of claim 1, wherein an opening size of the first trench along the first direction is 16 nm to 30 nm.
14. The method of claim 1, wherein the first trench is formed by etching using an anisotropic dry etch process.
15. The method of claim 1, wherein the second trench is formed by etching using an anisotropic dry etch process.
16. The method of forming a semiconductor structure of claim 1, wherein forming a shared contact plug in the first trench and the second trench comprises: filling a conductive material in the first groove and the second groove, wherein the conductive material also covers the top dielectric layer;
and taking the top surface of the top dielectric layer as a stop position, carrying out planarization treatment on the conductive material, and taking the residual conductive material as a shared contact plug.
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