US20080277699A1 - Recess Etch for Epitaxial SiGe - Google Patents
Recess Etch for Epitaxial SiGe Download PDFInfo
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- US20080277699A1 US20080277699A1 US11/747,708 US74770807A US2008277699A1 US 20080277699 A1 US20080277699 A1 US 20080277699A1 US 74770807 A US74770807 A US 74770807A US 2008277699 A1 US2008277699 A1 US 2008277699A1
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000011066 ex-situ storage Methods 0.000 claims abstract description 24
- 238000011065 in-situ storage Methods 0.000 claims abstract description 21
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 230000008569 process Effects 0.000 description 29
- 238000004519 manufacturing process Methods 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002243 precursor Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910003828 SiH3 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical compound [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010421 standard material Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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Abstract
Description
- This invention relates to the recess etch for epitaxial SiGe in PMOS transistors.
-
FIG. 1 is a cross-sectional view of a partially fabricated semiconductor wafer. -
FIG. 2 is a cross-sectional view of an alternative partially fabricated semiconductor wafer. -
FIGS. 3A-3F are cross-sectional diagrams of a process for forming a semiconductor wafer. - The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
- Referring to the drawings,
FIG. 1 is a cross-sectional view of a partially fabricatedsemiconductor wafer 10. In the example application,PMOS transistors 20 are epitaxial SiGe transistors that are formed within asemiconductor substrate 30 having an n-well region 40. SiGe transistors containepitaxial SiGe regions 150 that may improve transistor performance by increasing the mobility of the carriers in thechannel 110 of the PMOS transistors 20 (facilitated by the intentionally created lattice mismatch that induces mechanical stress across the channel region 110). Specifically, the compressively-stressed channel typically provides an improved hole mobility that improves the performance ofPMOS transistors 20 by increasing the PMOS drive current. - The
PMOS transistors 20 are electrically insulated from other active devices (not shown) by shallowtrench isolation structures 50 formed within thesemiconductor wafer 10; however, any conventional isolation structure may be used, such as field oxide regions (also known as “LOCOS” regions) or implanted isolation regions. Thesemiconductor substrate 30 is a doped single-crystalline substrate; however, it may be comprised of a different material such as GaAs or InP, and it may have additional layers. - The active portions of the
PMOS transistors 20 are the p-type doped source/drain extension regions 60, the p-type doped source/drain regions 70, p-type dopedepitaxial SiGe regions 150, and a PMOStransistor gate stack 80 that is comprised of agate oxide 90 and a p-type dopedpolysilicon electrode 100. However, it is within the scope of the invention for the PMOS transistor to have ametal gate electrode 100 instead of apolysilicon gate electrode 100. Thechannel region 110 of thePMOS transistors 20 is located directly below thegate oxide 90 within the n-well 40. - The
PMOS transistors 20 also haveoffset layers drain regions 70 and theepitaxial SiGe regions 150. In the example application shown inFIG. 1 , the source/drain extension regions 60 are formed using thegate stack extension sidewalls 140 may be formed proximate to the gate stack 80 (as shown inFIG. 2 ) and then used with the gate stack to act as a mask when implanting the dopants for the source/drain extension regions 60. - The
gate stack 80 and theepi sidewalls 120 of thePMOS transistors 20 are used as a mask to form theepitaxial SiGe regions 150. In the example application, an ex-situ recess etch plus an in-situ recess etch are used to form the recessed active regions before the formation of theepitaxial SiGe regions 150. This etch combination (described infra) will createepitaxial SiGe regions 150 that are generally funnel shaped for adjoiningPMOS transistors 20 having a sharedsource region 70 for one example application shown inFIG. 1 . Alternatively, the cross-section of theepitaxial SiGe regions 150 are generally isosceles trapezoid shaped if the PMOS transistors are formed further apart within thesemiconductor wafer 10, as shown inFIG. 2 . - The source/
drain regions 70 are formed using thegate stack 80, theepi sidewalls 120, and the source/drain sidewalls 130 as a mask. It is to be noted that the source/drain extension anneal and the source/drain anneal will likely cause a lateral migration of the source/drain extension regions 60, theepitaxial SiGe regions 150, and the source/drain regions 70 toward thechannel region 110 of the transistor. Therefore, the borders of the source/drain extension regions 60, theepitaxial SiGe regions 150, and the source/drain regions 70 will be softer than what is illustrated inFIGS. 1-2 when looking at a cross-section of a completed integrated through a transmission electron microscope (“TEM”). - In subsequent fabrication steps (not shown), a silicide layer may be formed overlying the
polysilicon gate electrode 100 and theepitaxial SiGe regions 150. The optional silicide layer facilitates an improved electrical connection between theepitaxial SiGe regions 150 and the transistor's metal contacts (not shown). Preferably, the silicide layer contains Ni or a combination of Ni and Pt. However, it is within the scope of the invention to use any suitable material—or combination of materials—within the silicide layer, such as Co, Ti, Pd, or Ir. - The remaining “front-end” portion of a completed integrated circuit generally contains metal contacts that electrically connect the
PMOS transistors 20 ofFIGS. 1-2 to other active or passive devices that are located throughout thesemiconductor wafer 10. The front-end also generally contains an insulative dielectric layer that electrically insulates the transistor's metal contacts. The back-end of a completed integrated circuit generally contains one or more interconnect layers (and possibly one or more via layers) that properly route electrical signals and power between thePMOS transistors 20 and the other electrical components of the completed integrated circuit. - Referring again to the drawings,
FIGS. 3A-3E are cross-sectional views of a partially fabricated semiconductor wafer that illustrate an example process for forming thePMOS transistors 20 ofFIGS. 1-2 . It is within the scope of the invention to use this process to form other transistor devices that vary in some manner from theexample PMOS transistor 30. For instance, the described method may be used to fabricate PMOS transistors on alternative substrates such as silicon-on-insulator (“SOI”) or Ge on SOI. -
FIG. 3A is a cross-sectional view of thesemiconductor wafer 10 after the formation of a portion of the PMOS transistors. Specifically, thesemiconductor wafer 10 contains the shallowtrench isolation structures 50, the n-well 40 within thesubstrate 30, thegate stacks 80 comprising thegate oxide 90 and thegate electrode 100, and the source/drain extension regions 60. In the example application, the PMOStransistor gate stacks 80 were used as the mask to form the source/drain extension regions 60; however, if the optional extension sidewalls 140 (discussed supra and shown inFIG. 2 ) were used, then thesemiconductor wafer 10 will also contain theoptional extension sidewalls 140. The fabrication processes used to form thesemiconductor wafer 10 shown inFIG. 3A are those that are standard in the industry, such as the fabrication process described in the commonly assigned patent Ser. No. _,___,___ (Ser. No. 11/677,496, Ti Docket Number TI-63176, filed Feb. 21, 2007), incorporated herein by reference and not admitted to be prior art with respect to the present invention by its mention in this section. - It is within the scope of the invention for all of the gate electrodes have an optional gate hardmask comprised of SiO2, SiN, SiON, or a combination thereof (as described in the incorporated reference). If used, the gate hardmask may protect the
gate electrodes 100 from undesired etching and epitaxial formation during the processes shown inFIGS. 3C-3E and described infra. - It is also within the scope of the embodiment to form halo implant regions within the n-well 40 (not shown). The optional halo implants (sometimes called “pocket implants” or “punch through stoppers” because of their ability to stop punch through current) may be formed with any standard implant or diffusion process within—or proximate to—the channel, the extension regions, or the source/drain regions.
- As shown in
FIG. 3B , theepi sidewalls 120 are now formed proximate to thegate stack 80 in preparation for the recess etch steps (170, 190). Theepi sidewalls 120 are fabricated using any standard process. For example, one or more layers of insulating materials, such as oxide or nitride based materials, are first applied conformally over thesemiconductor wafer 10. Then an anisotropic etch is used to remove the insulating material over thegate electrode 100 and the surface of most of the n-well 40, while leavinginsulating material 120 on the sidewalls of thegate stack 80. It is to be noted that the thickness of the epi sidewalls 120 may be adjusted to change the location of the subsequently formedepitaxial SiGe regions 150 in order to obtain a targeted transistor performance (that is determined by the amount of source/drain extension regions 70 that is etched during the recess etch process and therefore the amount remaining in the final PMOS structure). The exposed surfaces of the n-well 40 after the formation of the epi sidewalls 120 (i.e. the exposed surfaces of the source/drain extension regions 60) are now theactive regions 160 of thePMOS transistors 20. - The next step in the example application is an
ex-situ recess etch 170 of theactive regions 160 of thePMOS transistor 30, as shown inFIG. 3C . Preferably, theex-situ recess etch 170 is a standard anisotropic etch of the active regions 160 (i.e. a “box etch); therefore, the sides of theex-situ recesses 180 are generally perpendicular to the surface of the n-well region 40. An anisotropicex-situ recess etch 170 will also ensure that a maximum amount of previously formed dopedextension regions 60 remains after the formation of the ex-situ recesses 180. However, it is within the scope of the example embodiment to perform anex-situ recess etch 170 using a combination of an anisotropic etch with a minimal isotropic etch. An isotropic etch will generally be balloon-shaped and undercut the extension sidewalls 60, thereby creatingex-situ recesses 180 that encroach closer to thechannel region 110 and removes more material in the source/drain extension regions 60 (resulting in a corresponding change in the dosing level of those source/drain extension regions 60). Therefore, a combination of an anisotropic etch with a minimal isotropic etch may result in a recess etch having a small taper (i.e. a minimal recess shape tunneling). - The
ex-situ recess etch 170 of the example application may be any suitable etch process. For instance, a standard plasma etch machine (such as the Kiyo by LAM) may be used at a temperature of 40-100° C., a pressure of 1-10 torr, and with HBr, CF4, and O2 precursor gases. It is to be noted that theetch 170 is considered to be “ex-situ” because it is performed in a different machine than the SiGe epitaxial deposition step (210). - It is within the scope of the invention to form the
ex-situ recesses 180 to any suitable depth (i.e. from a depth that is shallower than theextension regions 60 to a depth that is greater than the source/drain regions 70). In the example application, theex-situ recesses 180 are etched to a depth between 100-1200 Å, which is greater than the depth of the source/drain extension regions 60 and approximately the same depth as the subsequently formed source and drain regions 70 (seeFIG. 1 ). - The next step in the example application is an in-
situ recess etch 190 of the exposed n-well 40, as shown inFIG. 3D . (It is to be noted that the exposed n-well oractive regions 160 of the NMOS transistors are protected by a patterned photoresist during the recess etch steps 170, 190 of the example application.) In the example application, the in-situ recess etch 190 is an HF epi etch of the exposed n-well 40; therefore, the in-situ etch will undercut the epi sidewalls 120 (along the surface of the n-well 40 in accordance with the Si crystal plane) and also etch the exposed n-well 40. The in-situ recess etch 190 may be any suitable epi etch process, such as reduced-temperature chemical vapor deposition (“RTCVD”), ultra-high vacuum chemical vapor deposition (“UHCVD”), molecular beam epitaxy (“MBE”), or a small or large batch furnace-based process. In the example application, a standard RTCVD machine (such as the Epsilon by ASM or the Centura by AMAT) is used at a temperature range of 450-1000° C. and a pressure between 1-300 torr for a period of 30 seconds to 5 minutes with HCl and H2 gas. (Process selectivity is achieved by including the HCl (hydrochloric acid) and the carrier gas H2 (hydrogen).) It is to be noted that the time period for theepi etch 190 is generally determined by the amount of undercut desired. For example, the performance of thePMOS transistor 20 may be improved by undercutting the epi sidewalls 120 to facilitate the placement of theepitaxial SiGe regions 150 close to thechannel region 110 at the surface of n-well 40 (increasing channel stress and thereby also increasing device speed). However, it may be undesirable to continue the in-situ recess etch process until it undercuts into thechannel region 110 because the performance of the PMOS transistors may be compromised by a reducedchannel region 110. It is also to be noted that theetch 190 is considered to be “in-situ” because it is performed in the same deposition machine that will be used for the subsequent SiGe epitaxial deposition step (210). - The combination of the
ex-situ recess etch 170 and the in-situ recess etch 190 creates recessactive regions 200 that are shaped differently than recesses formed by theex-situ recess etch 170 or the in-situ recess etch 190 alone. Moreover, the depth of recessedactive regions 200 is generally controlled by theex-situ etch 170 while the width of the recessed active regions is generally controlled by the in-situ etch 190. In the example application shown inFIG. 3D , the recessed active regions have a funnel shaped cross-section (created by the angled epi-etch at the top portion of the deep box etch). In an alternative application (shown inFIG. 2 ), the recessed active regions may have an isosceles trapezoid shaped cross-section that is created by an (in-situ) angled epi-etch at approximately the same depth as the (ex-situ) box etch. - The
epitaxial SiGe regions 150 are now formed over the recessedactive regions 200 of thePMOS transistors 20, as shown inFIG. 3E . Theepitaxial SiGe regions 150 are considered ‘selective’ because the epitaxial layer is comprised of SiGe that is selectively deposited on the exposedactive silicon substrate active regions 200; however, it is not deposited on any dielectric regions, such as the regions containing SiO2 or Si3N4. Moreover, theepitaxial SiGe regions 150 may be doped or undoped. For instance, in the example application theepitaxial SiGe regions 150 are doped p-type with B. - The
epitaxial SiGe regions 150 may be formed by any suitable standard process. In the example application, theepi deposition process 210 is performed in the same machine (without breaking vacuum) as the previous in-siturecess etch process 190. More specifically, the in-situ recess etch 190 transitions smoothly into theepi deposition process 210 by reducing the flow of the HCl gas and simultaneously introducing a silicon-bearing precursor DCS (dichlorosilane), a germanium-bearing precursor GeH4 (germane), and a p-doping precursor B2H6 (diborane) into the deposition chamber. Alternatively, theepitaxial deposition process 210 may also include a carbon-bearing precursor SiH3CH3 (mono-methyl-silane). The example RTCVD process uses a temperature range of 450-800° C. and a pressure between 1-100 torr. - As shown in
FIG. 3E , theRTCVD process 210 creates a slight rise in the top surface of theepitaxial SiGe regions 150 above the top surface of the recessedactive regions 200. Therefore, theRTCVD process 210 not only back-fills the recessedactive regions 200, it also continues to grow theepitaxial SiGe regions 150 to a height somewhere above the surface of the n-well 40. Growing theepitaxial SiGe regions 150 thicker than the depth of the recessedactive regions 200 can mitigate the impact of the loss of epitaxial SiGe during the subsequent silicidation processes. - The fabrication of the
semiconductor wafer 10 now continues with standard manufacturing steps. Generally, the next steps are the formation of source/drain sidewalls 130 and the creation of the source/drain regions 70. As shown inFIG. 3F , source/drain sidewalls 130 are formed proximate to the epi sidewalls 120 using any standard material and process. For example, the source/drain sidewalls 130 may be comprised of an oxide layer and a nitride layer that are formed with a CVD process and then subsequently anisotropically etched. However, the source/drain sidewalls 130 may contain more layers (. i.e. a spacer oxide layer, a silicon nitride layer, and a final oxide layer) or less layers (i.e. only an oxide layer or a nitride layer). - Next, the source/
drain sidewalls 130 are used as a template for the source/drain implantation step. The source/drain regions 70 may be formed through any one of a variety of processes, such as deep ion implantation or deep diffusion. The dopants used to create the source/drain regions 70 for a PMOS transistor are typically boron; however, other dopants or combinations of dopants may be used. The implantation of the dopants is generally self-aligned with respect to the outer edges of the source/drain sidewalls 130. (However, it is to be noted that due to lateral straggling of the implanted species, the source and drainregions 70 may begin slightly inside the outer corner of the source/drain sidewalls 130. ) The source and drainregions 70 are then activated by an anneal step. This anneal step acts to repair the damage to the semiconductor wafer and to activate the dopants. The activation anneal may be performed by any technique such as rapid thermal anneal (“RTA”), flash lamp annealing (“FLA”), or laser annealing. - The fabrication of the final integrated circuit continues with standard fabrication processes to complete of the front-end structure and the back-end structure. The front-end fabrication process includes the formation of a silicide layer on the surfaces of the epitaxial SiGe regions and gate electrodes (as described more fully in the incorporated reference), the deposition of the pre-metal dielectric layer, and the creation of the metal contacts (within the dielectric layer) that are connected to the source/drain regions or the gate electrode. The back-end fabrication includes the formation of metal vias and interconnects. Once the fabrication process is complete, the integrated circuit will be tested and packaged.
- Various additional modifications to the invention as described above are within the scope of the claimed invention. For example, a standard pre-clean process may be performed before the ex-situ etch (in order to remove any oxide film). Instead of using the carbon-bearing precursor SiH3CH3 (methylsilane) during the epi deposition process, other suitable carbon-bearing precursors such as SiH2(CH3)2 (dimethylsilane) or SiH(CH3)3 (trimethylsilane) may be used. In addition, the flow of the source gases during the epi deposition process may be controlled to alter the composition of the strain or stress producing material comprising the epitaxial SiGe regions. Moreover, the source/drain dopants may be implanted before, after, or during the formation of the epitaxial SiGe regions.
- Furthermore, an additional anneal process may be performed after any step in the above-described fabrication process. When used, an anneal process can improve the microstructure of materials and thereby improve the quality of the semiconductor structure. In addition, higher anneal temperatures may be used in order to accommodate transistors having thicker polysilicon gate electrodes.
- Moreover, the present invention may be used during the fabrication of NMOS transistors. For example, those skilled in the art could successfully modify the methods described above to form NMOS transistors having epitaxial regions comprised of any suitable material, such as SiC.
- While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
Claims (16)
Priority Applications (2)
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US11/747,708 US7553717B2 (en) | 2007-05-11 | 2007-05-11 | Recess etch for epitaxial SiGe |
US12/407,636 US20090179236A1 (en) | 2007-05-11 | 2009-03-19 | Recess Etch for Epitaxial SiGe |
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US11/747,708 US7553717B2 (en) | 2007-05-11 | 2007-05-11 | Recess etch for epitaxial SiGe |
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US12/407,636 Division US20090179236A1 (en) | 2007-05-11 | 2009-03-19 | Recess Etch for Epitaxial SiGe |
Publications (2)
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US20080277699A1 true US20080277699A1 (en) | 2008-11-13 |
US7553717B2 US7553717B2 (en) | 2009-06-30 |
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ID=39968725
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US11/747,708 Active 2027-12-04 US7553717B2 (en) | 2007-05-11 | 2007-05-11 | Recess etch for epitaxial SiGe |
US12/407,636 Abandoned US20090179236A1 (en) | 2007-05-11 | 2009-03-19 | Recess Etch for Epitaxial SiGe |
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