CN103383961A - Finfet structure and manufacturing method thereof - Google Patents
Finfet structure and manufacturing method thereof Download PDFInfo
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- CN103383961A CN103383961A CN2012101352672A CN201210135267A CN103383961A CN 103383961 A CN103383961 A CN 103383961A CN 2012101352672 A CN2012101352672 A CN 2012101352672A CN 201210135267 A CN201210135267 A CN 201210135267A CN 103383961 A CN103383961 A CN 103383961A
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Abstract
The invention provides a FinFET structure and a manufacturing method of the FinFET structure. According to the manufacturing method of the FinFET structure, a fin-shaped channel region shaped like a triangular prism is adopted to replace a fin-shaped channel region shaped like a cuboid, two protruding faces of the FinFET structure form opposite crystal face crystal orientation structures, the scattering effect of carriers is reduced, the charge storage capacity is improved, the structure that the fin-shaped channel region is used up is formed more easily when the FinFET structure is controlled by a grid electrode, the conductive path of channels is thoroughly cut off, and therefore the driving current of an FinFET element is improved. The FinFET structure and the manufacturing method of the FinFET structure are suitable for manufacturing the FinFET element of smaller size and with higher drive current.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of FinFET structure and manufacture method thereof.
Background technology
the MOSFET(metal oxide semiconductor field effect is answered transistor) be the main member of most of semiconductor device, when channel length during less than 100nm, in traditional MOSFET, because the semi-conducting material around the Semiconductor substrate of active area makes between source electrode and drain region interactive, the distance of drain electrode and source electrode also shortens thereupon, produce short-channel effect, the so control ability variation of grid to raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is also increasing, inferior threshold values electric leakage (Subthrehhold leakage) phenomenon is more easily occured.
Fin formula field-effect transistor (Fin Field effect transistor, FinFET) be that a kind of new metal oxide semiconductor field effect is answered transistor, its structure forms on silicon-on-insulator (SOI) substrate usually, comprise that narrow and isolated silicon strip (is the channel structure of vertical-type, also claim fin), fin both sides are with grid structure.The FinFET structure makes device less, and performance is higher.
As shown in Figure 1, a kind of structure of FinFET device in prior art comprises: substrate 10, source electrode 11, drain electrode 12, fin-shaped channel district 13 and the conductive grid structure 14 that is centered around 13 both sides, fin-shaped channel district and top.Wherein, source electrode 11, drain electrode 12 and fin-shaped channel district 13, be to be covered in strained silicon layer on SOI substrate dielectric layer and ion implantation technology obtains by patterning, described fin-shaped channel district 13 is generally rectangular-shaped, and namely it is " H " font with source electrode 11st district and 12nd district that drain.The thickness in described fin-shaped channel district 13 as thin as a wafer, and three faces of its protrusion are controlled, are subject to the control of grid, can construct entirely to exhaust structure, thoroughly cut off the conductive path of raceway groove.Yet the easy scattering of charge carrier in this rectangular-shaped fin-shaped channel district 13 causes stored charge indifferent.
along with the semiconductor industry is drive on boldly to the 22nm technology node, the FinFET device that requires to make has smaller szie and Geng Gao drive current, although can pass through such as pre-amorphous injection (PAI) technology in prior art, introduced stress technology etc. makes LDD and Halo inject the super shallow junction (USJ) that forms more shallow FinFET device, improve short-channel effect (SCE), improve the drive current of FinFET device, but the structure of FinFET device of the prior art, especially the structure in fin-shaped channel district 13, limited the raising of FinFET device performance, can not satisfy the requirement of the FinFET device of making smaller szie and Geng Gao drive current.
Summary of the invention
The object of the present invention is to provide a kind of FinFET structure and manufacture method thereof, by forming the drive current of triangular prism fin-shaped channel district's raising FinFET device.
For addressing the above problem, the present invention proposes a kind of FinFET structure, comprising:
Semiconductor substrate;
Be positioned at source electrode and drain electrode on described Semiconductor substrate;
The fin-shaped channel district that is triangular prism shape between described source electrode and drain electrode; And,
Be centered around the both sides in described fin-shaped channel district and the grid structure of top.
Further, described Semiconductor substrate is silicon-on-insulator substrate or sige-on-insulator substrate.
Further, the bottom width in described fin-shaped channel district is 5nm ~ 100nm.
Further, described grid structure comprises the both sides that are centered around successively described fin-shaped channel district and gate dielectric layer and the grid layer of top.
Further, described gate dielectric layer is oxide layer single layer structure or oxide layer and high K medium layer stacked structure.
Further, the thickness of described gate dielectric layer is
Further, described grid layer comprises at least a in polysilicon and metal material.
Further, the thickness of described grid layer is 30nm ~ 800nm.
The present invention also provides a kind of manufacture method of FinFET structure, comprises the following steps:
Semiconductor substrate is provided, forms the mask layer of the patterning that covers channel region on described Semiconductor substrate;
Take the mask layer of described patterning as mask, the Semiconductor substrate that exposes is carried out pre-amorphous Implantation, form trapezoidal amorphous area wide at the top and narrow at the bottom, remove described mask layer;
Dry etching is removed described trapezoidal amorphous area, forms the fin-shaped channel district that is triangular prism shape;
Formation is centered around the grid structure of described shape channel region both sides and top.
Further, described Semiconductor substrate is silicon-on-insulator substrate or sige-on-insulator substrate.
Further, the ion of described pre-amorphous Implantation comprises at least a in Si, Ge, Xe, In, As.
Further, the angle of described pre-amorphous Implantation is 15 ~ 60o, and dosage is 1E15/cm
2~ 2E16/cm
2, energy is 5KeV ~ 100KeV.
Further, the thickness of the Semiconductor substrate of the described channel region of described dry etching removal is 10nm ~ 200nm.
Compared with prior art, FinFET structure provided by the invention and manufacture method, employing is the alternative rectangular-shaped fin-shaped channel district, fin-shaped channel district of triangular prism shape, the two sides of its protrusion forms relative crystal face crystal structure, reduce the carrier scattering effect, improve charge storage, more easily construct the fin-shaped channel district when being subject to the control of grid and entirely exhaust structure, thoroughly cut off the conductive path of raceway groove, thereby improve the drive current of FinFET device, be applicable to the manufacturing of the FinFET device of smaller szie and Geng Gao drive current.
Description of drawings
Fig. 1 is a kind of FinFET perspective view of prior art;
Fig. 2 is the FinFET perspective view of the specific embodiment of the invention;
Fig. 3 is the flow chart of manufacturing process of the FinFET structure of the specific embodiment of the invention;
Fig. 4 A to 4D is the cross-sectional view of the FinFET structure manufacturing process of the specific embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, FinFET structure and the manufacture method thereof that the present invention proposes is described in further detail.
As shown in Figure 2, the present invention proposes a kind of FinFET structure, comprising:
Be positioned at source electrode 202b and drain electrode 202a on described Semiconductor substrate;
The fin-shaped channel district 202c that is triangular prism shape between described source electrode 202b and drain electrode 202a; And,
Be centered around the grid structure 203 of both sides and the top of described fin-shaped channel district 202c.
In the present embodiment, described Semiconductor substrate 201 is silicon-on-insulator substrate or sige-on-insulator substrate.
Preferably, the bottom width of described fin-shaped channel district 202c is 5nm ~ 100nm.The fin-shaped channel district 202c of this size can regard nano wire as, by lattice mismatch strain can really be disappeared by sidewall, thereby broken away from better the restriction of Lattice Matching, higher carrier collection efficient can be provided, and then improved the drive current of FinFET device.
As shown in Figure 3, the present invention also provides a kind of manufacture method of FinFET structure, comprises the following steps:
S301 provides Semiconductor substrate, forms the mask layer of the patterning that covers channel region on described Semiconductor substrate;
S302 take the mask layer of described patterning as mask, carries out pre-amorphous Implantation to the Semiconductor substrate that exposes, and forms trapezoidal amorphous area wide at the top and narrow at the bottom and removes described mask layer;
S303, dry etching is removed described trapezoidal amorphous area, forms the fin-shaped channel district that is triangular prism shape;
S304 forms the grid structure that is centered around described shape channel region both sides and top.
Below in conjunction with accompanying drawing 4A ~ 4D, S301 shown in Figure 3 ~ S304 step is described in further detail.
Please refer to Fig. 4 A, in step S301, the Semiconductor substrate that provides is preferably silicon-on-insulator substrate or sige-on-insulator substrate.In the present embodiment, the Semiconductor substrate that provides is silicon-on-insulator substrate, comprise the silicon layer 402 on substrate layer 400, insulating barrier 401 and insulating barrier 401, can be by chemical vapour deposition (CVD) insulating barrier 401 and silicon layer 402 successively on the pure silicon substrate, silicon layer 402 can be pure Si, SiGe or SiC.Then, form the mask layer 403 of patterning on silicon layer 402, the mask layer 403 of patterning comprises the hard mask layer (HM) that is positioned on silicon layer 402 and the photoresist layer (PR) of coating, and hard mask layer (HM) can be the TEOS(tetraethoxysilane), silicon nitride etc.Wherein, when the mask layer 403 of patterning can cover the channel region of FinFET structure to be manufactured, also cover the source/drain region of FinFET structure to be manufactured, its process window exposes the silicon layer 402 of remainder, and Size dependence is in FinFET requirement on devices to be manufactured.
Please continue the 4A with reference to figure, in step S302, take the mask layer 403 of patterning as mask, carry out pre-amorphous Implantation to silicon layer 402.In the present embodiment, first inject for the first time with the forward (Fig. 4 A middle finger is to shown in bottom-right arrow) of a default inclination angle along the channel region Width, then inject for the second time with oppositely (Fig. 4 A middle finger is left shown in the arrow of below) of this default inclination angle along the channel region Width; Then please refer to Fig. 4 B, through techniques such as short annealing or laser pulse annealing, make the ion diffusion evenly, thus, the silicon layer 402 that the mask layer 403 that the silicon layer 402 that exposes below the process window of the mask layer 403 of patterning and part are patterned covers transfers amorphous state to by crystalline state, forms trapezoidal amorphous area 402a wide at the top and narrow at the bottom; Then, the stripping photolithography glue-line, and wet etching is removed hard mask layer.
Wherein, the ion of described pre-amorphous Implantation can comprise at least a in Si, Ge, Xe, In, As; The angle of described pre-amorphous Implantation can be 15 ~ 60 °, and dosage can be 1E15/cm
2~ 2E16/cm
2, energy can be 5KeV ~ 100KeV.For example, the ion of described pre-amorphous Implantation is Si, Ge, and implant angle can be 25 °, and dosage can be 5E15/cm
2, energy can be 30KeV; Perhaps the ion of described pre-amorphous Implantation is Si, Xe, and implant angle can be 45 °, and dosage can be 2E15/cm
2, energy can be 45KeV.
Please refer to Fig. 4 C, in step S303, can first be formed for making the source/drain region of FinFET structure, the patterned mask layer of channel region, take this patterned mask layer as mask, employing such as the etching mode etchings such as plasma dry etching are removed described trapezoidal amorphous area, formation is the fin-shaped channel district 402b of triangular prism shape and source/drain region (not shown, can with reference to shown in 202b, the 202a of figure 2); Then inject by source/drain region being carried out lightly-doped source/drain region (LDD) Implantation and source/drain ion, can form source electrode, drain electrode and LDD source area, LDD drain region (not shown, can with reference to shown in 202b, the 202a of figure 2).The cross section that is on the fin-shaped channel district 402b broad ways of triangular prism shape is triangle, this structural limitations dispersal direction and the degree of depth of ion, be beneficial to the more shallow super shallow junction of formation.
Wherein, the thickness of the Semiconductor substrate of the described channel region of described dry etching removal can be 10nm ~ 200nm; The bottom width of the fin-shaped channel district 402b that forms is 5nm ~ 100nm.
Need to prove, nano wire is defined as a kind of one-dimentional structure that is limited in the horizontal 100nm following (vertically there is no restriction) that has, therefore, when the bottom width of fin-shaped channel district 402b is 5nm ~ 100nm, can be seen as nano wire, in fin-shaped channel district 402b, electronics laterally is being subject to the quantum constraint, energy level is discontinuous, has quantized conductivity, and mechanical stress strengthens; Simultaneously, fin-shaped channel district 402b is triangular prism, the cross section is triangular in shape, the two sides of its protrusion forms relative crystal face crystal structure, a kind of crystal face crystal structure that is different from cuboid, cause lattice mismatch, can reduce the carrier scattering effect, improve charge storage, what more easily construct fin-shaped channel district 402b when being subject to the control of grid structure exhausts structure entirely, thoroughly cut off the conductive path of raceway groove, thereby improve the drive current of FinFET device, be beneficial to the manufacturing of the FinFET device of smaller szie and Geng Gao drive current.
And, theoretical and research all shows, the breadth length ratio of raising carrier mobility, grid capacitance, raceway groove and reduction threshold voltage etc. all increase favourable to the drive current of FinFET device, adopt the fin-shaped channel district of triangular prism to compare rectangular-shaped fin-shaped channel district, the breadth length ratio of raceway groove is larger, make the drive current of FinFET device significantly improve, higher with this FinFET device performance that obtains.
Please refer to Fig. 4 D, in step S304, can 402b both sides, fin-shaped channel district and above deposition gate dielectric layer 404a and polysilicon layer 404b, and etching and planarization form the polysilicon gate electrode structure that is centered around 402b both sides, institute fin-shaped channel district and top; Can also 402b both sides, fin-shaped channel district and above after deposition gate dielectric layer 404a, then deposit high K dielectric layer and metal material layer, and etching and planarization form the metal gate structure that is centered around 402b both sides, institute fin-shaped channel district and top.
Preferably, the thickness of described gate dielectric layer 404a is
The thickness of described grid layer 404b is 30nm ~ 800nm.
In sum, FinFET structure provided by the invention and manufacture method, employing is the alternative rectangular-shaped fin-shaped channel district, fin-shaped channel district of triangular prism shape, the two sides of its protrusion forms relative crystal face crystal structure, reduce the carrier scattering effect, improve charge storage, more easily construct the fin-shaped channel district when being subject to the control of grid and entirely exhaust structure, thoroughly cut off the conductive path of raceway groove, thereby improve the drive current of FinFET device, be applicable to the manufacturing of the FinFET device of smaller szie and Geng Gao drive current.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (17)
1. a FinFET structure, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at source electrode and drain electrode on described Semiconductor substrate;
The fin-shaped channel district that is triangular prism shape between described source electrode and drain electrode; And
Be centered around the both sides in described fin-shaped channel district and the grid structure of top.
2. FinFET structure as claimed in claim 1, is characterized in that, described Semiconductor substrate is silicon-on-insulator substrate or sige-on-insulator substrate.
3. FinFET structure as claimed in claim 1, is characterized in that, the bottom width in described fin-shaped channel district is 5nm ~ 100nm.
4. FinFET structure as claimed in claim 1, is characterized in that, described grid structure comprises the both sides that are centered around successively described fin-shaped channel district and gate dielectric layer and the grid layer of top.
5. FinFET structure as claimed in claim 4, is characterized in that, described gate dielectric layer is oxide layer single layer structure or oxide layer and high K medium layer stacked structure.
6. FinFET structure as described in claim 4 or 5, is characterized in that, the thickness of described gate dielectric layer is
7. FinFET structure as claimed in claim 4, is characterized in that, described grid layer comprises at least a in polysilicon and metal material.
8. FinFET structure as described in claim 4 or 7, is characterized in that, the thickness of described grid layer is 30nm ~ 800nm.
9. the manufacture method of a FinFET structure, is characterized in that, comprising:
Semiconductor substrate is provided, forms the mask layer of the patterning that covers channel region on described Semiconductor substrate;
Take the mask layer of described patterning as mask, the Semiconductor substrate that exposes is carried out pre-amorphous Implantation, form trapezoidal amorphous area wide at the top and narrow at the bottom, remove described mask layer;
Dry etching is removed described trapezoidal amorphous area, forms the fin-shaped channel district that is triangular prism shape;
Formation is centered around the grid structure of described shape channel region both sides and top.
10. the manufacture method of FinFET structure as claimed in claim 9, is characterized in that, described Semiconductor substrate is silicon-on-insulator substrate or sige-on-insulator substrate.
11. the manufacture method of FinFET structure as claimed in claim 9 is characterized in that, the ion of described pre-amorphous Implantation comprises at least a in Si, Ge, Xe, In, As.
12. the manufacture method of FinFET structure as claimed in claim 9 is characterized in that, the angle of described pre-amorphous Implantation is 15 ~ 60o, and dosage is 1E15/cm
2~ 2E16/cm
2, energy is 5KeV ~ 100KeV.
13. the manufacture method of FinFET structure as claimed in claim 9 is characterized in that, the thickness that described dry etching is removed the Semiconductor substrate of described channel region is 10nm ~ 200nm.
14. the manufacture method of FinFET structure as claimed in claim 9 is characterized in that, the bottom width in described fin-shaped channel district is 5nm ~ 100nm.
15. the manufacture method of FinFET structure as claimed in claim 9 is characterized in that, described grid structure comprises the both sides that are centered around successively described fin-shaped channel district and gate dielectric layer and the grid layer of top.
16. the manufacture method of FinFET structure as claimed in claim 15 is characterized in that, the thickness of described gate dielectric layer is
17. the manufacture method of FinFET structure as claimed in claim 15 is characterized in that, the thickness of described grid layer is 30nm ~ 800nm.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105161419A (en) * | 2015-06-30 | 2015-12-16 | 上海华力微电子有限公司 | Fin-type field-effect tube base body preparation method |
| CN105448688A (en) * | 2014-07-09 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Gate formation method and semiconductor device |
| CN107369712A (en) * | 2016-05-13 | 2017-11-21 | 上海新昇半导体科技有限公司 | Semiconductor structure and forming method thereof |
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