WO2018090260A1

WO2018090260A1 - Tunnel field effect transistor, and manufacturing method thereof

Info

Publication number: WO2018090260A1
Application number: PCT/CN2016/106157
Authority: WO
Inventors: 蔡皓程; 徐挽杰; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2016-11-16
Filing date: 2016-11-16
Publication date: 2018-05-24
Also published as: CN109417032A

Abstract

A tunnel field effect transistor, and manufacturing method thereof. The method comprises: forming, on a substrate, a source region having a first doping type, a drain region having a second doping type, and a trench region; forming a dummy gate region covering the trench region; forming a side wall of the dummy gate region, wherein a width of the side wall on the side of the source region is manufactured according to an overlapping region between a gate region and the source region, and a width of the side wall on the side of the drain region is manufactured according to an overlapping region between the gate region and the drain region; and removing the dummy gate region and the side wall thereof, and forming a gate region in a clearance region obtained after the dummy gate region and the side wall thereof are removed. In this way, the present invention enables, by means of the side wall of the dummy gate region, control of an overlapping region between the gate region and the source region and of an overlapping region between the gate region and the drain region.

Description

Tunneling field effect transistor and manufacturing method thereof

Technical field

The present invention relates to the field of semiconductor technologies, and in particular, to a tunneling field effect transistor and a method of fabricating the same.

Background technique

Subthreshold Swing, which is limited by the carrier Boltzmann thermal distribution, as the gate length of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is reduced to less than 45 nm. SS) severely affects the switching rate of the MOSFET device at the corresponding gate voltage, causing the leakage current of the MOSFET to increase exponentially with the decrease of the power supply voltage, so that the static power consumption increases exponentially.

Tunneling field effect transistor (TFET) has a unique quantum mechanical working mechanism with inter-band tunneling. The working principle is fundamentally different from the traditional MOSFET of carrier diffusion drift mechanism. Since the turn-on current of the TFET has no exponential dependence on the temperature, the sub-turn current is not limited by the carrier heat distribution, and a relatively small SS can be realized, thereby reducing the operating voltage of the device, reducing the shutdown current of the device, and reducing Static power consumption of the device.

The source and drain regions in the TFET are respectively doped with different doping types and distributed on both sides of the channel region. The gate region controls the on and off of the channel through the gate voltage to form a current in the device. Taking an n-type TFET as an example, when a sufficiently large voltage is applied to the gate region, the energy band of the channel region coincides with the energy band of the source region, the carrier tunnels from the source region to the channel, and the electric field acts in the drain region. The drift drifts to the drain region to form a current. Throughout the process, the overlap between the source and gate regions determines the tunneling of carriers, and the overlap between the drain and gate regions determines the subsequent transport of carriers that tunnel into the channel.

Therefore, for the TFET, a reasonable adjustment of the gate region and the source region, as well as the overlap region between the gate region and the drain region, is essential for improving the tunneling capability of the TFET, but there is currently no control over the gate region and source. A method of fabricating a region, and an overlap region between the gate region and the drain region.

Summary of the invention

Embodiments of the present invention provide a tunneling field effect transistor and a method of fabricating the same, which enable control of an overlap region between a gate region and a source region and an overlap region between a gate region and a drain region through sidewalls of the dummy gate region.

In a first aspect, a method of fabricating a tunneling field effect transistor is provided, in which a dummy gate region is formed, and sidewalls of a dummy gate region are respectively formed on a source region side and a drain region side, in the source region The sidewall width of the dummy gate region on one side is made according to the overlapping region between the gate region and the source region, and the sidewall width of the dummy gate region on the drain region side is made according to the overlapping region between the gate region and the drain region. Removing the dummy gate region and the dummy gate region sidewall, and forming a gate region in the vacant region obtained after removing the dummy gate region and the dummy gate region sidewall, thereby passing through the dummy gate region The sidewalls control the overlapping area of the gate region and the source region, and the overlapping region between the gate region and the drain region.

The source region may be a first doping type, and the drain region may be a second doping type. A dummy gate region covers the channel region.

Wherein, the sidewall of the dummy gate region may be formed of a silicon nitride material, and the sidewall of the dummy gate region forming the silicon nitride material may adopt the following embodiments:

In a possible implementation, a sidewall of the dummy gate region may be formed on the side of the source region and the side of the drain region by depositing a silicon nitride film covering the dummy gate region.

In another possible implementation, the silicon nitride film may be subjected to oblique ion implantation by depositing a silicon nitride film covering the dummy gate region and using a tilt injection method, and utilizing the dummy gate region. a three-dimensional structure shadowing effect, forming a portion of the silicon nitride film not ion-implanted on one side of the source region, and etching the silicon nitride film subjected to the oblique ion implantation by an isotropic etching method, A side wall of the dummy gate region is formed on one side of the source region.

Wherein, the dummy gate region may be formed of a polysilicon material or a silicon nitride material. If the dummy gate region is a polysilicon dummy gate region, the sidewalls of the dummy gate region and the dummy gate region may be removed by depositing a sidewall covering the dummy gate region and the dummy gate region. An oxide film; planarizing the oxide film and exposing the polysilicon dummy gate region; removing the exposed polysilicon dummy gate region using a solution containing ammonium hydroxide; removing the dummy by using phosphoric acid The sidewall of the gate region.

If the dummy gate region is a silicon nitride dummy gate region, the sidewalls of the dummy gate region and the dummy gate region may be removed by depositing the dummy gate region and the dummy gate region side Wall oxide film; The oxide film is subjected to a planarization process and exposing the silicon nitride dummy gate region and the sidewall; removing the exposed silicon nitride dummy gate region and the sidewall using phosphoric acid.

In a second aspect, a tunneling field effect transistor is provided, the tunneling field effect transistor comprising a channel region, a gate region, a source region of a first doping type, and a drain region of a second doping type, wherein: the source a region and the drain region are disposed on both sides of the channel region; the gate region is formed in a void region after the dummy gate region and the sidewall of the dummy gate region are removed; wherein the dummy gate a region covering the channel region; a width of a side wall of the dummy gate region on a side of the source region is formed according to an overlapping region between the gate region and the source region, and a side of the dummy gate region The width of the wall on one side of the drain region is made in accordance with the overlap region between the gate region and the drain region.

In a possible design, the gate region and the source region have an overlapping region, and an overlapping region between the gate region and the source region is a partial region of the source region near a side of the channel region. There is no overlapping area between the gate region and the drain region.

In another possible design, an overlap region is formed between the gate region and the source region, and an overlap region between the gate region and the source region is a portion of the source region near a side of the channel region. a region; an overlap region between the gate region and the drain region, an overlap region between the gate region and the drain region is a partial region of the drain region near a side of the channel region, forming an asymmetry The tunneling field effect transistor can weaken the bipolar conduction characteristics of the tunneling field effect transistor and improve the current driving capability of the tunneling field effect transistor.

In yet another possible design, there is no overlap between the gate region and the drain region, and between the source regions.

DRAWINGS

1 is a schematic flow chart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention;

2 is a schematic structural diagram of a tunneling field effect transistor according to an embodiment of the present invention;

3 is a schematic flow chart of another manufacturing method of a tunneling field effect transistor according to an embodiment of the present invention;

FIG. 4A to FIG. 4F are schematic diagrams showing a manufacturing process of a tunneling field effect transistor according to an embodiment of the present invention; FIG. Figure

5 is a schematic flow chart of another method for fabricating a tunneling field effect transistor according to an embodiment of the present invention;

6A-6G are schematic diagrams showing another manufacturing process of a tunneling field effect transistor according to an embodiment of the present invention;

FIG. 7 is a schematic flow chart of still another method for fabricating a tunneling field effect transistor according to an embodiment of the present invention; FIG.

8A to FIG. 8H are schematic diagrams showing another manufacturing process of a tunneling field effect transistor according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, and not all of the embodiments.

Embodiments of the present invention provide a method for fabricating a tunneling field effect transistor. In the method, a dummy gate region is formed, and sidewalls of the dummy gate region are respectively formed on one side of the source region and one side of the drain region. The sidewall width of the dummy gate region on one side of the source region is made according to the overlapping region between the gate region and the source region, and the sidewall width of the dummy gate region on the drain region side is made according to the overlapping region between the gate region and the drain region. . Removing the dummy gate region and the dummy gate region sidewall, and forming a gate region in the vacant region obtained after removing the dummy gate region and the dummy gate region sidewall, thereby passing through the dummy gate region The sidewalls control the overlapping area of the gate region and the source region, and the overlapping region between the gate region and the drain region.

1 is a schematic flow chart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention, as shown in FIG. 1 , including:

S101: providing a substrate, and forming a source region of a first doping type, a drain region of a second doping type, and a channel region, respectively, on the substrate.

In the embodiment of the present invention, the substrate may be made of a semiconductor material such as crystalline silicon, silicon on silicon, germanium, germanium or a group III-V compound.

In the embodiment of the present invention, the source region may be a heavily doped region of a first doping type, and the heavy doping refers to an impurity concentration of 1E19/cm3 to 1E21/cm ³ . The first doping type may be an N-type doping or a P-type doping.

In the embodiment of the present invention, the drain region may be a heavily doped region of the second doping type. The second doping type may be a P-type doping or an N-type doping.

In the embodiment of the invention, the channel region may be a lightly doped region of the second doping type, and the light doping refers to an impurity concentration of 1E15/cm ³ or less. The channel region may specifically be made of a semiconductor material such as silicon, germanium, germanium silicon or a III-V compound.

It can be understood that, when the first doping type is N-type doping, the second doping type is specifically P-type doping; when the first doping type is P-type doping, The second doping type is specifically N-type doping.

S102: forming a dummy gate region covering the channel region.

The position where the dummy gate region is formed in the embodiment of the present invention is a position where the gate region is subsequently formed, and may be above the channel region. The dummy gate region may be specifically formed of a polysilicon material or a silicon nitride material.

S103: forming a sidewall of the dummy gate region, wherein a width of the sidewall on a side of the source region is formed according to an overlapping region between the gate region and the source region, and the sidewall is in the drain region The width of the side is made in accordance with the overlap area between the gate region and the drain region.

In the embodiment of the present invention, the width of the sidewall of the dummy gate region on one side of the source region depends on the overlap region between the gate region and the source region, and the width gate region and the drain region of the sidewall of the dummy gate region on the drain region side. Between the overlapping areas made. In other words, the width of the overlap region between the gate region and the source region is the width of the sidewall of the dummy gate region on one side of the source region, and the width of the overlap region between the gate region and the drain region is a dummy gate region. The width of the side wall on the side of the drain.

S104: removing sidewalls of the dummy gate region and the dummy gate region, and forming a gate region in a vacant region obtained after removing sidewalls of the dummy gate region and the dummy gate region.

In the embodiment of the present invention, since the width of the sidewall of the dummy gate region is determined according to the overlapping region of the gate region and the source region, and the overlapping region between the gate region and the drain region, the dummy gate region is removed and the Forming a gate region in the vacant region obtained after the sidewall of the dummy gate region, thereby realizing an overlap region between the gate region and the source region, And control of the overlap area between the gate region and the drain region.

FIG. 2 is a schematic view showing a structure of a tunneling field effect transistor fabricated by using the tunneling field effect transistor fabrication method shown in FIG. 1. As shown in FIG. 2, the tunneling field effect transistor includes a channel region 101, a gate region 102, a source region 103 of a first doping type, and a drain region 104 of a second doping type. The source region 103 and the drain region 104 are disposed on both sides of the channel region 101. The gate region 102 is formed in the vacant region after the dummy gate region 1021 and the dummy gate region sidewall 1022 are removed. The dummy gate region 1021 covers the channel region 101. The width of the sidewall of the dummy gate region 1022 on the side of the source region 103 is obtained according to the overlapping region between the gate region 102 and the source region 103, and the sidewall of the dummy gate region 1022 is in the drain The width of the side of the region 104 is made in accordance with the overlapping region between the gate region 102 and the drain region 104.

In the embodiment of the present invention, the width of the sidewalls 1022 of the dummy gate region is determined according to the overlapping region of the gate region 102 and the source region 103, and the overlapping region between the gate region 102 and the drain region 104. The gate region 102 is formed in the vacant region obtained after the dummy gate region 1021 and the dummy gate region sidewall 1022 are removed. Therefore, in the tunneling field effect transistor provided by the embodiment of the invention, the gate region 102 and the source region are formed. The overlap region of 103, and the overlap region between the gate region 102 and the drain region 104, can be controlled by setting the dummy gate region 1021 and the dummy gate region sidewall 1022 and removing them as needed.

In the embodiment of the present invention, the gate region 102 may have an overlapping region with the source region 103 and the drain region 104, or may not overlap with the source region 103 and the drain region 104, or may have a relationship with the source region 103. There is no overlapping area between the overlap area and the drain area 104. In FIG. 2, the case where the gate region 102 and the source region 103 and the drain region 104 do not overlap each other will be described as an example.

In an embodiment of the invention, the tunneling field effect transistor may further include a substrate 105, the channel region 101, the source region 103 and the drain region 104 are disposed above the substrate 105, and the channel region 101 is located between the source region 103 and the drain region 104. The source region and the drain region in the tunneling field effect transistor are of different doping types, so the source region 103 in the embodiment of the present invention may be a heavily doped region of the first doping type, and the heavy doping refers to the impurity concentration. It is from 1E19/cm3 to 1E21/cm ³ . The first doping type may be an N-type doping or a P-type doping. The drain region 104 may be a heavily doped region of the second doping type. The second doping type may be a P-type doping or an N-type doping.

In the embodiment of the present invention, the dummy gate region 1021 may be formed of a polysilicon material or a silicon nitride material, and the dummy gate region sidewalls 1022 may be formed of a silicon nitride material.

In the embodiment of the present invention, the material formed by the dummy gate region 1021 is different, and the manner of removing the dummy gate region 1021 and the dummy gate region sidewall 1022 is also different.

Embodiments of the Invention The tunneling field effect transistor according to the embodiment of the present invention and a method for fabricating the same are described below in conjunction with practical applications.

In one embodiment, the material of the dummy gate region 1021 in the embodiment of the present invention is polysilicon, and the material of the sidewall of the dummy gate region is silicon nitride.

FIG. 3 is a schematic diagram showing a fabrication process of a tunneling field effect transistor according to an embodiment of the invention. As shown in Figure 3, it includes:

S201: providing a substrate 105, and forming a dummy gate region 1021 of a polysilicon material and a dummy gate region sidewall 1022 of a silicon nitride material on the substrate, as shown in FIG. 4A.

In the embodiment of the present invention, a gate dielectric layer and a polysilicon layer may be sequentially deposited on a substrate, and the gate dielectric layer and the polysilicon layer are photolithographically and etched to define a shape and a position of the dummy gate region to form a desired A dummy gate region 1021.

After the dummy gate region 1021 is formed, a silicon nitride film covering the dummy gate region 1021 of the polysilicon material may be deposited by a method such as chemical weather deposition or furnace control, and the silicon nitride layer is photolithographically and etched. A dummy gate sidewall 1022 is formed.

When the dummy gate region sidewall 1022 is formed in the embodiment of the present invention, the overlap region width between the dummy gate region sidewall 1022 and the source region 103 and the drain region 104 will determine the overlapping region of the subsequent gate region 102 and the source region 103, and the gate. The overlap region between the region 102 and the drain region 104, so the overlap region width between the dummy gate region sidewall 1022 and the source region 103 and the drain region 104 is based on the overlapping region of the subsequent gate region 102 and the source region 103, and the gate region. The overlap area between 102 and drain region 104 is determined. In the embodiment of the present invention, the gate region 102 may have an overlapping region with the source region 103 and the drain region 104, or may not overlap with the source region 103 and the drain region 104, or may have a relationship with the source region 103. There is no overlapping area between the overlap area and the drain area 104. In FIG. 4A, an example in which the gate region 102 and the source region 103 and the drain region 104 have overlapping regions will be described as an example. Therefore, in the embodiment of the present invention, the source area 103 side and the drain area 104 are required. The dummy gate region sidewalls 1022 are formed on one side, respectively.

In the embodiment of the present invention, the implementation steps of forming the source region 103 of the first doping type, the drain region 104 of the second doping type, and the channel region 101 are further limited, and the specific formation manner is not limited herein.

A source region 103 of a first doping type, a drain region 104 of a second doping type, a channel region 101, a dummy gate region 1021 of a polysilicon material, and a dummy gate region sidewall of a silicon nitride material are formed over the substrate 105. A schematic diagram of the structure of 1022, as shown in FIG. 4A.

The material of the gate dielectric layer in the embodiment of the present invention may be an insulating material having a low dielectric constant such as silicon dioxide, or a high dielectric constant insulating material such as tantalum and aluminum oxide.

S202: depositing an oxide film covering the dummy gate region 1021 and the dummy gate region sidewall 1022 on the basis of FIG. 4A, as shown in FIG. 4B.

S203: performing an Introduction Of Planarization Technology (CMP) on the oxide film deposited in FIG. 4B and exposing the dummy gate region 1021 of the polysilicon material, as shown in FIG. 4C.

S204: Removing the exposed polysilicon material dummy gate region 1021 in FIG. 4C using a solution containing ammonium hydroxide, resulting in the structure shown in FIG. 4D.

S205: removing the dummy gate sidewall 1022 of the silicon nitride material with phosphoric acid, as shown in FIG. 4E.

S206: forming a tunneling field effect transistor in which the gate region 102 covers the source region 103 and the drain region 104, as shown in FIG. 4F.

In FIG. 4F, an overlap region is formed between the gate region 102 and the source region 103, and an overlap region between the gate region 102 and the source region 103 is a side of the source region 103 close to the channel region. partial area. An overlap region is formed between the gate region 102 and the drain region 104, and an overlap region between the gate region 102 and the drain region 104 is a partial region of the drain region 104 near a side of the channel region.

In the embodiment of the present invention, the gate region 102 may be a high-k metal gate (HKMG).

In another embodiment, the materials of the dummy gate region 1021 and the dummy gate region sidewall 1022 in the embodiment of the present invention are all silicon nitride.

FIG. 5 is a schematic diagram showing another process of fabricating a tunneling field effect transistor according to an embodiment of the present invention. Figure. In FIG. 5, S301, S302, S303, and S305 are similar to S201, S202, S203, and S206, and therefore will not be described in detail herein. Only the differences will be described below:

The difference between the embodiment of the present invention and the method shown in FIG. 4 is that the material of the dummy gate region 1021 is silicon nitride, and when the oxide film is planarized, the dummy gate region 1021 and the dummy gate need to be exposed. The process of removing the dummy gate region 1021 and the dummy gate region sidewall 1022 together in the region sidewalls 1022, and S304.

S304: removing the dummy gate region 1021 and the dummy gate region sidewall 1022 of the exposed silicon nitride material with phosphoric acid.

In the case where the materials of the dummy gate region 1021 and the dummy gate region sidewall 1022 are both silicon nitride, a schematic diagram of a fabrication process of the tunneling field effect transistor is shown in FIGS. 6A to 6G.

In the above implementation steps of the present invention, only the process of controlling the overlapping area of the gate region and the source region and the drain region by the method of adjusting the sidewall width of the dummy gate region is schematically illustrated, and the other steps of fabricating the tunneling field effect transistor are not performed. In detail, the embodiment of the present invention does not limit the steps of the embodiment of the present invention that do not include other execution steps, such as forming a metal electrode window by using a photolithography technique and an etching technique, and forming a corresponding metal electrode.

The above-described processes of forming sidewalls such as dummy gate regions and dummy gate regions in the embodiments of the present invention may be implemented by a self-aligned process.

In the embodiment of the present invention, the above-mentioned overlapping area between the gate region and the source region and the drain region is taken as an example, but the structure in which the gate region and the source region and the drain region have overlapping regions has the problem of bipolar conduction. That is, the tunneling field effect transistor can conduct electricity under positive and negative gate voltages, and the bipolar conduction of the tunneling field effect transistor leads to an increase in the leakage current of the tunneling field effect transistor in the standby or off state, resulting in low device. Power consumption characteristics are degraded.

The structure in which the above-mentioned gate region and the source region and the drain region have overlapping regions causes bipolar conduction because the energy band of the channel region and the source region are banded when a negative voltage is applied to the gate voltage. It is not possible to overlap, but the energy band of the channel region coincides with the energy band of the drain region, and the carrier tunnels from the drain region to the channel region to form a current. Therefore, in the embodiment of the invention, the bipolar conduction of the tunneling field effect transistor is weakened. Characteristics, and improve the current drive capability of the tunneling field effect transistor, can set an asymmetric tunneling field effect crystal The tube, that is, the overlap region between the gate region and the source region, does not have an overlap region with the drain region.

FIG. 7 is a flow chart showing the fabrication of an asymmetric tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 7, the method includes:

S401: providing a substrate 105 and forming a dummy gate region 1021 of a silicon nitride material on the substrate, as shown in FIG. 8A.

S402: depositing a silicon nitride film covering the dummy gate region 1021 of the silicon nitride material by a method such as chemical weather deposition or furnace control, as shown in FIG. 8B.

S403: performing tilt ion implantation on the silicon nitride film by using a tilt angle injection method, and forming a portion of the silicon nitride film not ion implanted on the source region side by using a three-dimensional shadow effect of the dummy gate region. As shown in Figure 8C.

S404: etching the silicon nitride film subjected to the oblique ion implantation by using an isotropic etching method, and forming a dummy gate sidewall 1022 of the silicon nitride material on one side of the source region, as shown in FIG. 8D. .

The execution steps of S405, S406, S407, and S408 are similar to the execution steps of S302, S303, S304, and S305, and are not described in detail herein, except that the gate region of the tunneling field effect transistor formed in S408 covers only the source region. . A schematic structural view of the formed tunneling field effect transistor is shown in FIGS. 8E, 8F, 8G, and 8H.

In the tunneling field effect transistor structure shown in FIG. 8H, the gate region 102 and the drain region 103 do not have an overlapping region. An overlap region between the gate region 102 and the source region 103, and an overlap region between the gate region 102 and the source region 103 is a partial region of the source region 103 near a side of the channel region, forming The asymmetric tunneling field effect transistor can weaken the bipolar conduction characteristics of the tunneling field effect transistor and improve the current driving capability of the tunneling field effect transistor.

It should be further noted that the specific structures of the tunneling field effect transistors involved in the above embodiments and the drawings of the present invention are only for illustrative purposes, and are not limited thereto. The structure of the tunneling field effect transistor obtained by the method of width control gate region and overlap region between the source region and the drain region is also within the scope of the present invention. For example, the tunneling field effect transistor in the embodiment of the present invention may have a vertical structure, that is, the source region, the channel, and the drain region are located in the vertical direction. The tunneling field effect transistor having a vertical structure may be a nanowire, fin-like field effect transistor (Fin) Field-Effect Transistor, FinFET), etc.

It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be performed by a program, and the program may be stored in a computer readable storage medium, which is non-transitory ( English: non-transitory) media, such as random access memory, read-only memory, flash memory, hard disk, solid state disk, magnetic tape (English: magnetic tape), floppy disk (English: floppy disk), CD (English: optical disc) And any combination thereof.

The present invention has been described with reference to the respective flowcharts and block diagrams of the method and apparatus of the embodiments of the invention. It will be understood that each flow and block of the flowchart illustrations. FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. A device that implements the functions specified in one or more blocks of a flowchart or a plurality of flows and block diagrams.

The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or within the technical scope disclosed by the present invention. Alternatives are intended to be covered by the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

A method for fabricating a tunneling field effect transistor, comprising:

Forming a source region of a first doping type, a drain region of a second doping type, and a channel region, respectively, on the substrate;

Forming a dummy gate region covering the channel region;

Forming a sidewall of the dummy gate region, a width of the sidewall on a side of the source region being formed according to an overlap region between the gate region and the source region, the sidewall being on a side of the drain region The width is made according to an overlapping area between the gate region and the drain region;

The sidewalls of the dummy gate region and the dummy gate region are removed, and a gate region is formed in a void region obtained after removing sidewalls of the dummy gate region and the dummy gate region.
The method of claim 1 wherein forming sidewalls of said dummy gate region comprises:

Depositing a silicon nitride film covering the dummy gate region;

Side walls of the dummy gate region are formed on one side of the source region and one side of the drain region, respectively.
The method of claim 1 wherein forming sidewalls of said dummy gate region comprises:

Depositing a silicon nitride film covering the dummy gate region;

The silicon nitride film is subjected to oblique ion implantation by using a tilt angle implantation method, and a silicon nitride film which is not ion-implanted is formed on one side of the source region by using a three-dimensional shadow effect of the dummy gate region;

The silicon nitride film subjected to the oblique ion implantation is etched by an isotropic etching method, and sidewalls of the dummy gate region are formed on one side of the source region.
The method according to any one of claims 1 to 3, wherein the dummy gate region is a polysilicon dummy gate region;

The removing sidewalls of the dummy gate region and the dummy gate region includes:

Depositing an oxide film covering the dummy gate region and the sidewall of the dummy gate region;

Performing a planarization process on the oxide film and exposing the polysilicon dummy gate region;

Removing the exposed polysilicon dummy gate region using a solution comprising ammonium hydroxide;

The sidewalls of the dummy gate region are removed using phosphoric acid.
The method according to any one of claims 1 to 3, wherein the dummy gate region is a silicon nitride dummy gate region;

The removing sidewalls of the dummy gate region and the dummy gate region includes:

Depositing an oxide film covering the dummy gate region and the sidewall of the dummy gate region;

Performing a planarization process on the oxide film and exposing the silicon nitride dummy gate region and the sidewall;

The exposed silicon nitride dummy gate region and the sidewall are removed using phosphoric acid.
A tunneling field effect transistor, comprising: a channel region, a gate region, a source region of a first doping type, and a drain region of a second doping type, wherein:

The source region and the drain region are disposed on both sides of the channel region;

The gate region is formed in a void region after the dummy gate region and the sidewall of the dummy gate region are removed;

Wherein the dummy gate region covers the channel region;

A width of a sidewall of the dummy gate region on a side of the source region is formed according to an overlapping region between the gate region and the source region, and a sidewall of the dummy gate region is on a side of the drain region The width is made according to the overlapping area between the gate region and the drain region.
The tunneling field effect transistor according to claim 6, wherein an overlap region is formed between the gate region and the source region, and an overlap region between the gate region and the source region is the source a portion of the area near a side of the channel region;

There is no overlapping area between the gate region and the drain region.
The tunneling field effect transistor according to claim 6, wherein an overlap region is formed between the gate region and the source region, and an overlap region between the gate region and the source region is the source a portion of the area near a side of the channel region;

An overlap region is formed between the gate region and the drain region, and an overlap region between the gate region and the drain region is a partial region of the drain region near a side of the channel region.
The tunneling field effect transistor of claim 6 wherein there is no overlap between said gate region and said drain region and between said source region.