WO2018120170A1

WO2018120170A1 - Manufacturing method for tunnelling field-effect transistor, and tunnelling field-effect transistor

Info

Publication number: WO2018120170A1
Application number: PCT/CN2016/113844
Authority: WO
Inventors: 蔡皓程; 徐挽杰; 张臣雄
Original assignee: 华为技术有限公司
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2018-07-05

Abstract

Disclosed are a manufacturing method for a tunnelling field-effect transistor, and a tunnelling field-effect transistor. The manufacturing method comprises: first using a spindle structure (13) to define a source region (21), and then forming a first gap wall (14) and a second gap wall (151) on two sides of the spindle structure (13), thus using the spindle structure (13), the first gap wall (14) and the second gap wall (151) as a mask to form a drain region (17); then removing the spindle structure (13), forming the source region (21) in a position of the spindle structure (13), and finally forming a gate structure (25) in a position of the first gap wall (14), so that the manufacturing method is not limited by a photolithography technique when the source region (21) and the drain region (17) are formed. In addition, the manufacturing method for a tunnelling field-effect transistor can use the second gap wall (151) to strictly control a non-overlapping region between the gate structure (25) and the drain region (17) so as to reduce a leak current of the tunnelling field-effect transistor, and uses an overlapping region between the gate structure (25) and the source region (21) to increase a turning-on current of the tunnelling field-effect transistor.

Description

Tunneling field effect transistor manufacturing method and tunneling field effect transistor

Technical field

The present invention relates to the field of semiconductor technologies, and in particular, to a method for fabricating a tunneling field effect transistor and a tunneling field effect transistor fabricated by the fabrication method.

Background technique

Subthreshold Swing limited by carrier Boltzmann thermal distribution as the gate length of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) shrinks below 45 nm , SS)) can seriously affect the switching rate of the metal-oxide-semiconductor field effect transistor at the corresponding gate voltage, causing the leakage current of the metal-oxide-semiconductor field effect transistor to increase exponentially with the decrease of the power supply voltage, resulting in The static losses of metal-oxide-semiconductor field effect transistors increase exponentially.

Tunneling Field Effect Transistor (TFET), as a potential replacement for MOSFETs, works with a tunneling mechanism. From the working principle, since the turn-on current of TFET has no exponential dependence on temperature, its sub-negative current is not limited by the carrier heat distribution, and a relatively small SS can be realized, thereby reducing the tunneling field effect transistor. The operating voltage reduces the turn-off current of the tunneling field effect transistor and reduces the static power consumption of the tunneling field effect transistor.

However, the tunneling field effect transistor is still in the research stage. Therefore, the tunneling field effect transistor and its fabrication method are called technical problems to be solved by those skilled in the art.

Summary of the invention

To solve the above problems, in a first aspect, an embodiment of the present invention provides a method for fabricating a tunneling field effect transistor, including:

Providing a substrate having a first oxide layer formed on the surface thereof;

Forming a spindle structure on a side of the first oxide layer facing away from the substrate, the predetermined region for forming a source region;

Forming a first spacer on the sidewall of the spindle structure;

Forming a second spacer wall on a side of the first spacer wall facing away from the spindle structure;

Removing the first oxide layer not covered by the spindle structure, the first spacer and the second spacer to form a first exposed region;

Forming a first doped region in a portion of the substrate corresponding to the first exposed region, the first doped region being a drain region;

Removing the spindle structure and the first oxide layer covered by the spindle structure, exposing the predetermined region, and forming a second exposed region on the surface of the substrate;

Forming a second doped region in a surface of the substrate corresponding to the second exposed region, the second doped region is different from the doping type of the first doped region, and the second doped region is a source Area;

Removing the first spacer and a first oxide layer covered by the first spacer, forming a gate structure on a surface of the substrate, the gate structure not overlapping the drain region and The source areas at least partially overlap.

The method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention first defines a source region by using a spindle structure, and then forms a first spacer wall and a second spacer wall on both sides of the spindle structure, thereby utilizing the spindle structure and the first The spacer wall and the second spacer wall serve as a mask to form a drain region; then the spindle structure is removed, a source region is formed at the spindle structure, and finally a gate structure is formed at the first spacer wall, thereby making the fabrication side The method is not limited by the photolithography process when forming the source and drain regions.

Optionally, the second spacer is a silicon oxide layer, and the second spacer has a density greater than a density of the first oxide layer.

In conjunction with the first aspect, in a first possible implementation manner of the present invention, a doping concentration of the source region is greater than a doping concentration of the drain region to increase an on current of a tunneling field effect transistor.

With reference to the first aspect, in a second possible implementation manner of the present invention, the forming process of the first oxide layer is an oxidation process; the thickness of the first oxide layer ranges from 10 nm to 100 nm, including The endpoint value is such that the first oxide layer is too thin to be broken, while avoiding the first oxide layer being too thick to facilitate subsequent removal.

In conjunction with the first aspect, in a third possible implementation of the present invention, forming the first spacer on the sidewall of the spindle structure includes:

Forming a first cover layer on a side of the spindle structure facing away from the substrate, the first cover layer completely covering the surface of the spindle structure, the sidewall of the spindle structure, and the surface of the substrate; The cover layer is anisotropically etched to remove the first cover layer of the surface of the spindle structure and the surface of the substrate, and the first cover layer of the sidewall of the spindle structure is retained to form a first spacer.

In conjunction with the first aspect, in a fourth possible implementation of the present invention, forming the second spacer on a side of the first spacer facing away from the spindle structure includes:

Forming a second cover layer on a side of the spindle structure facing away from the substrate, the second cover layer completely covering the surface of the spindle structure, the first spacer wall surface and the surface of the substrate;

Performing isotropic etching on the second cover layer to remove the surface of the main spindle structure and the second cover layer of the surface of the substrate, and retain a second cover of the first spacer wall away from the side of the spindle structure The layer forms a second spacer.

With reference to the first aspect, in a fifth possible implementation manner of the present invention, forming a first doped region in a portion of the substrate corresponding to the first exposed region includes:

Etching the first exposed region of the substrate with the first spindle structure and the second spacer wall of the sidewall of the spindle structure as a mask, and removing the substrate corresponding to the first a portion at the bare region such that a surface of the substrate corresponding to the first exposed region is lower than a surface of the substrate corresponding to the predetermined region;

Forming a first doped layer on a surface of the substrate corresponding to the first exposed region until a surface of the first doped layer facing away from the substrate is at a predetermined region corresponding to the substrate The surface is flush to form a first doped region.

With reference to the first aspect, in a sixth possible implementation manner of the present invention, forming a first doped region in a surface of the substrate corresponding to the first bare region includes: the spindle structure and sidewalls of the spindle structure The first spacer and the second spacer are masks, and the portion of the substrate corresponding to the first exposed region is ion-doped, and the first doping is formed in the surface of the substrate corresponding to the first exposed region region.

With reference to the first aspect, in a seventh possible implementation, the first spacer and the first oxide layer covered by the first spacer are removed, and a gate structure is formed on the surface of the substrate, The gate structure does not overlap the drain region and at least partially overlaps the source region includes:

Forming a fifth cover layer on a side of the first doped region facing away from the substrate, the fifth cover layer further covering the fourth cover layer surface, the first gap wall surface and the second spacer wall surface;

Flattening the fifth cover layer until the first spacer wall surface and the second spacer wall surface are exposed;

Removing the first spacer, forming a third recess, the third recess exposing a portion of the first oxide layer;

Removing the first oxide layer exposed by the third groove while removing part of the fifth cover layer to form a fourth groove, the fourth groove at least partially overlapping the source region;

A gate structure is formed in the fourth recess.

With reference to the seventh possible implementation manner of the first aspect, in the eighth possible implementation, when the second spacer and the fifth cover layer are silicon oxide layers, the second spacer The density is greater than the density of the first oxide layer, and the density of the second spacer is greater than the density of the fifth cover layer to ensure the first oxide layer and the fifth cover layer when The second spacer is not removed, such that the subsequently formed gate structure does not overlap the drain region.

In a second aspect, an embodiment of the present invention provides a method for fabricating another tunneling field effect transistor, including:

Providing a substrate having a first oxide layer formed on the surface thereof;

Forming a spindle structure on a side of the first oxide layer facing away from the substrate; the predetermined region is used to form a drain region;

Forming a first spacer on the sidewall of the spindle structure;

Removing the first oxide layer not covered by the main shaft structure and the first spacer to form a first exposed area;

Forming a first doped region in a portion of the substrate corresponding to the first exposed region, the first doped region being a source region;

Removing the spindle structure, exposing the predetermined area to form a first groove;

Forming a third spacer on a side of the first spacer facing the first recess, and removing a first oxide layer not covered by the first spacer and the third spacer, on the substrate Forming a second exposed area on the surface;

Forming a second doped region in the surface of the substrate corresponding to the second exposed region, the second doping The region is different from the doping type of the first doped region, and the second doped region is a drain region;

The method for fabricating the tunneling field effect transistor provided by the embodiment of the present invention first defines a drain region by using a spindle structure, and then forms a first spacer wall on both sides of the spindle structure, thereby using the spindle structure and the first spacer wall as a mask. Forming a first doped region; then removing the spindle structure, exposing the predetermined region, and forming a third spacer on a side of the first spacer facing the predetermined region to form a second exposed region, at the second bare A second doped region is formed at the region, and finally a gate structure is formed at the first spacer, so that the fabrication method is not limited by the photolithography process when forming the first doped region and the second doped region.

In conjunction with the second aspect, in a first possible implementation manner of the present invention, a doping concentration of the source region is greater than a doping concentration of the drain region to increase an on current of a tunneling field effect transistor.

With reference to the second aspect, in a second possible implementation manner of the present invention, the forming process of the first oxide layer is an oxidation process; the thickness of the first oxide layer ranges from 10 nm to 100 nm, including The endpoint value is such that the first oxide layer is too thin to be broken, while avoiding the first oxide layer being too thick to facilitate subsequent removal.

In conjunction with the second aspect, in a third possible implementation of the present invention, forming the first spacer on the sidewall of the spindle structure includes:

Forming a first cover layer on a side of the spindle structure facing away from the substrate, the first cover layer being completely Covering the surface of the spindle structure, the sidewall of the spindle structure, and the surface of the substrate; performing an isotropic etching on the first cover layer to remove the first cover of the surface of the spindle structure and the surface of the substrate a layer retaining a first cover layer of the sidewall of the spindle structure to form a first spacer.

With reference to the second aspect, in a fourth possible implementation manner of the present invention, forming the first doped region in the portion of the substrate corresponding to the first exposed region includes:

Etching the first exposed region of the substrate with the spindle structure and the first spacer of the sidewall of the spindle structure as a mask to remove a portion of the substrate corresponding to the first exposed region The surface of the substrate corresponding to the first exposed area is lower than the surface of the substrate corresponding to the predetermined area;

With reference to the second aspect, in a fifth possible implementation, the forming the first doped region in the surface of the substrate corresponding to the first bare region comprises: the spindle structure and the sidewall of the spindle structure A spacer is a mask, and a portion of the substrate corresponding to the first exposed region is ion-doped, and a first doped region is formed in a surface of the substrate corresponding to the first exposed region.

With reference to the second aspect, in a sixth possible implementation, the spindle structure is removed, and exposing the preset area includes:

Forming a third cover layer on the surface of the first doped region, the third cover layer, the first doped region, the first spacer, and the spindle structure;

Flattening the third cover layer until the surface of the polysilicon layer in the spindle structure is exposed;

The polysilicon layer is removed, and the predetermined area is exposed to form a first recess.

With reference to the second aspect, in a seventh possible implementation, a third spacer is formed on a side of the first spacer facing the first recess, and is removed from the first spacer and the first spacer The first oxide layer covered by the three gap walls, forming a second exposed area on the surface of the substrate comprises:

Forming a fourth cover layer on a side of the first spacer wall facing the first groove, the fourth cover layer completely covering the substrate, the first spacer, and the first doped region ;

Performing isotropic etching on the fourth cover layer to remove the substrate, the first spacer, and the fourth cover layer above the first doped region, leaving only the first spacer facing a fourth covering layer on one side of the first groove, forming a third gap wall;

The first oxide layer not covered by the first spacer and the third spacer is removed.

With reference to the second aspect, in an eighth possible implementation, the first spacer and the first oxide layer covered by the first spacer are removed, and a gate structure is formed on the surface of the substrate, The gate structure does not overlap the drain region and at least partially overlaps the source region includes:

Forming a fifth cover layer on a side of the second doped region facing away from the substrate, the fifth cover layer further covering the fourth cover layer surface, the first gap wall surface and the third gap wall surface;

Flattening the fifth cover layer until the first spacer wall surface and the third spacer wall surface are exposed;

A gate structure is formed in the fourth recess.

In conjunction with the eighth possible implementation of the second aspect, in a ninth possible implementation, when the third spacer and the fifth cover layer are silicon oxide layers, the third spacer The density of the first oxide layer is greater than the density of the first spacer layer, and the density of the third spacer layer is greater than the density of the fifth cladding layer to ensure the first oxide layer and the fifth cladding layer The third spacer is not removed, such that the subsequently formed gate structure does not overlap the drain region.

In a third aspect, the present invention also provides a method for fabricating a tunneling field effect transistor, including:

Providing a substrate having a first oxide layer formed on the surface thereof;

Forming a spindle structure on a side of the first oxide layer facing away from the substrate, the predetermined area including a first preset area and a second preset area, wherein the first preset area is used for Forming a drain region, the second predetermined region being used to form a source region;

Forming a first spacer on the sidewall of the spindle structure;

Removing a second spacer located on a side of the first spacer facing away from the drain region, and forming a first doped region at a portion of the substrate corresponding to the first exposed region;

The spindle structure and the first oxide layer covered by the spindle structure are removed, the predetermined region is exposed, and a second exposed region is formed on the surface of the substrate.

Forming a second doped region in a surface of the substrate corresponding to the second exposed region, wherein the doping type of the second doped region and the first doped region are different;

Removing the first spacer and a first oxide layer covered by the first spacer, forming a gate structure on a surface of the substrate, the gate structure not overlapping the drain region and At least part of the source area Stack.

In conjunction with the third aspect, in a first possible implementation, the doping concentration of the source region is equal to or greater than a doping concentration of the drain region.

In conjunction with the third aspect, in a second possible implementation manner, the forming process of the first oxide layer is an oxidation process; the thickness of the first oxide layer ranges from 10 nm to 100 nm, including an endpoint value.

In conjunction with the third aspect, in a third possible implementation, forming the first spacer on the sidewall of the spindle structure includes:

In conjunction with the third aspect, in a fourth possible implementation, forming the second spacer on a side of the first spacer facing away from the spindle structure includes:

With reference to the third aspect, in a fifth possible implementation, the second spacer is located on a side of the first spacer facing away from the drain region, where the substrate corresponds to the first exposed region Forming the first doped region includes:

Forming a second mask on a side of the spindle structure facing away from the substrate, the second mask covering the spindle structure and a first spacer and a second on a side of the spindle structure facing the drain region a spacer, exposing the second spacer wall of the spindle structure facing away from the drain region;

Using the second mask as a mask, removing a second spacer located on a side of the spindle structure facing away from the drain region;

Removing the second mask;

Forming a first doped region in a surface of the substrate corresponding to the first bare region by using the main shaft structure and the first and second spacers of the sidewall of the main shaft structure as a mask.

With reference to the fifth possible implementation of the third aspect, in a sixth possible implementation, the first and second spacers of the main shaft structure and the side wall of the main shaft structure are used as a mask Forming the first doped region in the surface of the substrate corresponding to the first exposed region includes:

With reference to the fifth possible implementation manner of the third aspect, in the seventh possible implementation, the first spacer wall and the second spacer wall of the main shaft structure and the side wall of the main shaft structure are used as a mask Forming the first doped region in the surface of the substrate corresponding to the first exposed region includes:

Blocking the main shaft structure and the first and second gap walls of the side wall of the main shaft structure a film, ion doping the portion of the substrate corresponding to the first exposed region, and forming a first doped region in a surface of the substrate corresponding to the first exposed region.

With reference to the third aspect, in an eighth possible implementation, the first spacer and the first oxide layer covered by the first spacer are removed, and a gate structure is formed on the surface of the substrate, The gate structure does not overlap the drain region and at least partially overlaps the source region includes:

Forming a fifth cover layer on a side of the second doped region facing away from the substrate, the fifth cover layer further covering the third cover layer surface, the first spacer wall surface, the second spacer wall, and the third layer Gap surface;

Flattening the fifth cover layer until the first spacer wall surface, the second spacer wall surface, and the third spacer wall surface are exposed;

A gate structure is formed in the fourth recess.

With reference to the eighth possible implementation manner of the third aspect, in a ninth possible implementation manner, when the second spacer is a silicon dioxide layer, the second spacer has a density greater than the first Densification of the oxide layer and the fifth cap layer, so that when the first oxide layer and the fifth cap layer are ensured, the second spacer is not removed, so that the subsequently formed gate structure and The drain regions do not overlap.

When the third spacer is a silicon dioxide layer, a density of the third spacer is greater than a density of the first oxide layer and the fifth cladding layer to ensure the first oxide layer And the fifth gap layer is not removed, so that the subsequently formed gate structure does not overlap the drain region.

In a fourth aspect, the embodiment of the present invention further provides a tunneling field effect transistor, which is fabricated by using any one of the above manufacturing methods, and includes:

Substrate:

a gate structure on a surface of the substrate;

Located in the surface of the substrate, oppositely disposed source and drain regions, wherein the gate structure does not overlap the drain region and at least partially overlaps the source region.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a flow chart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view showing the steps of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention; FIG.

FIG. 19 is a flowchart of a method for fabricating a tunneling field effect transistor according to another embodiment of the present invention; FIG.

20 is a cross-sectional view showing the steps of a method for fabricating a tunneling field effect transistor according to another embodiment of the present invention;

FIG. 36 is a flowchart of a method for fabricating a tunneling field effect transistor according to still another embodiment of the present invention; FIG.

37-55 are cross-sectional views showing the steps of a method of fabricating a tunneling field effect transistor according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The embodiment of the invention provides a method for fabricating a tunneling field effect transistor. As shown in FIG. 1 , the manufacturing method includes:

S11: As shown in FIG. 2, a substrate 11 is provided, and a surface of the substrate 11 is formed with a first oxide layer 12.

In the embodiment of the present invention, the substrate 11 is a silicon substrate on an insulating substrate, and includes a silicon substrate 111 and a first insulating structure 112 on both sides of the silicon substrate 111, the first insulating structure The surface of 112 is lower than the surface of the silicon substrate 111. Alternatively, the silicon substrate 111 may be an intrinsic semiconductor substrate or a low doped semiconductor substrate; when the silicon substrate 111 is low In the case of a doped semiconductor substrate, the silicon substrate 111 may be a low-doped semiconductor substrate, or may be formed by ion doping in an intrinsic semiconductor, which is not limited by the present invention. Depending on the situation.

It should be noted that, in the embodiment of the present invention, the doping type of the silicon substrate 111 may be N-type doping or P-type doping, which is not limited by the present invention, as the case may be. set. Hereinafter, a method of fabricating a tunneling field effect transistor according to an embodiment of the present invention will be described by taking a silicon substrate 111 in which the silicon substrate 111 is a P-type doping as an example.

Specifically, in one embodiment of the present invention, the process of forming the first oxide layer 12 on the substrate 11 is preferably an oxidation process to increase the density of the first oxide layer 12 for protecting the silicon substrate. Material 111. When the formation process of the first oxide layer 12 is an oxidation process, since the first insulation structure 112 cannot be oxidized, the first oxide layer 12 is formed only on the exposed surface of the silicon substrate 111.

It should be noted that, in the embodiment of the present invention, the thickness of the first oxide layer 12 ranges from 10 nanometers to 100 nanometers, including the endpoint value, to prevent the first oxide layer 12 from being broken through. At the same time, avoiding the first oxide layer 12 being too thick is not convenient for subsequent removal.

S12: As shown in FIG. 3, a predetermined structure is formed on a side of the first oxide layer 12 facing away from the substrate 11, and the predetermined area is used to form a source region.

Optionally, forming the spindle structure 13 on the surface of the first oxide layer 12 includes: forming a polysilicon layer 131 on a side of the first oxide layer 12 facing away from the substrate 11; and facing the polysilicon layer 131 away from the polysilicon layer Forming a first mask 132 on one side of the layer 131; etching the first mask 132 and the polysilicon layer 131 to retain the polysilicon layer 131 and the first mask 132 at the predetermined region Forming a spindle structure 13.

It should be noted that, in the embodiment of the present invention, the spindle structure 13 may cover only the preset area, and may also extend to cover the first insulating structure 112. The present invention does not limit this, as the case may be. And set.

Optionally, in the embodiment of the present invention, the first mask 132 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or a silicon oxide layer or a silicon nitride layer. The laminated structure of at least two layers in the silicon oxynitride layer is not limited in the present invention, and is specifically determined as the case may be.

S13: As shown in FIG. 4, a first spacer 14 is formed on the sidewall of the spindle structure 13.

Specifically, in an embodiment of the present invention, forming the first spacer 14 on the sidewall of the spindle structure 13 includes:

Forming a first cover layer on a side of the spindle structure 13 facing away from the substrate, the first cover layer completely covering the surface of the spindle structure 13, the sidewall of the spindle structure 13 and the surface of the substrate 11; The first cover layer is anisotropically etched to remove the surface of the spindle structure 13 and the first cover layer of the surface of the substrate 11, and the first cover layer of the sidewall of the spindle structure 13 is retained to form a first Clearance wall 14.

It should be noted that, in the embodiment of the present invention, the first cover layer may be a silicon dioxide layer, or may be a silicon oxynitride layer or a silicon nitride layer, which is not limited by the present invention, as the case may be. And set. Hereinafter, a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention will be described by taking the first cladding layer as a silicon oxynitride layer as an example.

S14: forming a second spacer 151 on a side of the first spacer 14 facing away from the spindle structure 13.

Specifically, in an embodiment of the present invention, forming the second spacer 151 on a side of the first spacer 14 facing away from the spindle structure 13 includes:

As shown in FIG. 5, a second cover layer 15 is formed on a side of the spindle structure 13 facing away from the substrate 11, and the second cover layer 15 completely covers the surface of the spindle structure 13, the first spacer 14 The surface and the surface of the substrate 11. Wherein, the second cover layer 15 is preferably a silicon dioxide layer;

As shown in FIG. 6, the second cover layer 15 is anisotropically etched to remove the surface of the spindle structure 13 and the second cover layer 15 of the surface of the substrate 11, leaving the first spacer 14 The second cover layer 151 is formed away from the second cover layer 15 on the side of the spindle structure 13.

S15: as shown in FIG. 7, the removal of the spindle structure 13, the first spacer 14 and the The first oxide layer 12 covered by the second spacers 151 forms a first exposed region.

It should be noted that, in the embodiment of the present invention, when the second cover layer 15 and the first oxide layer 12 are the same material, when the second cover layer 15 on the surface of the substrate 11 is removed, it is preferred. The first oxide layer 12 exposed on the surface of the substrate 11 is removed together. When the second cover layer 15 and the first oxide layer 12 are different materials, the second cover layer 15 and the first oxide layer 12 may be removed in the same process, or may be removed in different processes. The invention is not limited thereto, and is determined by the circumstances.

S16: As shown in FIG. 8, a first doping region 17 is formed on a portion of the substrate 11 corresponding to the first bare region.

In an embodiment of the present invention, forming the first doped region 17 at a portion of the substrate 11 corresponding to the first exposed region includes: a first sidewall of the spindle structure 13 and the spindle structure 13 The spacer 14 and the second spacer 151 are masks, and a first doped region 17 is formed in a surface of the substrate 11 corresponding to the first bare region, and a lower surface of the first doped region 17 and the first The upper surface of an insulating structure 112 is flush.

On the basis of the above embodiments, in one embodiment of the present invention, the first spacer 14 and the second spacer 151 of the sidewall structure 13 and the sidewall of the spindle structure 13 are used as a mask. Forming the first doped region 17 in the surface of the first exposed region of the substrate 11 includes: using the main structure 13 and the first spacer 14 and the second spacer 151 of the sidewall of the main shaft structure 13 as a mask, Etching the first exposed region of the substrate 11 to remove a portion of the substrate 11 corresponding to the first exposed region such that a surface of the substrate 11 corresponding to the first exposed region is lower than The substrate 11 corresponds to a surface at the predetermined region; a first doped layer is formed on a surface of the substrate 11 corresponding to the first exposed region until the first doped layer faces away from the base Surface and side of material 11 The substrate 11 is flush with the surface at the predetermined area to form the first doped region 17.

Optionally, when the substrate 11 includes a silicon substrate 111 and a first insulating structure 112 on both sides of the silicon substrate 111, the first structure of the spindle structure 13 and the sidewall of the spindle structure 13 The spacer 14 and the second spacer 151 are masks, and the first exposed region of the substrate 11 is etched until the surface of the substrate 11 corresponding to the first exposed region and the first insulation The surface of structure 112 is flush.

In another embodiment of the present invention, the first spacer 14 and the second spacer 151 of the sidewall of the main shaft structure 13 and the main shaft structure 13 are used as a mask, and the substrate 11 corresponds to the first bare Forming the first doped region 17 in the surface of the region includes: the first spacer 14 and the second spacer 151 of the sidewall structure 13 and the sidewall of the spindle structure 13 as a mask, corresponding to the substrate 11 A portion of the first exposed region is ion doped, and a first doped region 17 is formed in a surface of the substrate 11 corresponding to the first exposed region.

S17: removing the spindle structure 13 and the first oxide layer 12 covered by the spindle structure 13, exposing the predetermined region, and forming a second exposed region on the surface of the substrate 11.

Specifically, in an embodiment of the present invention, the spindle structure 13 and the first oxide layer 12 covered by the spindle structure 13 are removed, and the predetermined region is exposed to form a second surface on the surface of the substrate 11. The bare areas include:

As shown in FIG. 9, a third cover layer 18 is formed on a side of the spindle structure 13 facing away from the substrate 11, and the third cover layer 18 completely covers the surface of the substrate 11 and the first doped region. 17 a surface, a surface of the spindle structure 13 and surfaces of the first spacer 14 and the second spacer 151. The third cover layer 18 is preferably a silicon dioxide layer, and the formation process may be FCVD (Fluid chemical vapor deposition), SOG (Spin on glass), spin coater. High-density plasma chemical vapor deposition (HDPCVD) or high-aspect-ratio process (HARP), which is not limited by the present invention, as the case may be. set.

As shown in FIG. 10, the third cap layer 18 is planarized until the surface of the polysilicon layer 131 in the spindle structure 13 is exposed. The planarization of the third cap layer 18 may be performed by using an etching process, a chemical mechanical polishing process, or an etching process and a chemical mechanical polishing process. The invention is not limited thereto, as the case may be. And set.

As shown in FIG. 11, the polysilicon layer 131 in the spindle structure 13 is removed, and the portion of the first oxide layer 12 corresponding to the predetermined region is exposed to form a first recess 133; optionally, implemented in the present invention. In the example, the polysilicon layer 131 in the spindle structure 13 is removed by using an ammonia-containing solution (such as TMAN), but the invention is not limited thereto, as the case may be.

As shown in FIG. 12, the first oxide layer 12 exposed by the first recess 133 is removed to form a second exposed region.

S18: forming a second doped region 21, a doping of the second doped region 21 and the first doped region 17, in a surface of the substrate 11 corresponding to the second exposed region, as shown in FIG. Different types. In the embodiment of the invention, the first doped region 17 is a drain region, and the second doped region 21 is a source region.

Optionally, a doping concentration of the source region is greater than a doping concentration of the drain region to increase an on current of the tunneling field effect transistor and reduce a leakage current of the tunneling field effect transistor.

It should be noted that, in the embodiment of the present invention, forming the second doped region 21 in the surface of the substrate 11 corresponding to the second exposed region may be performed directly on the portion of the substrate 11 corresponding to the second exposed region. The ion doping is formed, and the second exposed area corresponding to the surface of the substrate 11 may also be used first. The etch is performed to deposit a second doped layer to form a second doped region, which is not limited by the present invention, as the case may be.

Optionally, in the embodiment of the present invention, a lower surface of the second doped region 21 is flush with an upper surface of the first insulating structure 112, and an upper surface of the second doped region 21 is The upper surface of the first doped region 17 is flush, that is, in a direction perpendicular to the surface of the substrate 11, the depth of the first doped region 17 is the same as the depth of the second doped region 21.

It should be noted that, in the embodiment of the present invention, since the silicon substrate is a P-type silicon substrate, in the embodiment of the present invention, the second doped region 21 is P-type doped, the first A doped region 17 is N-type doped; in other embodiments of the present invention, the silicon substrate may be an N-type silicon substrate, and the second doped region 21 is N-type doped, The first doped region 17 is P-type doped, which is not limited by the present invention, as the case may be.

Specifically, in an embodiment of the present invention, when the second doped region 21 is P-type doped and the first doped region 17 is N-doped, the first doped region 17 For SiGe, the second doped region 21 is SiP or SiC; when the second doped region 21 is N-type doped, and the first doped region 17 is P-doped, the first The doped region 17 is SiP or SiC, and the second doped region 21 is SiGe, which is not limited in the present invention. Of course, in other embodiments of the present invention, the first doped region 17 and the Other dopant ions may also be used for the second doped region 21, as the case may be.

S19: removing the first spacer 14 and the first oxide layer 12 covered by the first spacer 14, forming a gate structure 25 on the surface of the substrate 11, the gate structure 25 and the drain The regions do not overlap and at least partially overlap the source region.

Specifically, in an embodiment of the present invention, the first spacer 14 is removed and the first a first oxide layer 12 covered by the spacers 14 forms a gate structure 25 on the surface of the substrate 11. The gate structure 25 does not overlap the drain region and at least partially overlaps the source region.

As shown in FIG. 14, a fifth cover layer 22 is formed on a side of the second doped region 21 facing away from the substrate 11, and the fifth cover layer 22 also covers the surface of the third cover layer 18, first The surface of the spacer 14 and the surface of the second spacer 151. It can be seen that in the embodiment of the invention, the width of the first spacer 14 directly affects the width of the gate structure 25 of the tunneling field effect transistor.

As shown in FIG. 15 , the fifth cover layer 22 is planarized until the surface of the first spacer 14 and the second spacer 151 are exposed; alternatively, the planarization process may be etching. The invention can be used for chemical mechanical polishing, and can also be used for etching and chemical mechanical polishing. The present invention is not limited thereto, and is specific.

As shown in FIG. 16, the first spacer 14 is removed to form a third recess 23, and the third recess 23 exposes a portion of the first oxide layer 12; optionally, in the embodiment of the present invention, When the first spacer 14 is silicon nitride, it is preferably removed using phosphoric acid.

As shown in FIG. 17, the first oxide layer 12 exposed by the third recess 23 is removed while a portion of the fifth cover layer 22 is removed to form a fourth recess 24, and the fourth recess 24 is The source regions are at least partially overlapped. Optionally, in the embodiment of the present invention, the first oxide layer 12 is removed by using hydrofluoric acid, and a portion of the fifth cladding layer 22 is removed to increase the fourth recess. The overlap region of the trench 24 with the source region increases the overlap region of the subsequently formed gate structure 25 and the source region. It should be noted that, in the embodiment of the present invention, the width of the first spacer 14 only constitutes a part of the width of the gate structure 25, and the area where the fifth cover layer 22 is etched together determines the The width of the gate structure 25 is not limited by the present invention. In other embodiments of the present invention, the width of the gate structure 25 can also be obtained only by setting the width of the first spacer 14 . That is the first room The width of the gap wall 14 is the width of the gate structure 25, which is not limited by the present invention, as the case may be.

It should be noted that, in the embodiment of the present invention, when the second spacer 151 is a silicon dioxide layer, the density of the second spacer 151 is greater than the first oxide layer 12 and the fifth The density of the cover layer 22 is such that the second spacer 151 is not removed when the first oxide layer 12 and the fifth cladding layer are secured, so that the subsequently formed gate structure 25 and the drain The areas do not overlap.

As shown in FIG. 18, a gate structure 25 is formed in the fourth recess 24.

As can be seen, in the embodiment of the present invention, the gate structure 25 at least partially overlaps the source region, the gate structure 25 and the drain region do not overlap, and the gate structure 25 and The non-overlapping area of the drain region is determined by the width of the second spacer 151.

It should be noted that, in the embodiment of the present invention, the larger the non-overlapping area of the gate structure 25 and the drain region, the smaller the leakage current of the tunneling field effect transistor; the gate structure 25 The larger the overlap area with the source region, the greater the electron mobility of the tunneling field effect transistor.

It should be noted that the method for fabricating the tunneling field effect transistor provided by the embodiment of the present invention further includes forming a subsequent metal wiring process such as a gate electrode, a source and a drain after forming the gate structure 25, The invention will not be described in detail herein.

The embodiment of the present invention provides another method for fabricating a tunneling field effect transistor. Unlike the above embodiment, in the embodiment of the present invention, the preset region is used to form a drain region. Specifically, as shown in FIG. 19, the manufacturing method includes:

S21: As shown in FIG. 20, a substrate 11 is provided, and a surface of the substrate 11 is formed with a first oxide layer 12.

In the embodiment of the present invention, the substrate 11 is a silicon substrate on an insulating substrate, and includes a silicon substrate 111 and a first insulating structure 112 on both sides of the silicon substrate 111, the first insulating structure 112 table The surface of the silicon substrate 111 may be lower than the surface of the silicon substrate 111. Alternatively, the silicon substrate 111 may be an intrinsic semiconductor substrate or a low-doped semiconductor substrate; when the silicon substrate 111 is lowly doped When the semiconductor substrate is used, the silicon substrate 111 may be a low-doped semiconductor substrate, or may be formed by ion doping in an intrinsic semiconductor, which is not limited by the present invention, as the case may be. set.

It should be noted that, in the embodiment of the present invention, the doping type of the silicon substrate 111 may be N-type doping or P-type doping, which is not limited by the present invention, as the case may be. set. Hereinafter, a method of fabricating a tunneling field effect transistor according to an embodiment of the present invention will be described by taking a silicon substrate in which the silicon substrate 111 is N-doped as an example.

S22: As shown in FIG. 21, a predetermined structure is formed on a side of the first oxide layer 12 facing away from the substrate 11, and the predetermined region is used to form a drain region.

Optionally, forming the spindle structure 13 on the surface of the first oxide layer 12 includes: forming a polysilicon layer 131 on a side of the first oxide layer 12 facing away from the substrate 11; and facing the polysilicon layer 131 away from the polysilicon layer Forming a first mask 132 on one side of the layer 131; etching the first mask 132 and the polysilicon layer 131 to retain the polysilicon layer 131 and the first mask layer located at the predetermined region 132, forming a spindle structure 13.

S23: as shown in Figure 22, forming a first spacer 14 on the side wall of the spindle structure 13;

S24: as shown in FIG. 23, removing the first oxide layer not covered by the main shaft structure and the first spacer, to form a first bare region;

S25: forming a first doped region 17 at a portion of the substrate corresponding to the first exposed region, using the spindle structure 13 and the first spacer 14 as a mask, as shown in FIG. The first doped region 17 is a source region. Optionally, the lower surface of the first doped region 17 is flush with the upper surface of the first insulating structure 112.

In the embodiment of the present invention, in the embodiment of the present invention, the first spacer wall 14 of the sidewall of the spindle structure 13 and the first spacer 14 of the main shaft structure 13 are used as a mask, and the substrate 11 corresponds to the first bare Forming the first doped region 17 in the surface of the region includes: engraving the first exposed region of the substrate 11 with the main structure 13 and the first spacer 14 of the sidewall of the main spindle structure 13 as a mask Etching, removing a portion of the substrate 11 corresponding to the first exposed region such that the substrate 11 corresponds to a surface at the first exposed region is lower than a surface of the substrate 11 corresponding to the predetermined region; a first doped layer is formed on a surface of the substrate 11 corresponding to the first exposed region, until A surface of the first doped layer facing away from the substrate 11 is flush with a surface at a predetermined region of the substrate 11 to form a first doped region 17 .

In another embodiment of the present invention, the main structure 13 and the first spacer 14 of the sidewall of the main shaft structure 13 are used as a mask to form a surface in the surface of the substrate 11 corresponding to the first bare region. a doped region 17 includes: ion-doping the portion of the substrate 11 corresponding to the first exposed region by using the main spindle structure 13 and the first spacer 14 of the sidewall of the main spindle structure 13 as a mask. The substrate 11 forms a first doped region 17 in a surface corresponding to the first exposed region.

S26: removing the spindle structure 13, exposing the predetermined area, forming a first recess 133;

Specifically, in an embodiment of the present invention, removing the spindle structure 13 and exposing the predetermined area to form the first recess 133 includes:

As shown in FIG. 25, a third cover layer 18 is formed on a side of the spindle structure 13 facing away from the substrate 11, and the third cover layer 18 completely covers the surface of the substrate 11 and the first doped region. 17 a surface, a surface of the spindle structure 13 and a surface of the first spacer 14 .

As shown in FIG. 26, the third cap layer 18 is planarized until the surface of the polysilicon layer 131 in the spindle structure 13 is exposed. The planarization of the third cap layer 18 may be performed by using an etching process, a chemical mechanical polishing process, or an etching process and a chemical mechanical polishing process. The invention is not limited thereto, as the case may be. And set.

As shown in FIG. 27, the polysilicon layer 131 in the spindle structure 13 is removed, and the portion of the first oxide layer 12 corresponding to the predetermined region is exposed to form a first recess 133; optionally, implemented in the present invention. In an example, the polysilicon layer 131 in the spindle structure 13 is removed by using an ammonia-containing solution (such as TMAN). However, the present invention is not limited thereto, and may be determined as the case may be.

S27: forming a third spacer 191 on a side of the first spacer 14 facing the first recess 133, and removing the first oxidation not covered by the first spacer 14 and the third spacer 191 a layer 12, forming a second exposed area on the surface of the substrate;

Specifically, in an embodiment of the present invention, a third spacer 191 is formed on a side of the first spacer 14 facing the first recess 133, and is removed from the first spacer 14 and The first oxide layer 12 covered by the three gap walls 191, forming a second exposed region on the surface of the substrate comprises:

As shown in FIG. 28, a fourth cover layer 19 is formed on the inner surface of the first recess 133, the fourth cover layer 19 completely covering the surface of the substrate 11, the surface of the first spacer 14 and the The surface of the third cover layer 18; preferably, the fourth cover layer 19 is a silicon dioxide layer.

As shown in FIG. 29, the fourth cap layer 19 is anisotropically etched until the fourth cap layer 19 and the first oxide layer 12 at the bottom of the first recess 133 are removed, leaving only the first The fourth cover layer 19 on the side wall of the recess 133 forms a third spacer 191 and a second recess 192. It should be noted that, in the embodiment of the present invention, when the fourth cover layer 19 is a silicon dioxide layer, during the isotropic etching of the fourth cover layer 19, the second concave The portion of the first oxide layer 12 exposed by the trench 192 is also removed together to form a second exposed region on the surface of the substrate.

S28: forming a second doped region 21, a doping type of the second doped region 21 and the first doped region 17, in a surface corresponding to the second exposed region of the substrate, as shown in FIG. Different, the second doped region 21 is a drain region;

S29: removing the first spacer 14 and the first oxide layer 12 covered by the first spacer 14 to form a gate structure 25 on the surface of the substrate, the gate structure 25 and the drain region Do not overlap and at least partially overlap the source region.

Specifically, in one embodiment of the present invention, the first spacer 14 and the first oxide layer 12 covered by the first spacer 14 are removed, and a gate structure 25 is formed on the surface of the substrate 11. The gate structure 25 does not overlap the drain region and at least partially overlaps the source region, including:

As shown in FIG. 31, a fifth cover layer 22 is formed on a side of the second doped region 21 facing away from the substrate 11, and the fifth cover layer 22 also covers the surface of the third cover layer 18, first The surface of the spacer 14 and the surface of the third spacer 191.

As shown in FIG. 32, the fifth cap layer 22 is planarized until the surface of the first spacer 14 and the third spacer 191 are exposed; alternatively, the planarization process may be etching. The invention can be used for chemical mechanical polishing, and can also be used for etching and chemical mechanical polishing. The present invention is not limited thereto, and is specific.

As shown in FIG. 33, the first spacer 14 is removed to form a third recess 23, and the third recess 23 exposes a portion of the first oxide layer 12; optionally, in the embodiment of the present invention, When the first spacer 14 is silicon nitride, it is preferably removed using phosphoric acid.

As shown in FIG. 34, the first oxide layer 12 exposed by the third recess 23 is removed while a portion of the fifth cover layer 22 is removed to form a fourth recess 24, and the fourth recess 24 is The source regions are at least partially overlapped. Optionally, in the embodiment of the present invention, the first oxide layer 12 is removed by using hydrofluoric acid, and a portion of the fifth cladding layer 22 is removed to increase the fourth recess. The overlap region of the trench 24 with the source region increases the overlap region of the subsequently formed gate structure 25 and the source region.

It should be noted that, in the embodiment of the present invention, when the third spacer 191 is a silicon dioxide layer, the density of the third spacer 191 is greater than the first oxide layer 12 and the fifth The density of the cover layer 22 is such that the third spacer 191 is not removed when the first oxide layer 12 and the fifth cladding layer are secured, so that the subsequently formed gate structure 25 and the drain The areas do not overlap.

As shown in FIG. 35, a gate structure 25 is formed in the fourth recess 24.

It should be noted that, in the above embodiment, an N-type tunneling field effect transistor or a P-type tunneling field effect transistor is fabricated by using the method of fabricating the tunneling field effect transistor as an example. In other embodiments of the present invention, the fabrication method provided by the embodiment of the present invention may simultaneously fabricate a plurality of P-type tunneling field effect transistors, or simultaneously fabricate a plurality of N-type tunneling field effect transistors, or simultaneously fabricate at least one The P-type tunneling field effect transistor and the at least one N-type tunneling field effect transistor are not limited in the present invention, as the case may be.

Since a plurality of P-type tunneling field effect transistors are fabricated by using the fabrication method, the process steps are substantially the same as those for fabricating a single P-type tunneling field effect transistor, and a plurality of N-type tunneling field effects are produced by the fabrication method. In the case of a transistor, the process steps are substantially the same as those in the process of fabricating a single N-type tunneling field effect transistor, and the present invention will not repeat the description.

Hereinafter, the above fabrication method will be described by taking a fabrication method to simultaneously fabricate a P-type tunneling field effect transistor and an N-type tunneling field effect transistor. It is to be noted that in the following embodiments, only the portions that are different from the above-described embodiments will be described, and the same portions will not be described again.

Specifically, in the embodiment of the present invention, as shown in FIG. 36, the method for fabricating the tunneling field effect transistor includes:

S31: As shown in FIG. 37, a substrate 11 is provided, and a surface of the substrate 11 is formed with a first oxide layer 12.

Specifically, in an embodiment of the present invention, in the embodiment of the present invention, the substrate 11 includes a silicon substrate 111 and a first insulating structure 112 on both sides of the silicon substrate 111, the silicon substrate 111 includes a P-type silicon substrate 113 and an N-type silicon substrate 114.

S32, as shown in FIG. 38, a spindle structure 13 is formed on a side of the first oxide layer 12 facing away from the substrate 11, and the preset area includes a first preset area and a second preset area. The first preset area is used to form a drain area, and the second preset area is used to form a source area.

In the following, the first predetermined area corresponds to the P-type silicon substrate, and the second predetermined area corresponds to the N-type silicon substrate as an example, and the manufacturing method provided by the embodiment of the present invention is described, but the present invention does not Limited, depending on the situation.

Optionally, in an embodiment of the present invention, forming the spindle structure 13 on the surface of the first oxide layer 12 includes: forming a polysilicon layer 131 on a side of the first oxide layer 12 facing away from the substrate 11; Forming a first mask 132 on a side of the polysilicon layer 131 away from the polysilicon layer 131; etching the first mask 132 and the polysilicon layer 131 to retain polysilicon located at the predetermined region Layer 131 and first mask 132 form a spindle structure 13.

S33: As shown in FIG. 39, a first spacer 14 is formed on the side wall of the spindle structure 13.

Specifically, in an embodiment of the present invention, a first space is formed on a sidewall of the spindle structure 13 The gap wall 14 includes:

S34: As shown in FIG. 40, a second spacer 151 is formed on a side of the first spacer 14 facing away from the spindle structure 13.

Forming a second cover layer on a side of the spindle structure 13 facing away from the substrate 11 , the second cover layer completely covering the surface of the spindle structure 13 , the surface of the first spacer 14 and the surface of the substrate 11 Performing isotropic etching on the second cover layer to remove the surface of the main spindle structure 13 and the second cover layer of the surface of the substrate 11, leaving the first spacer 14 away from the spindle structure 13 The second cover layer on the side forms a second spacer 151.

S35: As shown in FIG. 41, the first oxide layer 12 not covered by the spindle structure 13, the first spacer 14 and the second spacer 151 is removed to form a first exposed region.

S36: removing the second spacer 151 located on a side of the spindle structure 13 facing away from the drain region, and forming a first doping region 17 at a portion of the substrate 11 corresponding to the first exposed region.

Optionally, in an embodiment of the present invention, the second spacer 151 located on a side of the spindle structure 13 facing away from the drain region is removed, and the portion of the substrate 11 corresponding to the first bare region is removed. Forming the first doped region 17 includes:

As shown in FIG. 42, a second mask 16 is formed on a side of the spindle structure 13 facing away from the substrate 11, the second mask 16 covering the spindle structure 13 and being oriented toward the spindle structure 13. a first spacer and a second spacer on one side of the drain region, the second spacer of the spindle structure 13 facing away from the drain region is exposed; optionally, the second mask 16 is preferably a photoresist mask Membrane plate.

As shown in FIG. 43, using the second mask 16 as a mask, the second spacer 151 on the side of the spindle structure 13 facing away from the drain region is removed; and the second mask 16 is removed.

It should be noted that, in the embodiment of the present invention, the second spacer 151 located on the side of the spindle structure 13 facing away from the drain region is preferably a wet etching process, and the etching solution used may be hydrofluoric. The acid or a mixed solution of different ratios of hydrofluoric acid and water may also be dry etched, and the etching material may be CF ₃ or CF ₄ , which is not limited by the present invention, as the case may be. set.

As shown in FIG. 44, the first spacer 14 and the second spacer 151 of the sidewall structure 13 and the sidewall of the spindle structure 13 are used as a mask, and the substrate 11 corresponds to the surface of the first bare region. A first doped region 17 is formed. The lower surface of the first doped region 17 is flush with the upper surface of the first insulating structure 112.

On the basis of the above embodiments, in one embodiment of the present invention, the first spacer 14 and the second spacer 151 of the sidewall structure 13 and the sidewall of the spindle structure 13 are used as a mask. Forming the first doped region 17 in the surface of the substrate 11 corresponding to the first exposed region includes:

The first exposed region of the substrate 11 is etched by using the spindle structure 13 and the first spacer 14 and the second spacer 151 of the sidewall of the spindle structure 13 as a mask to remove the substrate Corresponding to the portion at the first exposed area, such that the surface of the substrate corresponding to the first exposed area is lower than the surface of the substrate corresponding to the predetermined area;

Forming a first doped layer on a surface of the substrate 11 corresponding to the first exposed region, until The surface of the first doped layer facing away from the substrate 11 is flush with the surface at the corresponding preset region of the substrate to form a first doped region 17.

In another embodiment of the present invention, the first spacer 14 and the second spacer 151 of the sidewall of the main shaft structure 13 and the main shaft structure 13 are used as a mask, and the substrate 11 corresponds to the first bare Forming the first doped region 17 in the surface of the region includes:

Ion-doping the portion of the substrate 11 corresponding to the first exposed region by using the spindle structure 13 and the first spacer 14 and the second spacer 151 of the sidewall of the spindle structure 13 as a mask. The substrate 11 forms a first doped region 17 in a surface corresponding to the first bare region.

Specifically, in an embodiment of the present invention, the first doped region 17 is formed on a portion of the substrate 11 corresponding to the first exposed region: the P-type silicon substrate 113 corresponds to the first A portion of the bare region forms a drain region 171 while a source region 172 is formed at a portion of the first exposed region corresponding to the N-type silicon substrate 114.

S37: removing the spindle structure 13 and the first oxide layer 12 covered by the spindle structure 13, exposing the predetermined region, and forming a second exposed region on the surface of the substrate 11.

As shown in FIG. 45, a third cover layer 18 is formed on the side of the spindle structure 13 facing away from the substrate 11, and the third cover layer 18 completely covers the surface of the substrate 11, the first doping. a surface of the region 17, a surface of the main spindle structure 13 and a surface of the first spacer 14 and the second spacer 151; the third cover layer 18 is further planarized until the polysilicon layer 131 in the spindle structure 13 is exposed s surface.

As shown in FIG. 46, the polysilicon layer 131 in the spindle structure 13 is removed, and a portion of the first oxide layer 12 corresponding to the predetermined region is exposed to form a first recess 133.

As shown in FIG. 47, a fourth cover layer 19 is formed on the inner surface of the first recess 133, and the fourth cover layer 19 completely covers the surface of the substrate 11, the surface of the first spacer 14 and the second a surface of the spacer 151 and a surface of the third cover layer 18;

As shown in FIG. 48, the fourth cap layer 19 is anisotropically etched until the fourth cap layer 19 and the first oxide layer 12 at the bottom of the first recess 133 are removed, leaving only the first A fourth cover layer 19 on the sidewall of the recess forms a third spacer 191 and a second recess 192.

As shown in FIG. 49, a third mask 20 is formed on a side of the third cover layer 18 facing away from the substrate 11, and the third mask 20 covers the second recess located corresponding to the first predetermined area. The slot 192 faces away from the third cover layer 18 and the first spacer 14 on the side of the drain region 171 and the second recess 192 corresponding to the second predetermined region and the third spacer 191 of the inner sidewall thereof, and the exposure corresponds to the A third spacer 191 of the inner sidewall of the second recess 192 of the P-type silicon substrate.

As shown in FIG. 50, the third spacer 191 on the inner sidewall of the second recess 192 corresponding to the first predetermined region and the first oxide layer 12 on the bottom thereof are removed by using the third mask 20 as a mask. Exposing the first predetermined area to form a second exposed area corresponding to the first preset area; and then removing the third mask 20 to form a second exposed area corresponding to the second preset area.

S38: forming a second doped region 21 in a surface of the substrate corresponding to the second exposed region, wherein a doping type of the second doped region and the first doped region is as shown in FIG. different. It should be noted that, in the embodiment of the present invention, the second doped region formed in the surface of the P-type silicon substrate is a source region of the P-type tunneling field effect transistor, and is formed in the surface of the N-type silicon substrate. The second doped region is a drain region of the N-type tunneling field effect transistor. It should also be noted that, in the embodiment of the present invention, The source and drain regions of the tunneling field effect transistor have the same doping concentration, but the invention is not limited thereto. In other embodiments of the invention, the source of the tunneling field effect transistor may also be made. The doping concentration is greater than the doping concentration of the drain region.

S39: removing the first spacer 14 and the first oxide layer 12 covered by the first spacer 14, forming a gate structure 25 on the surface of the substrate 11, the gate structure 25 and the drain The regions do not overlap and at least partially overlap the source region.

As shown in FIG. 52, a fifth cover layer 22 is formed on a side of the second doped region 21 facing away from the substrate 11, and the fifth cover layer 22 further covers the surface of the third cover layer 18, first a surface of the spacer 14 , a surface of the second spacer 151 and the third spacer 191; planarizing the fifth cover 22 until the surface of the first spacer 14 , the surface of the second spacer 151 , and the first The surface of the three gap walls 191.

It can be seen that in the embodiment of the invention, the width of the first spacer 14 directly affects the width of the gate structure 25 of the tunneling field effect transistor.

As shown in Figure 53, the first spacer 14 is removed to form a third recess 23, the third recess 23 exposes a portion of the first oxide layer 12;

As shown in FIG. 54, the first oxide layer 12 exposed by the third recess 23 is removed while a portion of the fifth cover layer 22 is removed to form a fourth recess 24, and the fourth recess 24 is The source regions at least partially overlap;

Optionally, in the embodiment of the present invention, the first oxide layer 12 is removed by using hydrofluoric acid, and at the same time A portion of the fifth cover layer 22 is removed to increase an overlap region of the fourth recess 24 with the source region, thereby increasing an overlap region of the subsequently formed gate structure 25 and the source region. It should be noted that, in the embodiment of the present invention, the width of the first spacer 14 only constitutes a part of the width of the gate structure 25, and the area where the fifth cover layer 22 is etched together determines the The width of the gate structure 25 is not limited by the present invention. In other embodiments of the present invention, the width of the gate structure 25 can also be obtained only by setting the width of the first spacer 14 . That is, the width of the first spacer 14 is the width of the gate structure 25, which is not limited by the present invention, as the case may be.

Similarly, when the third spacer 191 is a silicon dioxide layer, the density of the third spacer 191 is greater than the densities of the first oxide layer 12 and the fifth cladding layer 22 to When the first oxide layer 12 and the fifth cap layer are secured, the third spacer 191 is not removed, so that the subsequently formed gate structure 25 does not overlap the drain region.

As shown in FIG. 55, a gate structure 25 is formed in the fourth recess 24.

It can be seen that the fabrication method provided by the embodiment of the present invention can simultaneously fabricate an N-type tunneling field effect transistor and a P-type tunneling field effect transistor.

Correspondingly, an embodiment of the present invention further provides a tunneling field effect transistor, the tunneling field effect transistor comprising: a substrate: a gate structure on a surface of the substrate; and a relative arrangement in the surface of the substrate a source region and a drain region, wherein the gate structure does not overlap the drain region and at least partially overlaps the source region.

It should be noted that the tunneling field effect transistor provided in the embodiment of the present invention may be a planar semiconductor device, a fin semiconductor device, or a semiconductor device on an insulating substrate, and the present invention does not Limited, depending on the situation.

As described above, the embodiments of the present invention provide a method for fabricating a tunneling field effect transistor and a specific structure of a tunneling field effect transistor fabricated by the fabrication method. Moreover, the method for fabricating the tunneling field effect transistor provided by the embodiment of the present invention first defines a source region by using a spindle structure, and then forms a first spacer wall and a second spacer wall on both sides of the spindle structure, thereby utilizing the spindle structure and The first spacer wall and the second spacer wall serve as a mask to form a drain region; then the spindle structure is removed, a source region is formed at the spindle structure, and finally a gate structure is formed at the first spacer wall, thereby making the fabrication method in the formation source The regions and drain regions are not limited by the lithography process. In addition, in the manufacturing method of the tunneling field effect transistor provided by the embodiment of the present invention, the second spacer may be used to strictly control a non-overlapping region between the gate diode and the drain region to reduce the tunneling. A leakage current of the field effect transistor and an overlap region of the gate structure and the source region is used to increase an on current of the tunneling field effect transistor.

The various embodiments in the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but It is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

A method for fabricating a tunneling field effect transistor, comprising:

Providing a substrate having a first oxide layer formed on the surface thereof;

Forming a spindle structure on a side of the first oxide layer facing away from the substrate, the predetermined region for forming a source region;

Forming a first spacer on the sidewall of the spindle structure;

Forming a second spacer wall on a side of the first spacer wall facing away from the spindle structure;

Removing the first oxide layer not covered by the spindle structure, the first spacer and the second spacer to form a first exposed region;

Forming a first doped region in a portion of the substrate corresponding to the first exposed region, the first doped region being a drain region;

Removing the spindle structure and the first oxide layer covered by the spindle structure, exposing the predetermined region, and forming a second exposed region on the surface of the substrate;

Forming a second doped region in a surface of the substrate corresponding to the second exposed region, the second doped region is different from the doping type of the first doped region, and the second doped region is a source Area;

Removing the first spacer and a first oxide layer covered by the first spacer, forming a gate structure on a surface of the substrate, the gate structure not overlapping the drain region and The source areas at least partially overlap.
The method according to claim 1, wherein the source region has a doping concentration greater than a doping concentration of the drain region.
The method according to claim 1, wherein the forming process of the first oxide layer is an oxidation process; and the thickness of the first oxide layer ranges from 10 nm to 100 nm, inclusive.
The manufacturing method according to claim 1, wherein the forming the first spacer on the sidewall of the spindle structure comprises:

Forming a first cover layer on a side of the spindle structure facing away from the substrate, the first cover layer completely covering the surface of the spindle structure, the sidewall of the spindle structure, and the surface of the substrate; The cover layer is anisotropically etched to remove the first cover layer of the surface of the spindle structure and the surface of the substrate, and the first cover layer of the sidewall of the spindle structure is retained to form a first spacer.
The manufacturing method according to claim 1, wherein the forming the second spacer wall on a side of the first spacer wall facing away from the spindle structure comprises:

Forming a second cover layer on a side of the spindle structure facing away from the substrate, the second cover layer completely covering the surface of the spindle structure, the first spacer wall surface and the surface of the substrate;

Performing isotropic etching on the second cover layer to remove the surface of the main spindle structure and the second cover layer of the surface of the substrate, and retain a second cover of the first spacer wall away from the side of the spindle structure The layer forms a second spacer.
The method according to claim 1, wherein the forming the first doped region in the portion of the substrate corresponding to the first exposed region comprises:

Etching the first exposed region of the substrate with the first spindle structure and the second spacer wall of the sidewall of the spindle structure as a mask, and removing the substrate corresponding to the first a portion at the bare region such that a surface of the substrate corresponding to the first exposed region is lower than a surface of the substrate corresponding to the predetermined region;

Forming a first doped layer on a surface of the substrate corresponding to the first exposed region until a surface of the first doped layer facing away from the substrate is at a predetermined region corresponding to the substrate The surface is flush to form a first doped region.
The fabricating method according to claim 1, wherein the forming the first doped region in the surface of the substrate corresponding to the first bare region comprises: forming the first spindle region and the first sidewall of the spindle structure The spacer and the second spacer are masks, and the portion of the substrate corresponding to the first exposed region is ion doped, and the first doped region is formed in the surface of the substrate corresponding to the first exposed region.
The fabricating method according to claim 1, wherein the first spacer and the first oxide layer covered by the first spacer are removed, and a gate structure is formed on the surface of the substrate, the gate The pole structure does not overlap the drain region and at least partially overlaps the source region:

Forming a fifth cover layer on a side of the first doped region facing away from the substrate, the fifth cover layer further covering the fourth cover layer surface, the first gap wall surface and the second spacer wall surface;

Flattening the fifth cover layer until the first spacer wall surface and the second spacer wall surface are exposed;

Removing the first spacer, forming a third recess, the third recess exposing a portion of the first oxide layer;

Removing the first oxide layer exposed by the third groove while removing part of the fifth cover layer to form a fourth groove, the fourth groove at least partially overlapping the source region;

A gate structure is formed in the fourth recess.
The manufacturing method according to claim 8, wherein when the second spacer and the fifth cladding layer are silicon oxide layers, the second spacer has a density greater than the first oxide layer Densification of the second spacer; the density of the second spacer is greater than the density of the fifth cover.
A method for fabricating a tunneling field effect transistor, comprising:

Providing a substrate having a first oxide layer formed on the surface thereof;

Forming a spindle structure on a side of the first oxide layer facing away from the substrate; the predetermined region is used to form a drain region;

Forming a first spacer on the sidewall of the spindle structure;

Removing the first oxide layer not covered by the main shaft structure and the first spacer to form a first exposed area;

Forming a first doped region in a portion of the substrate corresponding to the first exposed region, the first doped region being a source region;

Removing the spindle structure, exposing the predetermined area to form a first groove;

Forming a third spacer on a side of the first spacer facing the first recess, and removing a first oxide layer not covered by the first spacer and the third spacer, on the substrate Forming a second exposed area on the surface;

Forming a second doped region in a surface of the substrate corresponding to the second exposed region, the second doped region is different from the doping type of the first doped region, and the second doped region is a drain Area;

Removing the first spacer and a first oxide layer covered by the first spacer, forming a gate structure on a surface of the substrate, the gate structure not overlapping the drain region and The source areas at least partially overlap.
The method according to claim 10, wherein the doping concentration of the source region is greater than the doping concentration of the drain region.
The method according to claim 10, wherein the forming process of the first oxide layer is an oxidation process; and the thickness of the first oxide layer ranges from 10 nm to 100 nm, inclusive.
The manufacturing method according to claim 10, wherein forming the first spacer on the sidewall of the spindle structure comprises:

Forming a first cover layer on a side of the spindle structure facing away from the substrate, the first cover layer completely covering the surface of the spindle structure, the sidewall of the spindle structure, and the surface of the substrate; The cover layer is anisotropically etched to remove the first cover layer of the surface of the spindle structure and the surface of the substrate, and the first cover layer of the sidewall of the spindle structure is retained to form a first spacer.
The method according to claim 10, wherein forming the first doped region in the portion of the substrate corresponding to the first exposed region comprises:

Etching the first exposed region of the substrate with the spindle structure and the first spacer of the sidewall of the spindle structure as a mask to remove a portion of the substrate corresponding to the first exposed region The surface of the substrate corresponding to the first exposed area is lower than the surface of the substrate corresponding to the predetermined area;

Forming a first doped layer on a surface of the substrate corresponding to the first exposed region until a surface of the first doped layer facing away from the substrate is at a predetermined region corresponding to the substrate The surface is flush to form a first doped region.
The manufacturing method according to claim 10, wherein forming the first doped region in the surface of the substrate corresponding to the first bare region comprises: forming the first spindle region and the first sidewall of the spindle structure The spacer is a mask, and a portion of the substrate corresponding to the first exposed region is ion-doped, and a first doped region is formed in a surface of the substrate corresponding to the first exposed region.
The manufacturing method according to claim 10, wherein removing the spindle structure and exposing the preset area comprises:

Forming a third cover layer on the surface of the first doped region, the third cover layer, the first doped region, the first spacer, and the spindle structure;

Flattening the third cover layer until the polysilicon layer in the spindle structure is exposed surface;

The polysilicon layer is removed, and the predetermined area is exposed to form a first recess.
The manufacturing method according to claim 10, wherein a third spacer is formed on a side of the first spacer facing the first recess, and is removed from the first spacer and the third The first oxide layer covered by the spacer, forming a second exposed region on the surface of the substrate comprises:

Forming a fourth cover layer on a side of the first spacer wall facing the first groove, the fourth cover layer completely covering the substrate, the first spacer, and the first doped region ;

Performing isotropic etching on the fourth cover layer to remove the substrate, the first spacer, and the fourth cover layer above the first doped region, leaving only the first spacer facing a fourth covering layer on one side of the first groove, forming a third gap wall;

The first oxide layer not covered by the first spacer and the third spacer is removed.
The fabricating method according to claim 10, wherein the first spacer and the first oxide layer covered by the first spacer are removed, and a gate structure is formed on the surface of the substrate, the gate The pole structure does not overlap the drain region and at least partially overlaps the source region:

Forming a fifth cover layer on a side of the second doped region facing away from the substrate, the fifth cover layer further covering the fourth cover layer surface, the first gap wall surface and the third gap wall surface;

Flattening the fifth cover layer until the first spacer wall surface and the third spacer wall surface are exposed;

Removing the first spacer, forming a third recess, the third recess exposing a portion of the first oxide layer;

Removing the first oxide layer exposed by the third groove while removing part of the fifth cover layer to form a fourth groove, the fourth groove at least partially overlapping the source region;

A gate structure is formed in the fourth recess.
The manufacturing method according to claim 18, wherein when the third spacer and the fifth cover layer are silicon oxide layers, the third spacer has a density greater than the first oxide layer Densification of the third spacer; the density of the third spacer is greater than the density of the fifth cover.
A method for fabricating a tunneling field effect transistor, comprising:

Providing a substrate having a first oxide layer formed on the surface thereof;

Forming a spindle structure on a side of the first oxide layer facing away from the substrate, the predetermined area including a first preset area and a second preset area, wherein the first preset area is used for Forming a drain region, the second predetermined region being used to form a source region;

Forming a first spacer on the sidewall of the spindle structure;

Forming a second spacer wall on a side of the first spacer wall facing away from the spindle structure;

Removing the first oxide layer not covered by the spindle structure, the first spacer and the second spacer to form a first exposed region;

Removing a second spacer located on a side of the first spacer facing away from the drain region, and forming a first doped region at a portion of the substrate corresponding to the first exposed region;

Removing the spindle structure and the first oxide layer covered by the spindle structure, exposing the predetermined region, and forming a second exposed region on the surface of the substrate;

Forming a second doped region in a surface of the substrate corresponding to the second exposed region, wherein the doping type of the second doped region and the first doped region are different;

Removing the first spacer and a first oxide layer covered by the first spacer, forming a gate structure on a surface of the substrate, the gate structure not overlapping the drain region and The source areas at least partially overlap.
The method according to claim 20, wherein the source region has a doping concentration equal to or greater than a doping concentration of the drain region.
The method according to claim 20, wherein the forming process of the first oxide layer is an oxidation process; and the thickness of the first oxide layer ranges from 10 nm to 100 nm, inclusive.
The manufacturing method according to claim 20, wherein forming the first spacer on the sidewall of the spindle structure comprises:

Forming a first cover layer on a side of the spindle structure facing away from the substrate, the first cover layer completely covering the surface of the spindle structure, the sidewall of the spindle structure, and the surface of the substrate; The cover layer is anisotropically etched to remove the first cover layer of the surface of the spindle structure and the surface of the substrate, and the first cover layer of the sidewall of the spindle structure is retained to form a first spacer.
The manufacturing method according to claim 20, wherein forming the second spacer wall on a side of the first spacer wall facing away from the spindle structure comprises:

Forming a second cover layer on a side of the spindle structure facing away from the substrate, the second cover layer completely covering the surface of the spindle structure, the first spacer wall surface and the surface of the substrate;

Performing isotropic etching on the second cover layer to remove the surface of the main spindle structure and the second cover layer of the surface of the substrate, and retain a second cover of the first spacer wall away from the side of the spindle structure The layer forms a second spacer.
The manufacturing method according to claim 20, wherein the second spacer wall located on a side of the first spacer wall facing away from the drain region is removed, and a portion of the substrate corresponding to the first bare region is formed. The first doped region includes:

Forming a second mask on a side of the spindle structure facing away from the substrate, the second mask covering The main shaft structure and the first gap wall and the second gap wall on the side of the main shaft structure facing the drain area, and the second gap wall on the side of the main shaft structure facing away from the drain area is exposed;

Using the second mask as a mask, removing a second spacer located on a side of the spindle structure facing away from the drain region;

Removing the second mask;

Forming a first doped region in a surface of the substrate corresponding to the first bare region by using the main shaft structure and the first and second spacers of the sidewall of the main shaft structure as a mask.
The manufacturing method according to claim 25, wherein the first spacer wall and the second spacer wall of the main shaft structure and the side wall of the main shaft structure are used as a mask, and the first bare area is corresponding to the substrate Forming the first doped region in the surface includes:

Etching the first exposed region of the substrate with the first spindle structure and the second spacer wall of the sidewall of the spindle structure as a mask, and removing the substrate corresponding to the first a portion at the bare region such that a surface of the substrate corresponding to the first exposed region is lower than a surface of the substrate corresponding to the predetermined region;

Forming a first doped layer on a surface of the substrate corresponding to the first exposed region until a surface of the first doped layer facing away from the substrate is at a predetermined region corresponding to the substrate The surface is flush to form a first doped region.
The manufacturing method according to claim 25, wherein the first spacer wall and the second spacer wall of the main shaft structure and the side wall of the main shaft structure are used as a mask, and the first bare area is corresponding to the substrate Forming the first doped region in the surface includes:

And ion-doping the portion of the substrate corresponding to the first exposed region by using the main shaft structure and the first and second spacers of the sidewall of the main shaft structure as a mask, where the substrate is corresponding to the substrate Description A first doped region is formed in a surface of the first bare region.
The fabricating method according to claim 20, wherein the first spacer and the first oxide layer covered by the first spacer are removed, and a gate structure is formed on the surface of the substrate, the gate The pole structure does not overlap the drain region and at least partially overlaps the source region:

Forming a fifth cover layer on a side of the second doped region facing away from the substrate, the fifth cover layer further covering the third cover layer surface, the first spacer wall surface, the second spacer wall, and the third layer Gap surface;

Flattening the fifth cover layer until the first spacer wall surface, the second spacer wall surface, and the third spacer wall surface are exposed;

Removing the first spacer, forming a third recess, the third recess exposing a portion of the first oxide layer;

Removing the first oxide layer exposed by the third groove while removing part of the fifth cover layer to form a fourth groove, the fourth groove at least partially overlapping the source region;

A gate structure is formed in the fourth recess.
The manufacturing method according to claim 28, wherein when the second spacer is a silicon dioxide layer, the second spacer has a density greater than the first oxide layer and the fifth cover Density of the layer;

When the third spacer is a silicon dioxide layer, the density of the third spacer is greater than the density of the first oxide layer and the fifth cover layer.
A tunneling field effect transistor, comprising:

Substrate:

a gate structure on a surface of the substrate;

Located in the surface of the substrate, oppositely disposed source and drain regions, wherein the gate structure and the gate The drain regions do not overlap and at least partially overlap the source region.