CN104517857A - Integrated circuit devices including finfets and methods of forming the same - Google Patents

Integrated circuit devices including finfets and methods of forming the same Download PDF

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Publication number
CN104517857A
CN104517857A CN201410505130.0A CN201410505130A CN104517857A CN 104517857 A CN104517857 A CN 104517857A CN 201410505130 A CN201410505130 A CN 201410505130A CN 104517857 A CN104517857 A CN 104517857A
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China
Prior art keywords
channel region
barrier layer
source
drain region
sidewall
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CN201410505130.0A
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CN104517857B (en
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B.J.奥布拉多维克
R.C.鲍恩
M.S.罗德
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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Abstract

Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SixGe1-x, and x may be in a range of about 0.05 to about 0.2.

Description

Integrated circuit (IC)-components comprising fin-shaped field effect transistor and forming method thereof
Technical field
The disclosure generally relates to electronic applications, more specifically, relates to the method forming integrated circuit (IC)-components.
Background technology
Developed comprise pure germanium raceway groove FinFET (fin-shaped field effect transistor) to improve carrier mobility.But due to interband tunnelling (band-to-band tunneling, BTBT) electric current larger in drain region, pure germanium raceway groove can have the leakage current higher than silicon raceway groove.The direct band gap in silicon is less than, so interband tunnelling current can than larger in silicon in germanium due to the direct band gap in germanium.
Summary of the invention
A kind of method of finFET of being formed can comprise: on substrate, form the fin-shaped channel district comprising germanium; And on substrate, form the source/drain region of contiguous channel region.The method can also comprise the barrier layer forming the contact sidewall of channel region and the sidewall of source/drain region.Barrier layer can comprise Si xge 1-x, the value of x can in the scope of about 0.05 to about 0.2.
According to each embodiment, the germanium concentration in channel region can be greater than the germanium concentration in barrier layer.
In various embodiments, formation channel region can comprise formation and comprise Si 1-yge ychannel region, form source/drain region and can comprise and form the part comprising pure germanium substantially of source/drain region.The value of y can in the scope of about 0.8 to about 1.According to each embodiment, the germanium concentration in channel region can be greater than the germanium concentration in barrier layer, and the germanium concentration in source/drain region can be substantially equal to or be greater than the germanium concentration in barrier layer.According to each embodiment, the method can also comprise the contact zone of the upper surface forming contact source/drain region, and the part comprising pure germanium substantially of source/drain region can contact contact zone.
In various embodiments, formation channel region can comprise formation and comprise Si 1-yge yraceway groove, form source/drain region and can comprise and form the part comprising pure silicon substantially of source/drain region.The value of y can in the scope of about 0.85 to about 1.According to each embodiment, the germanium concentration in channel region can be greater than the germanium concentration in barrier layer.According to each embodiment, the method can also comprise the contact zone of the upper surface forming contact source/drain region, and the part comprising pure silicon substantially of source/drain region can contact contact zone.
According to each embodiment, formation channel region and barrier layer can comprise: on substrate, form original trench district; Original trench district forms mask pattern; Use mask pattern as etching mask etching original trench district to form channel region; Then use channel region as seed layer epitaxial growth barrier layer.
In various embodiments, form mask pattern can be included in and original trench district formed the first mask pattern and form spacer patterns in the opposing sidewalls of the first mask pattern.
In various embodiments, etch original trench district can comprise etching original trench district until original trench district by the degree of depth of etching part arrive desired depth.
According to each embodiment, formation channel region and barrier layer can comprise: on substrate, form original trench district; The Part I in original trench district is formed the first mask pattern; The first mask pattern is used to stop that mask injects silicon ion to original trench district as injection; On the Part I in original trench district, the second mask pattern is formed after injection silicon ion; Then the second mask pattern is used as etching mask etching original trench district to form channel region and barrier layer.
In various embodiments, formed in opposing sidewalls that the second mask pattern can be included in the first mask pattern and form spacer patterns.
According to each embodiment, form source/drain region and can comprise use barrier layer as seed layer epitaxial growth source/drain region.
According to each embodiment, the first source/drain region that formation source/drain region can comprise the first side wall forming contiguous channel region makes barrier layer can contact the first side wall of channel region and the sidewall of the first source/drain region.The method can also comprise formation second source/drain region, second sidewall contrary with the first side wall of this channel region of the second source/drain region contact channel region.
In various embodiments, the method can also comprise the contact zone of the upper surface forming contact source/drain region.
According to each embodiment, the width of barrier layer on the direction from channel region to source/drain region can be about 10nm.
According to each embodiment, the method can also comprise and forms gate electrode over the channel region, barrier layer can be substantially aligned at the sidewall of gate electrode with the sidewall of the sidewall contact of channel region, knot can be formed in barrier layer.
The method forming finFET device can comprise: on substrate, form the fin-shaped channel district comprising germanium; Substrate forms source/drain region on the sidewall of channel region; And barrier layer is formed between the sidewall and the sidewall of source/drain region of channel region.Barrier layer can comprise silicon and germanium, and the germanium concentration in barrier layer can be less than the germanium concentration in channel region.
According to each embodiment, formation barrier layer can comprise formation and comprise Si xge 1-xbarrier layer, the value of x can in the scope of about 0.05 to about 0.2.
According to each embodiment, formation channel region and barrier layer can comprise: on substrate, form original trench district; Original trench district forms mask pattern; Use mask pattern as etching mask etching original trench district to form channel region; Then use channel region as seed layer epitaxial growth barrier layer.
In various embodiments, form mask pattern can be included in and original trench district formed the first mask pattern and form spacer patterns in the opposing sidewalls of the first mask pattern.
According to each embodiment, formation channel region and barrier layer can comprise: on substrate, form original trench district; The Part I in original trench district is formed the first mask pattern; The first mask pattern is used to stop that mask injects silicon ion to original trench district as injection; In original trench district, the second mask pattern is formed after injection silicon ion; Then the second mask pattern is used as etching mask etching original trench district to form channel region and barrier layer.
In various embodiments, formed in opposing sidewalls that the second mask pattern can be included in the first mask pattern and form spacer patterns.
According to each embodiment, formation channel region can comprise formation and comprise Si 1-yge ychannel region, form source/drain region and can comprise and form the part comprising pure germanium substantially of source/drain region.The value of y can in the scope of about 0.8 to about 1.In various embodiments, the method can also comprise the contact zone of the upper surface forming contact source/drain region, and the part comprising pure germanium substantially of source/drain region can contact contact zone.In various embodiments, the germanium concentration in channel region can be greater than the germanium concentration in barrier layer, and the germanium concentration in source/drain region can be substantially equal to or be greater than the germanium concentration in barrier layer.FinFET can be P type finFET.
According to each embodiment, formation channel region can comprise formation and comprise Si 1-yge ychannel region, form source/drain region and can comprise and form the part comprising pure silicon substantially of source/drain region.The value of y can in the scope of about 0.85 to about 1.In various embodiments, the method can also comprise the contact zone of the upper surface forming contact source/drain region, and the part comprising pure silicon substantially of source/drain region can contact contact zone.In various embodiments, the germanium concentration in channel region can be greater than the germanium concentration in barrier layer.FinFET can be N-type finFET.
In various embodiments, formed and the first side wall that source/drain region can be included in channel region forms the first source/drain region barrier layer can be arranged between the first side wall of channel region and the sidewall of the first source/drain region.The method can also comprise the second source/drain region of second sidewall contrary with the first side wall of channel region forming contact channel region, and barrier layer can not be arranged between the second sidewall of channel region and the second source/drain region.
According to each embodiment, the width of barrier layer on the direction from channel region to source/drain region can be about 10nm.
In various embodiments, the method can also comprise and forms gate electrode over the channel region, and the sidewall of the sidewall in the face of channel region on barrier layer can be substantially aligned at the sidewall of gate electrode, and knot can be formed in barrier layer.
The integrated circuit (IC)-components comprising finFET can be included in the fin-shaped channel district comprising germanium on substrate, the source/drain region of contiguous channel region and the barrier layer of the contact sidewall of channel region and the sidewall of source/drain region on substrate.Barrier layer can comprise Si xge 1-x, the value of x can in the scope of about 0.05 to about 0.2.
According to each embodiment, the germanium concentration in channel region can be greater than the germanium concentration in barrier layer.
In various embodiments, channel region can comprise Si 1-yge y, source/drain region can comprise the part substantially comprising pure germanium.The value of y can in the scope of about 0.8 to about 1.Germanium concentration in channel region can be greater than the germanium concentration in barrier layer, and the germanium concentration in source/drain region can be substantially equal to or be greater than the germanium concentration in barrier layer.According to each embodiment, the method can also comprise the contact zone of the upper surface forming contact source/drain region, and the part comprising pure germanium substantially of source/drain region can contact contact zone.
In various embodiments, this channel region can comprise Si 1-yge y, and the value of y can in the scope of about 0.85 to about 1.Source/drain region can comprise the part substantially comprising pure silicon.Germanium concentration in channel region can be greater than the germanium concentration in barrier layer.According to each embodiment, the method can also comprise the contact zone of the upper surface forming contact source/drain region.The part comprising pure silicon substantially of source/drain region can contact contact zone.
In various embodiments, the sidewall on the contact barrier layer of channel region can comprise the first side wall of channel region.Source/drain region can comprise the first source/drain region and make barrier layer can contact the first side wall of channel region and the sidewall of the first source/drain region.This device can also comprise the second source/drain region, second sidewall contrary with the first side wall of channel region of the second source/drain region contact channel region.
According to each embodiment, the width of barrier layer on the direction from channel region to source/drain region can be about 10nm.
In various embodiments, this device can also comprise gate electrode over the channel region, barrier layer can be substantially aligned at the sidewall of gate electrode with the sidewall of the sidewall contact of channel region, knot can be formed in barrier layer.
Accompanying drawing explanation
Fig. 1 is the perspective view of the integrated circuit (IC)-components of some embodiments illustrated according to the present invention's design.
Fig. 2 is the sectional view intercepted along the line A-A' of Fig. 1, and the integrated circuit (IC)-components of some embodiments according to the present invention's design is shown.
Fig. 3 is the sectional view intercepted along the line A-A' of Fig. 1, and the integrated circuit (IC)-components of some embodiments according to the present invention's design is shown.
Fig. 4 is the perspective view of the integrated circuit (IC)-components of some embodiments illustrated according to the present invention's design.
Fig. 5 to Fig. 6 is the perspective view of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components that some embodiments be provided as according to the present invention's design are shown.
Fig. 7 is the sectional view intercepted along the line B-B' of Fig. 6, and the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some embodiments be provided as according to the present invention's design is shown.
Fig. 8 to Figure 10 is the sectional view intercepted along the line B-B' of Fig. 6, and the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some embodiments be provided as according to the present invention's design is shown.
Figure 11 to Figure 13 is the sectional view intercepted along the line B-B' of Fig. 6, and the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some embodiments be provided as according to the present invention's design is shown.
Embodiment
With reference to the accompanying drawings example embodiment is described.Many different forms and embodiment can exist, and do not deviate from spirit of the present disclosure and instruction, so the disclosure should not be construed as limited to the example embodiment set forth here.But, provide these example embodiment to make the disclosure thoroughly with complete, and the scope of the present disclosure will be conveyed to those skilled in the art.In the accompanying drawings, in order to clear, the size in layer and region and relative size can be exaggerated.Identical Reference numeral refers to identical element all the time.
Here describe the example embodiment of the present invention's design with reference to sectional view or perspective view, these figure are the schematic diagram of the intermediate structure of idealized embodiments and example embodiment.Thus, the change of the diagram shape caused by such as manufacturing technology and/or tolerance is contingent.Therefore, the example embodiment of the present invention's design should not be construed as limited to the given shape in shown here region, but comprises by such as manufacturing the form variations caused.
Unless otherwise defined, the same implication usually understood of all terms used herein (comprising technical term and the scientific terminology) those of ordinary skill all had in field belonging to the present invention.It will also be understood that, the term defined in such as universaling dictionary, unless clearly defined, otherwise should be interpreted as having the consistent implication of implication with them in the linguistic context of association area here, and should not be interpreted as Utopian or excessive formal meaning.
Terminology used here is only the object in order to describe specific embodiment, is not intended to limit embodiment.As used herein, clearly state unless context separately has, otherwise singulative " " and " being somebody's turn to do " are also intended to comprise plural form.It will also be understood that, term " comprises " and/or " comprising ", when using in this manual, specify the existence of described feature, step, operation, element and/or assembly, but do not get rid of other features one or more, step, operation, element, the existence of assembly and/or its combination or increase.
To understand, when title element " be connected to ", " being connected to " or " in response to " another element or another element " on ", time, it can directly be connected to, be connected to or in response to another element or directly on another element, or can also there is the element of insertion.On the contrary, when title element " be directly connected to ", " being directly connected to " or " corresponding directly to " another element or " directly " another element " on " time, there is not the element of insertion.As used herein, term "and/or" comprises any and all combinations of one or more listed relevant item.
To understand, although first, second grade of term can be used here to describe various element, these elements should not be subject to the restriction of these terms.These terms are only for differentiating an element and another element.Therefore, the first element discussed below can be called as the second element and not deviate from the instruction of present example.
Here can use such as ease of describing " ... under ", " ... below ", D score, " ... on ", " on " etc. spatial relationship term to describe the relation between an element as shown in drawings or feature and another (a bit) element or feature.To understand, spatial relationship term is used to summarize device different orientation in use or operation except orientation shown in accompanying drawing.Such as, if the device in accompanying drawing turns, be described to " " element of other elements or feature " under " or " below " will in " top " of other elements or feature.Therefore, exemplary term " ... below " just can contain on and under two kinds of orientations.Device can additionally orientation (90-degree rotation or in other orientations), and spatial relation description symbol used here does respective explanations.
Due to the higher leakage currents in drain region, use that pure germanium raceway groove can not as was expected improves device performance.As present inventor understands, add silicon and can increase direct band gap to (such as, making germanium and alloying with silicon) in germanium and reduce the leakage current in drain region.The method comprising the integrated circuit (IC)-components of fin-shaped field effect transistor (FinFET) according to the formation of each embodiment of the present invention's design can comprise and is optionally being arranged at the barrier layer being formed in the tunnel region between channel region and drain region and comprise germanium and silicon.
Fig. 1 is the perspective view of integrated circuit (IC)-components of some embodiments illustrated according to the present invention's design, and Fig. 2 is the sectional view intercepted along the line A-A' of Fig. 1, and the integrated circuit (IC)-components of some embodiments conceived according to the present invention is shown.Line A-A' extends in the X direction.
See figures.1.and.2, the separator 110 that integrated circuit (IC)-components can comprise substrate 100 and be arranged on substrate.Integrated circuit (IC)-components can also comprise the channel region 120 with fin-shaped, and channel region 120 can on the substrate 100 and partly in separator 110.Channel region 120 can comprise germanium (Ge).To understand, channel region 120 can by Si 1-yge ycomposition, and the value of y can be determined according to the proper level of stress.
In certain embodiments, channel region 120 can by Si 1-yge ycomposition, and when channel region 120 is channel regions of N-type transistor, the value of y can be about 0.85 or larger.In the embodiment that some substitute, the value of y can be about 0.9 or larger.In the embodiment that some substitute, when channel region 120 is the channel regions for the N-type transistor of high carrier mobility, channel region 120 can be made up of pure germanium (that is, the value of y is about 1) substantially.In certain embodiments, channel region 120 can by Si 1-yge ycomposition, and when channel region 120 is channel regions of P-type crystal pipe, the value of y can be about 0.8 or larger.In the embodiment that some substitute, the value of y can be about 0.9 or larger.
Substrate 100 can comprise one or more semi-conducting materials, such as Si, Ge, SiGe, GaAs or SiGeC.In certain embodiments, substrate 100 can be body silicon substrate or semiconductor-on-insulator (SOI) substrate.Separator 110 such as can comprise insulating material such as Si oxide.
Grid 240 can be formed on channel region 120.Grid 240 can comprise gate insulation layer 236 and gate electrode 238.In certain embodiments, gate insulation layer 236 can comprise the high-g value with the dielectric constant higher than Si oxide, such as such as hafnium oxide (HfO 2), lanthanum-oxides (La 2o 3), Zirconium oxide (ZrO 2) and tantalum pentoxide (Ta 2o 5).Gate insulation layer 236 can use such as ald (ALD) technique to be conformally formed on the sidewall and basal surface of gate electrode 238.
In certain embodiments, gate electrode 238 can comprise sequentially stacking first grid electrode and second gate electrode.Such as, first grid electrode can comprise the one in TiN, TaN, TiC and TaC, and the second electrode can comprise W or Al.
According to Fig. 2, barrier layer 140 can be arranged on the sidewall of channel region 120.Barrier layer 140 can contact the sidewall of channel region 120.Barrier layer 140 can comprise two barrier layers 140 be arranged in the corresponding opposing sidewalls of channel region 120.In certain embodiments, each barrier layer 140 can be included in the horizontal component that the upper surface of substrate 100 extends, as shown in Figure 2.Barrier layer 140 can comprise Si xge 1-x, x can in the scope of about 0.05 to about 0.2.Therefore, the germanium concentration in barrier layer 140 can be less than the germanium concentration in channel region 120.
The width on barrier layer 140 can usually at the order of magnitude of 10nm, and in certain embodiments, the width on barrier layer 140 can be about 10nm.To understand, the width on barrier layer 140 refers to the thickness in the X-direction shown in Figure 1 of barrier layer 140.In certain embodiments, part that is that barrier layer 140 can comprise undoped and/or doping, the part of this doping can comprise such as the boron (B) of P type finFET and for the phosphorus (P) of N-type finFET or arsenic (As) as dopant.In certain embodiments, tie and outside edge that (such as, PN junction) can be formed in gate electrode 238, to make knot can not laterally overlapping gate electrode 238.Knot can be formed in barrier layer 140.In the embodiment that some substitute, within the edge that knot can be formed in gate electrode 238, make gate electrode 238 can laterally overlapping knot.The position of duct ligation is not how, and the embodiment reducing interband tunnelling current can comprise barrier layer 140, and barrier layer 140 comprises the alloy of germanium and silicon.Although Fig. 2 illustrates that the sidewall on barrier layer 140 is aligned the sidewall of the gate insulation layer 236 in Fig. 2, in certain embodiments, the sidewall on barrier layer 140 can in alignment with the sidewall of gate electrode 238.
In certain embodiments, the horizontal component of channel region 120 can extend between the upper surface of substrate 100 and the horizontal component on barrier layer 140, as shown in Figure 2.But in certain embodiments, channel region 120 can not comprise horizontal component, therefore barrier layer 140 can the upper surface of contact substrate 100.
The contact zone 180 that integrated circuit (IC)-components can also comprise the source/drain region 160 on the sidewall being arranged on barrier layer 140 and be arranged in source/drain region 160.Therefore, barrier layer 140 can be arranged in the tunnelling region between channel region 120 and source/drain region 160.Contact zone 180 can contact the upper surface of source/drain region 160.Barrier layer 140 can contact the sidewall of channel region 120 and the sidewall of source/drain region 160.Contact zone 180 can contact conductive layer, and source/drain region 160 is electrically connected to all parts of integrated circuit (IC)-components by this conductive layer, such as bit line or capacitor.Conductive layer can comprise metal or metal alloy.
To understand, when source/drain region 160 is in N-type transistor, source/drain region 160 can be included in the part comprising pure silicon substantially near contact zone 180; When source/drain region 160 is in P-type crystal pipe, source/drain region 160 can be included in the part comprising pure germanium substantially near contact zone 180.Therefore, the germanium concentration had in channel region 120, barrier layer 140 and source/drain region 160 according to the N-type transistor of some embodiments of the present invention's design can reduce along from channel region 120 to the direction of source/drain region 160.The germanium concentration in the channel region larger than the germanium concentration in barrier layer can be had and the germanium concentration that can have being substantially equal to or be greater than in the source/drain region of the germanium concentration in barrier layer according to the P-type crystal pipe of some embodiments of the present invention's design.In certain embodiments, in N-type transistor, the part comprising pure silicon substantially of source/drain region 160 can contact contact zone 180, and in P-type crystal pipe, the part comprising pure germanium substantially of source/drain region 160 can contact contact zone 180.
Fig. 3 is the sectional view intercepted along the line A-A' of Fig. 1, and the integrated circuit (IC)-components of some embodiments according to the present invention's design is shown.With reference to Fig. 3, integrated circuit (IC)-components can comprise be arranged on channel region 120 the first side wall on a barrier layer 140.Therefore, the source/drain region 160 of the second sidewall of contiguous channel region 120 can contact the second sidewall of channel region 120, and the second sidewall of channel region 120 is contrary with the first side wall of channel region 120.In other words, in certain embodiments, barrier layer 140 can on only in the sidewall of channel region 120, and therefore integrated circuit (IC)-components can have asymmetric structure.
Fig. 4 is the perspective view of the integrated circuit (IC)-components of some embodiments illustrated according to the present invention's design.With reference to Fig. 4, bury separator 112 and can arrange on the substrate 100, channel region 120 can be arranged on bury separator 112 upper surface on.Bury separator 112 can be plugged between substrate 100 and channel region 120.To understand, channel region 120 can use SOI manufacturing process to be formed, such as wafer bonding process.
Fig. 5 and Fig. 6 is the perspective view of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components that some embodiments be provided as according to the present invention's design are shown.Fig. 7 is the sectional view intercepted along the line B-B' of Fig. 6, and the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some embodiments be provided as according to the present invention's design is shown.With reference to Fig. 5, separator 110 and original trench district 118 can be formed on the substrate 100.The bottom in original trench district 118 can in separator 110, and the opposing sidewalls in original trench district 118 can contact seal 110.Original trench district 118 can have extend in the X direction linear.In certain embodiments, original trench district 118 can utilize substrate 100 to use epitaxial growth technology to be formed as seed layer.
According to Fig. 6 and Fig. 7, initial gate 220 can be formed in original trench district 118.Initial gate 220 can have extend in the Y-direction being substantially perpendicular to X-direction linear.Therefore, initial gate 220 can stride across original trench district 118.Initial gate 220 can comprise initial gate insulation layer 214, initial gate electrode 216 and mask pattern 218.Such as, initial gate insulation layer 214 can comprise oxide, and initial gate electrode 216 can comprise polysilicon, and mask pattern 218 can comprise the material relative to initial gate insulation layer 214 and initial gate electrode 216 with etching selectivity.
Fig. 8 to Figure 10 is the sectional view intercepted along the line B-B' of Fig. 6, and the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some embodiments be provided as according to the present invention's design is shown.With reference to Fig. 8, original trench district 118 can use initial gate 220 to be etched with as etching mask and form channel region 120.The sidewall of initial gate 220 and the sidewall of channel region 120 can be aimed at substantially perpendicular to each other.Original trench district 118 can be etched until the horizontal component that channel region 120 extends on the upper surface of substrate 100 arrives predetermined thickness, as shown in Figure 8.In other words, original trench district 118 can be etched until original trench district 118 by the degree of depth of etching part arrive desired depth.In certain embodiments, original trench district 118 can be etched until the upper surface of substrate 100 is exposed.
To understand, before etching original trench district 118, offset spacer can be formed on the sidewall of initial gate 220, and offset spacer can be used as etching mask when etching original trench district 118 together with initial gate 220.Therefore, in certain embodiments, the sidewall of channel region 120 laterally can be given prominence to from the sidewall of initial gate 220.In certain embodiments, even if when offset spacer is used as etching mask, due to the depression of the transverse direction of original trench district 118 below offset spacer, the sidewall of initial gate 220 and the sidewall of channel region 120 can be aimed at substantially perpendicular to each other, as shown in Figure 8.Offset spacer can comprise the material relative to original trench district 118 with etching selectivity, and offset spacer can comprise such as silicon nitride.
With reference to Fig. 9, barrier layer 140 can be formed on channel region 120.Can carry out epitaxial growth technology to form barrier layer 140, channel region 120 can be used as seed layer.Barrier layer 140 can comprise Si xge 1-x, x can in the scope of about 0.05 to about 0.2.In certain embodiments, barrier layer 140 can to have on whole barrier layer 140 uniform composition substantially and makes x can be constant on whole barrier layer 140.But will understand, barrier layer 140 can the vicissitudinous composition of tool.Such as, silicon concentration can have the gradient in barrier layer 140, and x can be understood to the mean value of x in barrier layer 140.
When before formation barrier layer 140, the sidewall of initial gate 220 and the sidewall of channel region 120 are by substantially perpendicular to each other on time, the sidewall on barrier layer 140 can substantially perpendicularly in alignment with the sidewall of initial gate 220, as shown in Figure 9.As discussed with reference to Fig. 8, in certain embodiments, the sidewall of channel region 120 laterally can be given prominence to from the sidewall of initial gate 220 before formation barrier layer 140, and therefore the sidewall on barrier layer 140 can laterally be given prominence to from the sidewall of initial gate 220.The width on barrier layer can be typically about the order of magnitude of 10nm, and in certain embodiments, the width on barrier layer 140 can be about 10nm.In certain embodiments, barrier layer 140 can comprise undoped and/or doping part.Such as, the part of doping can comprise the boron (B) for P type finFET and the phosphorus (P) for N-type finFET or arsenic (As) as dopant.
According to Figure 10, source/drain region 160 can be formed on barrier layer 140.Source/drain region 160 can use epitaxial growth technology to be formed, and barrier layer 140 can be used as seed layer.To understand, can carry out in identical processing chamber with the epitaxial growth technology of source/drain region 160 for the formation of barrier layer 140.In certain embodiments, in N-type transistor, source/drain region 160 can be included in the part comprising pure silicon substantially near contact zone 180, and in P-type crystal pipe, source/drain region 160 can be included in the part comprising pure germanium substantially near contact zone 180.Contact zone 180 can be formed in the upper surface that source/drain region 160 also can contact source/drain region 160.
Referring again to Fig. 2, grid 240 can be formed on channel region 120.In certain embodiments, initial gate 220 can use such as replacement gate process and replace with grid 240.When using replacement gate process, the method can be included on channel region 120 and on the sidewall of initial gate 220 and form interlayer insulating film.Sept can be formed in the opposing sidewalls of initial gate 220 before formation interlayer insulating film.Initial gate insulation layer 214, initial gate electrode 216 and mask pattern 218 can use etch process, wet etching process and/or dry etching process to remove to form groove in interlayer insulating film.Then gate insulation layer 236 and gate electrode 238 can be formed in the trench.
Figure 11 to Figure 13 is the sectional view intercepted along the line B-B' of Fig. 6, and the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some embodiments be provided as according to the present invention's design is shown.With reference to Figure 11, after forming the structure shown in Fig. 7, ion implantation technology can be carried out and inject silicon ion to original trench district 118 to use initial gate 220 as implantation mask layer.Therefore, the part exposed by initial gate 220 in original trench district 118 can be converted into the initial resistance floor 138 comprising silicon.Initial resistance layer 138 can comprise Si xge 1-x, x can in the scope of about 0.05 to about 0.2.Initial resistance layer 138 can be amorphous after carrying out ion implantation technology, therefore can carry out annealing process to make initial resistance layer 138 crystallization.
The thickness of initial resistance layer 138 can be determined according to the energy level of ion implantation technology.Such as, the thickness of initial resistance layer 138 can increase along with the energy level of ion implantation technology and increase.In certain embodiments, only the top in original trench district 118 can be converted into initial resistance floor 138 as shown in figure 11, and the horizontal component of channel region 120 can be extended between the upper surface of substrate 100 and initial resistance layer 138.But will understand, original trench district 118 whole part in vertical direction can be converted into initial resistance floor 138, initial resistance layer 138 can the upper surface of contact substrate 100.
According to Figure 12, offset spacer 250 can be formed in the opposing sidewalls of initial gate 220, and then initial resistance layer 138 can use offset spacer 250 and initial gate 220 to be etched with as etching mask and form barrier layer 140.Initial resistance layer 138 can be etched until the part that initial resistance layer 138 extends on the upper surface of substrate 100 arrives predetermined thickness, as shown in figure 12.In other words, initial resistance layer 138 can be etched, until the degree of depth of the etching part of initial resistance layer 138 arrives desired depth.In certain embodiments, initial resistance layer 138 can be etched until the upper surface of channel region 112 is exposed.
Source/drain region 160 can be formed in (Figure 13) on barrier layer 140.Source/drain region 160 can use epitaxial growth technology to be formed, and barrier layer 140 can be used as seed layer.Referring again to Fig. 2, grid 240 can be formed on channel region 120.Initial gate 220 can use such as replacement gate process grid 240 to replace.
Disclosed theme should be considered to illustrative above, instead of restrictive, claims be intended to contain drop on the present invention's design practicalness and scope in all such amendments, enhancing and other embodiment.Therefore, allow at utmost to law, scope of the present invention is released by the widest admissible solutions of claim and equivalent thereof and is determined, and by above detailed description restriction or should not limit.
This application claims and to submit to and name is called the priority of the U.S. Provisional Patent Application No.61/883235 of " HIGHPERFORMANCE GE FINFET WITH LOW BAND-TO-BAND TUNNELINGLEAKAGE CURRENT (having the high-performance Ge fin-shaped FET of low interband Tunneling leakage current) " in U.S.Patent & Trademark Office on September 27th, 2013, its disclosure by reference entirety is incorporated into this.

Claims (20)

1. form a method for fin-shaped field effect transistor, the method comprises:
Substrate is formed the fin-shaped channel district comprising germanium;
Form the source/drain region of contiguous described channel region on the substrate;
Form the barrier layer of the contact sidewall of described channel region and the sidewall of described source/drain region, wherein said barrier layer comprises Si xge 1-x, and x is in the scope of 0.05 to 0.2.
2. the method for claim 1, the germanium concentration in wherein said channel region is greater than the germanium concentration in described barrier layer.
3. the method for claim 1, wherein:
Form described channel region to comprise formation and comprise Si 1-yge ychannel region, and y is in the scope of 0.8 to 1;
Form described source/drain region and comprise the part comprising pure germanium substantially forming described source/drain region.
4. method as claimed in claim 3, wherein:
Germanium concentration in described channel region is greater than the germanium concentration in described barrier layer, and
Germanium concentration in described source/drain region is substantially equal to or is greater than the germanium concentration in described barrier layer.
5. method as claimed in claim 3, also comprises the contact zone of the upper surface forming the described source/drain region of contact, contact zone described in the part contact comprising pure germanium substantially of wherein said source/drain region.
6. the method for claim 1, wherein:
Form described channel region to comprise formation and comprise Si 1-yge ydescribed channel region, and y is in the scope of 0.85 to 1; And
Form described source/drain region and comprise the part comprising pure silicon substantially forming described source/drain region.
7. method as claimed in claim 6, the germanium concentration in wherein said channel region is greater than the germanium concentration in described barrier layer.
8. method as claimed in claim 6, also comprises the contact zone of the upper surface forming the described source/drain region of contact, contact zone described in the part contact comprising pure silicon substantially of wherein said source/drain region.
9. the method for claim 1, wherein forms described channel region and described barrier layer and comprises:
Form original trench district on the substrate;
Described original trench district forms mask pattern;
Use described mask pattern as etching mask to etch described original trench district to form described channel region; And
Use described channel region as barrier layer described in seed layer epitaxial growth.
10. method as claimed in claim 9, wherein forms described mask pattern and comprises:
Described original trench district forms the first mask pattern; And
The opposing sidewalls of described first mask pattern forms spacer patterns.
11. methods as claimed in claim 9, wherein etch described original trench district comprise etching described original trench district until described original trench district by the degree of depth of etching part arrive desired depth.
12. the method for claim 1, wherein form described channel region and described barrier layer and comprise:
Form original trench district on the substrate;
The Part I in described original trench district forms the first mask pattern;
Described first mask pattern is used to stop that mask injects silicon ion to described original trench district as injection;
On the described Part I in described original trench district, the second mask pattern is formed after the described silicon ion of injection; And
Described second mask pattern is used to etch described original trench district to form described channel region and described barrier layer as etching mask.
13. methods as claimed in claim 12, are wherein formed in opposing sidewalls that described second mask pattern is included in described first mask pattern and form spacer patterns.
14. the method for claim 1, wherein form described source/drain region and comprise the described barrier layer of use as source/drain region described in seed layer epitaxial growth.
15. the method for claim 1, wherein:
Form the first source/drain region that described source/drain region comprises the first side wall forming contiguous described channel region, make described barrier layer contact the described the first side wall of described channel region and the sidewall of described first source/drain region; And
The method also comprises formation second source/drain region, and described second source/drain region contacts second sidewall contrary with the described the first side wall of described channel region of described channel region.
16. the method for claim 1, also comprise the contact zone of the upper surface forming the described source/drain region of contact.
17. the method for claim 1, wherein said barrier layer is about 10nm at the width on from described channel region to the direction of described source/drain region.
18. the method for claim 1, also comprise being formed and cover the gate electrode of described channel region, and the sidewall being substantially aligned at described gate electrode with the sidewall of the sidewall contact of described channel region on wherein said barrier layer makes knot be formed in described barrier layer.
19. 1 kinds of methods forming fin-shaped field effect transistor, the method comprises:
Substrate is formed the fin-shaped channel district comprising germanium;
On the substrate and form source/drain region on the sidewall of described channel region; And
Barrier layer is formed between the sidewall of the sidewall in described channel region and described source/drain region, wherein:
Described barrier layer comprises silicon and germanium; And
Germanium concentration in described barrier layer is less than the germanium concentration in described channel region.
20. 1 kinds of integrated circuit (IC)-components comprising fin-shaped field effect transistor, comprising:
Comprise the fin-shaped channel district of germanium, on substrate;
Source/drain region, on the substrate contiguous described channel region; And
Barrier layer, contact the sidewall of described channel region and the sidewall of described source/drain region, wherein said barrier layer comprises Si xge 1-x, and x is in the scope of 0.05 to 0.2.
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CN105185712A (en) * 2014-05-02 2015-12-23 三星电子株式会社 Integrated circuit devices including finfets and methods of forming the same
CN107667430A (en) * 2015-06-26 2018-02-06 英特尔公司 High mobility semiconductor source/drain spacer
CN108695158A (en) * 2017-04-05 2018-10-23 中芯国际集成电路制造(北京)有限公司 A kind of semiconductor devices and its manufacturing method
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