CN105185712A - Integrated circuit devices including finfets and methods of forming the same - Google Patents
Integrated circuit devices including finfets and methods of forming the same Download PDFInfo
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- CN105185712A CN105185712A CN201510220856.4A CN201510220856A CN105185712A CN 105185712 A CN105185712 A CN 105185712A CN 201510220856 A CN201510220856 A CN 201510220856A CN 105185712 A CN105185712 A CN 105185712A
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- channel region
- source
- drain
- sidewall
- barrier layer
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- 238000000034 method Methods 0.000 title claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 229910052738 indium Inorganic materials 0.000 claims abstract description 29
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims description 131
- 230000015572 biosynthetic process Effects 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000013078 crystal Substances 0.000 claims description 13
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052733 gallium Inorganic materials 0.000 claims description 10
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 9
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 157
- 229910052732 germanium Inorganic materials 0.000 description 19
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 18
- 238000009413 insulation Methods 0.000 description 18
- 125000006850 spacer group Chemical group 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- -1 silicon ion Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1-yAs, and y is in a range of about 0.3 to about 0.5.
Description
The cross reference of related application
The application is the U.S. Non-provisional Patent patent application serial numbers 14/489 being entitled as INTEGRATEDCIRCUITDEVICESINCLUDINGFINFETSANDMETHODSOFFORM INGTHESAME (integrated circuit (IC)-components comprising fin FETs and forming method thereof) submitted at USPTO on September 18th, 2014, the part continuation application of 965, it requires the U.S. Provisional Patent Application sequence number 61/883 being entitled as HIGHPERFORMANCEGeFINFETWITHLOWBAND-TO-BANDTUNNELINGLEAKA GECURRENT (having the high-performance Ge fin FETs of low interband Tunneling leakage current) that on September 27th, 2013 submits at USPTO, the priority of 235, its disclosure is all by reference to being hereby incorporated herein.The application also requires the U.S. Provisional Patent Application sequence number 61/988 being entitled as HIGHPERFORMANCEGeFINFETWITHLOWBAND-TO-BANDTUNNELINGLEAKA GECURRENT (having the high-performance Ge fin FETs of low interband Tunneling leakage current) that on May 2nd, 2014 submits at USPTO, the U.S. Provisional Patent Application sequence number 61/988 being entitled as HIGHPERFORMANCEInGaAsFINFETWITHLOWBAND-TO-BANDTUNNELINGL EAKAGECURRENT (there is the high-performance InGaAs fin FETs of low interband Tunneling leakage current) that on May 2nd, 039 and 2014 submits at USPTO, the priority of 046, its disclosure is all by reference to being hereby incorporated herein.
Technical field
Present disclosure relates generally to person in electronics, and more specifically, relates to the method forming integrated circuit (IC)-components.
Background technology
Developed comprise pure germanium raceway groove or InGaAsP (InGaAs) raceway groove fin FETs (fin formula field effect transistor) to improve carrier mobility.But those fin FETs can have higher leakage current due to interband tunnelling (bandtoband, band-to-bandtunneling, the BTBT) electric current in drain region.
Summary of the invention
The method forming fin FETs can comprise: in substrate, form the fin-shaped channel region comprising indium (In), form the deep/source drain extensions being adjacent to described channel region on the substrate, and form source/drain extension area between described channel region and described deep/source drain extensions.The contrary sidewall of described source/drain extension area can contact described channel region and described deep/source drain extensions respectively.Described source/drain extension area can comprise In
yga
1-yas, and y can in the scope of about 0.3-about 0.5.
In numerous embodiments, the indium concentration in described channel region can be greater than the indium concentration in described source/drain extension area.
According to numerous embodiments, form described channel region and can comprise formation and comprise In
xga
1-xthe channel region of As, and x can in the scope of about 0.5-about 0.6.
According to numerous embodiments, x can be about 0.53.In numerous embodiments, y can be about 0.4.
In numerous embodiments, the indium concentration in described deep/source drain extensions can be greater than the indium concentration in described channel region.
According to numerous embodiments, form described deep/source drain extensions and can comprise formation and comprise In
zga
1-zthe deep/source drain extensions of As, z can in the scope of about 0.6-about 1.
In numerous embodiments, described method can comprise the contact zone of the upper face forming the described deep/source drain extensions of contact further.A part for described deep/source drain extensions can contact described contact zone and can comprise pure InAs.
According to numerous embodiments, described substrate can comprise at the bottom of InP-base or In
aga
1-aas, and a can be about 0.53 or less.
In numerous embodiments, described substrate can comprise at the bottom of InP-base, and comprises In described in being formed
xga
1-xthe channel region of As can comprise that formed can In at the bottom of Lattice Matching to described InP-base
xga
1-xas pattern.
According to numerous embodiments, form described channel region and described source/drain extension area can comprise: form preliminary channel region on the substrate, described preliminary channel region forms mask pattern, use described mask pattern as the described preliminary channel region of etching mask etching to form described channel region, with the described channel region of use as source/drain extension area described in crystal seed layer (Seed Layer, seedlayer) epitaxial growth.
In numerous embodiments, forming described mask pattern can comprise: on described preliminary channel region, form the first mask pattern, and forms spacer patterns on the contrary sidewall of described first mask pattern.
In numerous embodiments, etch described preliminary channel region and can comprise the described preliminary channel region of etching until the degree of depth through etching part of described preliminary channel region reaches desired depth.
According to numerous embodiments, form described deep/source drain extensions and can comprise the described source/drain extension area of use as deep/source drain extensions described in crystal seed layer epitaxial growth.
In numerous embodiments, form described deep/source drain extensions and can comprise the first deep/source drain extensions being formed and can be adjacent to the first side wall of described channel region, make the contrary sidewall of described source/drain extension area contact the first side wall of described channel region and the sidewall of described first deep/source drain extensions respectively.Described method can comprise the second deep/source drain extensions of the second sidewall forming the contact described channel region contrary with the first side wall of described channel region further.
In numerous embodiments, described method also can comprise the contact zone of the upper face forming the described deep/source drain extensions of contact.
According to numerous embodiments, described source/drain extension area can be about 10nm at the width on from described channel region to the direction of described deep/source drain extensions.
In numerous embodiments, described method can comprise the gate electrode being formed and overlay on above described channel region further.Contact one of contrary sidewall of the described source/drain extension area of the sidewall of described channel region can with the sidewall substantial alignment (aligned) of described gate electrode, make can be formed in described source/drain extension area knot (junction).
The method forming fin FETs can comprise: in substrate, form the fin-shaped channel region comprising the first semi-conducting material, on the sidewall of described channel region, form source/drain region on the substrate, and form barrier layer between sidewall in described channel region and the sidewall of described source/drain region.Described barrier layer can comprise described first semi-conducting material and the second semi-conducting material, and the first semi-conducting material concentration in described barrier layer can be less than the first semi-conducting material concentration in described channel region.
According to numerous embodiments, the first semi-conducting material concentration in described source/drain region and the first semi-conducting material concentration in described barrier layer can be different.
In numerous embodiments, described first semi-conducting material can comprise indium (In), and described second semi-conducting material can comprise gallium (Ga).The first semi-conducting material concentration in described source/drain region can be greater than the first semi-conducting material concentration in described channel region.
In numerous embodiments, form described channel region and can comprise formation and comprise In
xga
1-xthe channel region of As, and x can in the scope of about 0.5-about 0.6.
According to numerous embodiments, described first semi-conducting material can comprise indium (In), and forms described channel region and can comprise formation and comprise In
xga
1-xthe channel region of As, and x can in the scope of about 0.5-about 0.6.
In numerous embodiments, form described barrier layer and can comprise formation and comprise In
yga
1-ythe barrier layer of As, and y can in the scope of about 0.3-about 0.5.
According to numerous embodiments, x can be about 0.53.In numerous embodiments, y can be about 0.4.
According to numerous embodiments, the indium concentration in described source/drain region can be greater than the indium concentration in described channel region.
In numerous embodiments, form described source/drain region and can comprise formation and comprise In
zga
1-zthe source/drain region of As, and z can in the scope of about 0.6-about 1.
According to numerous embodiments, described method also can comprise the contact zone of the upper face forming the described source/drain region of contact.A part for described source/drain region can contact described contact zone and can comprise pure InAs.
In numerous embodiments, described substrate can comprise at the bottom of InP-base or In
aga
1-aas, and a can be about 0.53 or less.
According to numerous embodiments, described substrate can comprise at the bottom of InP-base, and comprises In described in being formed
xga
1-xthe channel region of As can comprise that formed can In at the bottom of Lattice Matching to described InP-base
xga
1-xas pattern.
According to numerous embodiments, form described channel region and described barrier layer can comprise: form preliminary channel region on the substrate, described preliminary channel region forms mask pattern, use described mask pattern as the described preliminary channel region of etching mask etching to form described channel region, and use described channel region as barrier layer described in crystal seed layer epitaxial growth.
In numerous embodiments, forming described mask pattern can comprise: on described preliminary channel region, form the first mask pattern, and forms spacer patterns on the contrary sidewall of described first mask pattern.
According to numerous embodiments, formed on the first side wall that described source/drain region can be included in described channel region and form the first source/drain region, described barrier layer can be arranged between the first side wall of described channel region and the sidewall of described first source/drain region.Described method can comprise the second source/drain region of the second sidewall forming the contact described channel region contrary with the first side wall of described channel region further.
According to numerous embodiments, described barrier layer can be about 10nm at the width on from described channel region to the direction of described source/drain region.
In numerous embodiments, described method can comprise the gate electrode being formed and overlay on above described channel region further.In the face of described channel region sidewall described barrier layer sidewall can with the sidewall substantial alignment of described gate electrode, make to form knot in described barrier layer.
The integrated circuit (IC)-components comprising fin FETs can comprise: in the suprabasil fin-shaped channel region comprising indium (In), the deep/source drain extensions being adjacent to described channel region on the substrate, and the source/drain extension area comprising the contrary sidewall contacting described channel region and described deep/source drain extensions respectively.Described source/drain extension area can comprise In
yga
1-yas, and y can in the scope of about 0.3-about 0.5.
In numerous embodiments, the indium concentration in described channel region can be greater than the indium concentration in described source/drain extension area.
According to numerous embodiments, described channel region can comprise In
xga
1-xas, and x can in the scope of about 0.5-about 0.6.
In numerous embodiments, x can be about 0.53.According to numerous embodiments, y can be about 0.4.
According to numerous embodiments, the indium concentration in described deep/source drain extensions can be greater than the indium concentration in described channel region.
In numerous embodiments, described deep/source drain extensions can comprise In
zga
1-zas, and z can in the scope of about 0.6-about 1.
In numerous embodiments, described device can comprise the contact zone of the upper face contacting described deep/source drain extensions further.A part for described deep/source drain extensions can contact described contact zone and can comprise pure InAs.
According to numerous embodiments, described substrate can comprise at the bottom of InP-base or In
aga
1-aas, and a can be about 0.53 or less.
In numerous embodiments, described substrate can comprise at the bottom of InP-base, and can comprise can In at the bottom of Lattice Matching to described InP-base in described channel region
xga
1-xas pattern.
According to numerous embodiments, described deep/source drain extensions can comprise the first deep/source drain extensions, it can be adjacent to the first side wall of described channel region, makes one of contrary sidewall of described source/drain extension area contact the first side wall of described channel region and the sidewall of described first deep/source drain extensions.Described device can comprise the second deep/source drain extensions further, the second sidewall of the described channel region that its contact is contrary with the first side wall of described channel region.
In numerous embodiments, described source/drain extension area can be about 10nm at the width on from described channel region to the direction of described deep/source drain extensions.
According to numerous embodiments, described device also can comprise the gate electrode overlayed on above described channel region.Contact one of contrary sidewall of the described source/drain extension area of the sidewall of described channel region can with the sidewall substantial alignment of described gate electrode, make to form knot in described source/drain extension area.
Accompanying drawing explanation
Fig. 1 is the perspective view of the integrated circuit (IC)-components of some execution modes illustrated according to the present invention's design.
The cross-sectional view got along the line A-A ' of Fig. 1 of the integrated circuit (IC)-components of some execution modes that Fig. 2 conceives according to the present invention for explanation.
The cross-sectional view got along the line A-A ' of Fig. 1 of the integrated circuit (IC)-components of some execution modes that Fig. 3 conceives according to the present invention for explanation.
Fig. 4 is the perspective view of the integrated circuit (IC)-components of some execution modes illustrated according to the present invention's design.
Fig. 5-6 is the perspective view of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components that some execution modes be provided as according to the present invention's design are described.
Fig. 7 is provided as the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes according to the present invention's design for explanation.
Fig. 8 to 10 is for illustrating the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes be provided as according to the present invention's design.
Figure 11 to 13 is for illustrating the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes be provided as according to the present invention's design.
Embodiment
Below with reference to the accompanying drawings Example embodiments is described.When the spirit and the instruction that do not deviate from present disclosure, many different forms and execution mode are possible, and therefore described disclosure should not be construed as and is limited to set forth Example embodiments herein.On the contrary, provide these Example embodiments, make present disclosure to be thorough and complete, and the scope of present disclosure will be passed on to those skilled in the art.In the accompanying drawings, in order to clear, can the size in amplification layer and district and relative size.Identical Reference numeral refers to identical element all the time.
The Example embodiments of the present invention's design is described with reference to the cross-sectional view of the idealized execution mode of execution mode and the schematic diagram of intermediate structure as an example or perspective view.Like this, using expect as such as manufacturing technology and/or tolerance result with the deviation of illustrated shape.Therefore, the Example embodiments of the present invention's design should not be construed as and is limited to illustrated given shape herein, but comprises by such as manufacturing the deviation in shape caused.
Unless otherwise defined, the implication of used in this article all terms (comprising technology and scientific terminology) is identical with the implication that those skilled in the art understand usually.Will be further understood that, term, such as define in common dictionary those, should be interpreted as having the implication that implication with them in association area background is consistent, and will not make an explanation, unless clearly so defined in this article with meaning that is idealized or too form.
The term used in this article is only in order to describe the object of embodiment and be not intended to limit described execution mode.As used in this article, singulative " a kind of (individual) (a, an) " and " being somebody's turn to do (described) (the) " are also intended to comprise plural form, unless context clearly indicates in addition.Will be further understood that, term " comprises ", " comprising ", " containing " and/or " containing " where used in this disclosure, show the feature described in existing, step, operation, element and/or parts (component), but do not get rid of existence or increase one or more further feature, step, operation, element, parts (component) and/or its set.
To understand, when an element be called as " combination " to, ' attach ' to or " response " in other element or " " other element " on " time, it can directly be attached to, be connected to or in response to described other element or on described other element, or also can there is intermediary element.On the contrary, when an element be called as " directly combine " to, " directly connecting " to or " directly responding " in other element or " directly existing " other element " on " time, then there is not intermediary element.Use "and/or" as used in this article comprises one or more any and whole combination of associated listed items.
To understand, although first, second grade of term can in this article for describing multiple element, these elements should not limit by these terms.These terms are only for separating an element with another element region.Therefore, when not departing from the instruction of present embodiment, the first element can be referred to as the second element.
For convenience of description, in this article can usage space relative terms such as " ... under ", " ... below ", " bottom ", " in ... top ", " top " etc. describes the relation of an element or feature and other element or feature as illustrated in the drawing.To understand, except the orientation shown in figure, space relative terms is also intended to the different azimuth of the device comprised in use or operation.Such as, if by the device upset in figure, be described as " " element of other element or feature " below " or " under " then by orientation " " described in other element or feature " top ".Therefore, exemplary term " ... can be encompassed in below " ... top and ... two kinds of orientation below.Device can otherwise directed (90-degree rotation or in other orientation), and the space relative descriptors used in this article can correspondingly make an explanation.
Due to the higher leakage current in drain region, use pure germanium raceway groove can improve device performance as expected.As the present inventor understand, silicon is added to (such as, by germanium and alloying with silicon) in germanium and can increase direct band gap and reduce leakage current in drain region.The method comprising the integrated circuit (IC)-components of fin formula field effect transistor (fin FETs) according to the formation of the numerous embodiments of the present invention's design can be included in the barrier layer optionally being formed in the tunnel region be arranged between channel region and drain region and comprise germanium and silicon.
Fig. 1 is the perspective view of integrated circuit (IC)-components of some execution modes illustrated according to the present invention's design, and the cross-sectional view got along the line A-A ' of Fig. 1 of the integrated circuit (IC)-components of some execution modes that Fig. 2 conceives according to the present invention for explanation.Line A-A ' extends in the X direction.
With reference to Fig. 1 and 2, integrated circuit (IC)-components can comprise substrate 100 and be arranged on described suprabasil separator 110.Described integrated circuit (IC)-components also can comprise the channel region 120 with fin-shaped shape, and it can in substrate 100 and partly in separator 110.Channel region 120 can comprise germanium (Ge).To understand, channel region 120 can by Si
1-yge
yform, and the value of y can be determined based on the proper level of strain.
In some embodiments, when channel region 120 is the channel region of N-type transistor, channel region 120 can by Si
1-yge
yform, and the value of y can be about 0.85 or larger.In some substituting execution modes, the value of y can be about 0.9 or larger.In some substituting execution modes, in order to high carrier mobility, when channel region 120 is the channel region of N-type transistor, channel region 120 can be made up of substantially pure germanium (that is, the value of y is about 1).In some embodiments, when channel region 120 is the channel region of P-transistor npn npn, channel region 120 can by Si
1-yge
yform, and the value of y can be about 0.8 or larger.In some substituting execution modes, the value of y can be about 0.9 or larger.
Substrate 100 can comprise one or more semi-conducting materials, such as Si, Ge, SiGe, GaAs or SiGeC.In some embodiments, substrate 100 can be body (overall, bulk) silicon base or semiconductor-on-insulator (SOI) substrate.Separator 110 can comprise insulating material such as silica.
Grid 240 can be formed on channel region 120.Grid 240 can comprise gate insulation layer 236 and gate electrode 238.In some embodiments, gate insulation layer 236 can comprise the high k dielectric such as hafnium oxide (HfO with the dielectric constant higher than silica
2), lanthana (La
2o
3), zirconia (ZrO
2) and tantalum oxide (Ta
2o
5).Gate insulation layer 236 can use such as ald (ALD) technique to be conformally formed on the sidewall and lower surface of gate electrode 238.
In some embodiments, gate electrode 238 can comprise the first and second gate electrodes of sequence stack.Such as, described first grid electrode can comprise one of TiN, TaN, TiC and TaC, and described second electrode can comprise W or Al.
According to Fig. 2, barrier layer 140 can be arranged on the sidewall of channel region 120.Barrier layer 140 can contact the sidewall of channel region 120.Barrier layer 140 can comprise two barrier layers 140 be arranged on each contrary sidewall of channel region 120.In some embodiments, barrier layer 140 can be included in the horizontal component that the upper face of substrate 100 extends separately, as illustrated in figure 2.Barrier layer 140 can comprise Si
xge
1-x, and x can in the scope of about 0.05-about 0.2.Therefore, the germanium concentration in barrier layer 140 can be less than the germanium concentration in channel region 120.
The width on barrier layer 140 substantially in the grade of 10nm, and in some embodiments, can stop that the width of 140 can be about 10nm.To understand, the width on barrier layer 140 refers to the thickness in the X-direction illustrated in FIG of barrier layer 140.In some embodiments, barrier layer 140 can comprise part that is unadulterated and/or doping, can comprise with the part of described doping, such as, the boron (B) for P-type fin FETs and the phosphorus (P) for N-type fin FETs or arsenic (As) are as dopant.In some embodiments, knot (such as, P-N junction) can be formed in the outside at the edge of gate electrode 238, make described knot can not be laterally overlapping with gate electrode 238.Described knot can be formed in barrier layer 140.In some substituting execution modes, described knot can be formed in the inside at the edge of gate electrode 238, makes gate electrode 238 can be laterally overlapping with described knot.No matter how, the execution mode reducing interband tunnelling current can comprise the barrier layer 140 of the alloy comprising germanium and silicon in the position of described knot.Although the sidewall on barrier layer 140 aligns with the sidewall of gate insulation layer 236 in Fig. 2 key diagram 2, in some embodiments, the sidewall on barrier layer 140 can align with the sidewall of gate electrode 238.
In some embodiments, the horizontal component of channel region 120 can extend between the upper face of substrate 100 and the horizontal component on barrier layer 140, as illustrated in figure 2.But in some embodiments, channel region 120 can not comprise horizontal component and therefore barrier layer 140 can contact the upper face of substrate 100.
The contact zone 180 that described integrated circuit (IC)-components can comprise the source/drain region 160 on the sidewall being arranged on barrier layer 140 further and be arranged on source/drain region 160.Therefore, barrier layer 140 can be arranged in the tunnel region between channel region 120 and source/drain region 160.Contact zone 180 can contact the upper face of source/drain region 160.Barrier layer 140 can contact the sidewall of channel region 120 and source/drain region 160.Contact zone 180 can contact conductive layer, and source/drain region 160 is electrically connected to multiple parts such as bit line or capacitor of described integrated circuit (IC)-components by it.Described conductive layer can comprise metal or metal alloy.
To understand, when source/drain region 160 is in N-type transistor, source/drain region 160 can be included in the part comprising substantially pure silicon near contact zone 180, with when source/drain region 160 is in P-transistor npn npn, source/drain region 160 can be included in the part comprising substantially pure germanium near contact zone 180.Therefore, such germanium concentration in channel region 120, barrier layer 140 and source/drain region 160 can be had according to the N-type transistor of some execution modes of the present invention's design: it reduces along from channel region 120 to the direction of source/drain region 160.The P-transistor npn npn of some execution modes according to the present invention's design can have the germanium concentration in described channel region larger than the germanium concentration in described barrier layer, and can have substantially the same with the germanium concentration in described barrier layer or larger than it germanium concentration in described source/drain region.In some embodiments, in N-type transistor, the part comprising substantially pure silicon of source/drain region 160 can contact described contact zone 180, and in P-transistor npn npn, the part comprising substantially pure germanium of source/drain region 160 can contact described contact zone 180.
The cross-sectional view got along the line A-A ' of Fig. 1 of the integrated circuit (IC)-components of some execution modes that Fig. 3 conceives according to the present invention for explanation.With reference to figure 3, integrated circuit (IC)-components can comprise be arranged on channel region 120 the first side wall on a barrier layer 140.Therefore, the source/drain region 160 being adjacent to the second sidewall of the channel region 120 contrary with the first side wall of channel region 120 can contact the second sidewall of channel region 120.In other words, in some embodiments, barrier layer 140 can at the sidewall of channel region 120 only on one and therefore described integrated circuit (IC)-components can have asymmetrical structure.
Fig. 4 is the perspective view of the integrated circuit (IC)-components of some execution modes illustrated according to the present invention's design.With reference to figure 4, bury separator 112 can be arranged in substrate 100 and channel region 120 can be arranged on bury separator 112 upper face on.Burying separator 112 can between substrate 100 and channel region 120.To understand, channel region 120 can use SOI manufacturing process such as wafer to combine (bonding chip, waferbonding) technique and be formed.
Fig. 5 and 6 is the perspective view of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components that some execution modes be provided as according to the present invention's design are described.Fig. 7 is provided as the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes according to the present invention's design for explanation.With reference to figure 5, separator 110 and preliminary channel region 118 can be formed in substrate 100.The low portion of preliminary channel region 118 can in separator 110, and the contrary sidewall of preliminary channel region 118 can contact seal 110.Preliminary channel region 118 can have the wire shaped extended in the X direction.In some embodiments, epitaxial growth technology can be used to use substrate 100 to form preliminary channel region 118 as crystal seed layer.
According to Fig. 6 and 7, preliminary grid 220 can be formed on preliminary channel region 118.Preliminary grid 220 can have with the wire shaped that extends in the Y-direction of described X-direction perpendicular.Therefore, preliminary grid 220 can intersect above preliminary channel region 118.Preliminary grid 220 can comprise preliminary gate insulation layer 214, preliminary gate electrode 216 and mask pattern 218.Such as, preliminary gate insulation layer 214 can comprise oxide, and preliminary gate electrode 216 can comprise polysilicon, and mask pattern 218 can comprise the material of the etching selectivity had for preliminary gate insulation layer 214 and preliminary gate electrode 216.
Fig. 8 to 10 is for illustrating the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes be provided as according to the present invention's design.With reference to figure 8, preliminary grid 220 can be used to etch preliminary channel region 118 to form channel region 120 as etching mask.The sidewall of preliminary grid 220 and the sidewall of channel region 120 can align each other substantially vertically.Preliminary channel region 118 can be etched until reach predetermined thickness at the horizontal component of the channel region 120 that the upper face of substrate 100 extends, as illustrated in figure 8.In other words, preliminary channel region 118 can be etched until the degree of depth through etching part of preliminary channel region 118 reaches desired depth.In some embodiments, preliminary channel region 118 can be etched until the upper face of substrate 100 is exposed.
To understand, before the preliminary channel region 118 of etching, offset spacer can be formed on the sidewall of preliminary grid 220, and when etching preliminary channel region 118, described offset spacer can be used as etching mask together with preliminary grid 220.Therefore, in some embodiments, the sidewall of channel region 120 laterally can be given prominence to from the sidewall of preliminary grid 220.In some embodiments, even if when using described offset spacer as etching mask, due to the transverse recess of the preliminary channel region 118 below described offset spacer, the sidewall of preliminary grid 220 and the sidewall of channel region 120 also can align each other substantially vertically, as illustrated in figure 8.Described offset spacer can comprise the material of the etching selectivity had for preliminary channel region 118, and described offset spacer can comprise such as silicon nitride.
With reference to figure 9, barrier layer 140 can be formed on channel region 120.Epitaxial growth technology can be carried out to form barrier layer 140, and channel region 120 can be used as crystal seed layer.Barrier layer 140 can comprise Si
xge
1-x, and x can in the scope of about 0.05-about 0.2.In some embodiments, barrier layer 140 can have and substantially forms uniformly in whole barrier layer 140, makes x in whole barrier layer 140 can be constant.But will understand, barrier layer 140 can have variable composition.Such as, in whole barrier layer 140, silicon concentration can have gradient, and x can be regarded as the mean value of the x in barrier layer 140.
When making the sidewall of preliminary grid 220 and the sidewall of channel region 120 substantially align vertically each other before forming barrier layer 140, the sidewall on barrier layer 140 can align substantially vertically with the sidewall of preliminary grid 220, as illustrated in figure 9.As discussed in reference to Figure 8, in some embodiments, before formation barrier layer 140, the sidewall of channel region 120 laterally can be given prominence to from the sidewall of preliminary grid 220, and therefore the sidewall on barrier layer 140 can laterally be given prominence to from the sidewall of preliminary grid 220.The width on described barrier layer can substantially in the grade of 10nm, and in some embodiments, the width on barrier layer 140 can be about 10nm.In some embodiments, barrier layer 140 can comprise part that is unadulterated and/or doping.Such as, the part of described doping can comprise the boron (B) for P-type fin FETs and the phosphorus (P) for N-type fin FETs or arsenic (As) as dopant.
According to Figure 10, source/drain region 160 can be formed on barrier layer 140.Source/drain region 160 can use epitaxial growth technology to be formed, and barrier layer 140 can be used as crystal seed layer.To understand, epitaxial growth technology can be carried out to form barrier layer 140 and source/drain region 160 in identical processing chamber.In some embodiments, in N-type transistor, source/drain region 160 can be included in the part comprising substantially pure silicon near contact zone 180, and in P-transistor npn npn, source/drain region 160 can be included in the part comprising substantially pure germanium near contact zone 180.Contact zone 180 can be formed on source/drain region 160 with the upper face that can contact source/drain region 160.
Refer again to Fig. 2, grid 240 can be formed on channel region 120.In some embodiments, such as replacement grid technique grid 240 can be used to replace preliminary grid 220.When using replacement grid technique, described method can be included on channel region 120 and on the sidewall of preliminary grid 220 and form interlayer insulating film.Sept can be formed on the contrary sidewall of preliminary grid 220 before the described interlayer insulating film of formation.Can use etch process, wet method and/or dry method etch technology remove preliminary gate insulation layer 214, preliminary gate electrode 216 and mask pattern 218, to form groove in described interlayer insulating film.Then gate insulation layer 236 and gate electrode 238 can be formed in the trench.
Figure 11 to 13 is for illustrating the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes be provided as according to the present invention's design.With reference to Figure 11, in formation as after structure illustrated in fig. 7, preliminary grid 220 can be used to carry out ion implantation technology silicon ion to be implanted to preliminary channel region 118 as implantation (injection) mask layer.Therefore, preliminary channel region 118 can be converted into by the part that preliminary grid 220 expose the preliminary barrier layer 138 comprising silicon.Preliminary barrier layer 138 can comprise Si
xge
1-x, and x can in the scope of about 0.05-about 0.2.After carrying out described ion implantation technology, preliminary barrier layer 138 can be amorphous, and therefore can carry out annealing process to make preliminary barrier layer 138 crystallization.
The thickness on preliminary barrier layer 138 can be determined based on the energy level of described ion implantation technology (energy level).Such as, when the energy level of described ion implantation technology increases, the thickness on preliminary barrier layer 138 can increase.In some embodiments, as illustrated in Figure 11 the only upper part of preliminary channel region 118 can be converted into preliminary barrier layer 138, the horizontal component of channel region 120 can be extended between the upper face of substrate 100 and preliminary barrier layer 138.But, will understand, and the whole of the in the vertical direction of preliminary channel region 118 can be partially converted into preliminary barrier layer 138, the upper face of substrate 100 can be contacted with preliminary barrier layer 138.
According to Figure 12, offset spacer 250 can be formed on the contrary sidewall of preliminary grid 220, offset spacer 250 and preliminary grid 220 then can be used to etch preliminary barrier layer 138 to form barrier layer 140 as etching mask.Preliminary barrier layer 138 can be etched until the part that the upper face in substrate 100 on preliminary barrier layer 138 extends reaches predetermined thickness, as illustrated in Figure 12.In other words, preliminary barrier layer 138 can be etched until the degree of depth through etching part on preliminary barrier layer 138 reaches desired depth.In some embodiments, preliminary barrier layer 138 can be etched until the upper face of channel region 112 is exposed.
Source/drain region 160 (Figure 13) can be formed on barrier layer 140.Source/drain region 160 can use epitaxial growth technology to be formed, and barrier layer 140 can be used as crystal seed layer.Refer again to Fig. 2, grid 240 can be formed on channel region 120.Such as replacement grid technique grid 240 can be used to replace preliminary grid 220.
The raceway groove comprising the alloy of indium (In), gallium (Ga) and arsenide (arsenic, As) can improve carrier mobility.But due to the high leakage current in drain region, the device comprising InGaAsP raceway groove can improve device performance as expected.As the present inventor understand, the composition changed near drain region can increase direct band gap and therefore can reduce the leakage current in drain region.The method comprising the integrated circuit (IC)-components of fin formula field effect transistor (fin FETs) according to the formation of numerous embodiments of the present invention's design can be included in the tunnel region be arranged between channel region and drain region and optionally form source/drain extension area.
The integrated circuit (IC)-components of some execution modes according to the present invention's design is described with reference to Fig. 1 and 2.Refer again to Fig. 1 and 2, the separator 110 that integrated circuit (IC)-components can comprise substrate 100 and be arranged in substrate 100.Described integrated circuit (IC)-components also can comprise the channel region 120 with fin-shaped shape, and it can in substrate 100 and partly in separator 110.Channel region 120 can comprise indium (In), gallium (Ga) and arsenide (arsenic, As).Channel region 120 can by In
x1ga
1-x1as is formed, and the value of x1 can in the scope of about 0.5-about 0.6.In some embodiments, the value of x1 can be about 0.53, makes channel region 120 can by In
0.53ga
0.47as is formed.To understand, comprise In
0.53ga
0.47the channel region 120 of As can provide high electron mobility.
Substrate 100 can comprise one or more semi-conducting materials.Such as, substrate 100 can comprise indium phosphide (InP) or InGaAsP (In
aga
1-athe value of As, a can be about 0.53 or less).In some embodiments, substrate 100 can be at the bottom of InP-base, and channel region 120 can at the bottom of Lattice Matching to described InP-base.In some embodiments, substrate 100 can be body substrate or semiconductor-on-insulator (SOI) substrate.Separator 110 can comprise insulating material such as oxide.
Grid 240 can be formed on channel region 120.Grid 240 can comprise gate insulation layer 236 and gate electrode 238.In some embodiments, gate insulation layer 236 can comprise the high k dielectric such as hafnium oxide (HfO with the dielectric constant higher than silica
2), lanthana (La
2o
3), zirconia (ZrO
2) and tantalum oxide (Ta
2o
5).Gate insulation layer 236 can use such as ald (ALD) technique to be conformally formed on the sidewall and lower surface of gate electrode 238.
In some embodiments, gate electrode 238 can comprise the first and second gate electrodes of sequence stack.Such as, described first grid electrode can comprise one of TiN, TaN, TiC and TaC, and described second electrode can comprise tungsten (W) or aluminium (Al).
According to Fig. 2, barrier layer 140 can be arranged on the sidewall of channel region 120.Barrier layer 140 can contact the sidewall of channel region 120.Barrier layer 140 can comprise two barrier layers 140 be arranged on each contrary sidewall of channel region 120.In some embodiments, barrier layer 140 can be included in the horizontal component that the upper face of substrate 100 extends separately, as illustrated in figure 2.To understand, barrier layer 140 can be called as source/drain extension area.Barrier layer 140 can by In
y1ga
1-y1as is formed, and the value of y1 can be less than 0.53.In some embodiments, the value of y1 can in the scope of about 0.3-about 0.5, and the value of more particularly y1 can in the scope of about 0.35-about 0.4.In some embodiments, the value of y1 can be about 0.4, and barrier layer 140 can therefore by In
0.4ga
0.6as is formed.Therefore, the indium concentration in barrier layer 140 can be less than the indium concentration in channel region 120, and the gallium concentration in barrier layer 140 can be greater than the gallium concentration in channel region 120.Indium concentration in channel region 120 and barrier layer 140 and gallium concentration can increase band gap and therefore can reduce interband tunnelling current.In some embodiments, barrier layer 140 can comprise and comprise the defect reducing quantity or the region not comprising defect to reduce tunnelling (TA-BTBT) electric current between trap subband.
The width on barrier layer 140 in the grade of 10nm, and in some embodiments, can stop that the width of 140 can be about 10nm.To understand, the width on barrier layer 140 refers to the thickness in the X-direction illustrated in FIG of barrier layer 140.In some embodiments, knot (such as, P-N junction) can be formed in the outside at the edge of gate electrode 238, make described knot can not be laterally overlapping with gate electrode 238.Described knot can be formed in barrier layer 140.In some substituting execution modes, described knot can be formed in the inside at the edge of gate electrode 238, makes gate electrode 238 can be laterally overlapping with described knot.No matter the position of described knot how, can reduce interband tunnelling current according to the integrated circuit (IC)-components of some execution modes and can comprise the barrier layer 140 of the alloy comprising indium (In), gallium (Ga) and arsenide (arsenic, As).Although Fig. 2 illustrates that the sidewall on barrier layer 140 aligns with the sidewall of gate insulation layer 236, in some embodiments, the sidewall on barrier layer 140 can align with the sidewall of gate electrode 238.
In some embodiments, the horizontal component of channel region 120 can extend between the upper face of substrate 100 and the horizontal component on barrier layer 140, as illustrated in figure 2.But in some embodiments, channel region 120 can not comprise horizontal component and therefore barrier layer 140 can contact the upper face of substrate 100.
The contact zone 180 that described integrated circuit (IC)-components can comprise the source/drain region 160 on the sidewall being arranged on barrier layer 140 further and be arranged on source/drain region 160.To understand, source/drain region 160 can be described as deep/source drain extensions.Therefore, barrier layer 140 can be arranged in the tunnel region between channel region 120 and source/drain region 160.Contact zone 180 can contact the upper face of source/drain region 160.Barrier layer 140 can contact the sidewall of channel region 120 and source/drain region 160.Contact zone 180 can contact conductive layer, and source/drain region 160 is electrically connected to multiple parts such as bit line or capacitor of described integrated circuit (IC)-components by it.Described conductive layer can comprise metal or metal alloy.
Source/drain region 160 can by In
z1ga
1-z1as is formed, and the value of z1 can be greater than 0.53.In some embodiments, the value of z1 can in the scope of about 0.6-about 1.In some embodiments, the value of z1 can be about 1, and therefore source/drain region 160 can be made up of pure InAs.In some embodiments, source/drain region 160 can be included in the part comprising substantially pure InAs near contact zone 180.Therefore, the indium concentration in source/drain region 160 can be greater than the indium concentration in barrier layer 140, and the gallium concentration in source/drain region 160 can be less than the gallium concentration in barrier layer 140.
To understand, composition classification (gradual change, grading) along the sense of current can be had with tunnelling current between inhibition zone with low-leakage operation can be suitable for according to the transistor of some execution modes of the present invention's design.Transistor according to some execution modes of the present invention's design can be n-type field-effect transistor.In some embodiments, the base section of the base section and/or channel region 120 that are adjacent to the source/drain region 160 of substrate 100 can by InP and/or In
bga
1-bas (value of b can be about 0.53 or less) is formed.
Refer again to Fig. 3, integrated circuit (IC)-components can comprise be arranged on channel region 120 the first side wall on a barrier layer 140.Therefore, the source/drain region 160 being adjacent to the second sidewall of the channel region 120 contrary with the first side wall of channel region 120 can contact the second sidewall of channel region 120.In other words, in some embodiments, barrier layer 140 can at the sidewall of channel region 120 only on one and therefore described integrated circuit (IC)-components can have asymmetrical structure.
Refer again to Fig. 4, bury separator 112 and can be arranged in substrate 100, and channel region 120 can be arranged on bury separator 112 upper face on.Burying separator 112 can between substrate 100 and channel region 120.To understand, channel region 120 can use SOI manufacturing process such as wafer to be formed.
The formation method of the integrated circuit (IC)-components of some execution modes according to the present invention's design is described with reference to Fig. 5 to Figure 10.Fig. 5 and 6 is the perspective view of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components that some execution modes be provided as according to the present invention's design are described.Fig. 7 is provided as the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes according to the present invention's design for explanation.
Refer again to Fig. 5, separator 110 and preliminary channel region 118 can be formed in substrate 100.The low portion of preliminary channel region 118 can in separator 110, and the contrary sidewall of preliminary channel region 118 can contact seal 110.Preliminary channel region 118 can have the wire shaped extended in the X direction.In some embodiments, preliminary channel region 118 can use epitaxial growth technology to use substrate 100 to be formed as crystal seed layer.
Channel region 120 can by In
x1ga
1-x1as is formed, and the value of x1 can in the scope of about 0.5-about 0.6.In some embodiments, the value of x1 can be about 0.53, makes channel region 120 can by In
0.53ga
0.47as is formed.Substrate 100 can comprise indium phosphide (InP) or InGaAsP (In
aga
1-athe value of As, a can be about 0.53 or less).In some embodiments, substrate 100 can be at the bottom of InP-base and channel region 120 can at the bottom of Lattice Matching to described InP-base.
Refer again to Fig. 6 and 7, preliminary grid 220 can be formed on preliminary channel region 118.Preliminary grid 220 can have with the wire shaped that extends in the Y-direction of described X-direction perpendicular.Therefore, preliminary grid 220 can intersect above preliminary channel region 118.Preliminary grid 220 can comprise preliminary gate insulation layer 214, preliminary gate electrode 216 and mask pattern 218.Such as, preliminary gate insulation layer 214 can comprise oxide, and preliminary gate electrode 216 can comprise polysilicon, and mask pattern 218 can comprise the material of the etching selectivity had for preliminary gate insulation layer 214 and preliminary gate electrode 216.
Fig. 8 to 10 is for illustrating the cross-sectional view got along the line B-B ' of Fig. 6 of the intermediate structure of the part of the formation method of the integrated circuit (IC)-components of some execution modes be provided as according to the present invention's design.Refer again to Fig. 8, preliminary grid 220 can be used to etch preliminary channel region 118 to form channel region 120 as etching mask.The sidewall of preliminary grid 220 and the sidewall of channel region 120 can align each other substantially vertically.Preliminary channel region 118 can be etched until the horizontal component of the channel region 120 extended on the upper face of substrate 100 reaches predetermined thickness, as illustrated in figure 8.In other words, preliminary channel region 118 can be etched until the degree of depth through etching part of preliminary channel region 118 reaches desired depth.In some embodiments, preliminary channel region 118 can be etched until the upper face of substrate 100 is exposed.
To understand, before the preliminary channel region 118 of etching, offset spacer can be formed on the sidewall of preliminary grid 220, and when etching preliminary channel region 118, described offset spacer can be used as etching mask together with preliminary grid 220.Therefore, in some embodiments, the sidewall of channel region 120 laterally can be given prominence to from the sidewall of preliminary grid 220.In some embodiments, even if when using described offset spacer as etching mask, due to the transverse recess of the preliminary channel region 118 below described offset spacer, the sidewall of preliminary grid 220 and the sidewall of channel region 120 also can align each other substantially vertically, as illustrated in figure 8.Described offset spacer can comprise the material of the etching selectivity had for preliminary channel region 118, and described offset spacer can comprise such as silicon nitride.
Refer again to Fig. 9, barrier layer 140 can be formed on channel region 120.Epitaxial growth technology can be carried out to form barrier layer 140, and channel region 120 can be used as crystal seed layer.Barrier layer 140 can by In
y1ga
1-y1as is formed, and the value of y1 can be less than 0.53.In some embodiments, the value of y1 can in the scope of about 0.3-about 0.5, and the value of more particularly y1 can in the scope of about 0.35-about 0.4.In some embodiments, the value of y1 can be about 0.4, and barrier layer 140 can therefore by In
0.4ga
0.6as is formed.
In some embodiments, barrier layer 140 can have and substantially forms uniformly in whole barrier layer 140, makes y1 in whole barrier layer 140 can be constant.But will understand, barrier layer 140 can have variable composition.Such as, in whole barrier layer 140, indium concentration can have gradient, and y1 can be understood to the mean value of the y1 in barrier layer 140.
When making the sidewall of preliminary grid 220 and the sidewall of channel region 120 substantially align vertically each other before forming barrier layer 140, the sidewall on barrier layer 140 can align substantially vertically with the sidewall of preliminary grid 220, as illustrated in figure 9.As discussed in reference to Figure 8, in some embodiments, before formation barrier layer 140, the sidewall of channel region 120 laterally can be given prominence to from the sidewall of preliminary grid 220, and therefore the sidewall on barrier layer 140 can laterally be given prominence to from the sidewall of preliminary grid 220.The width on described barrier layer can substantially in the grade of 10nm, and in some embodiments, the width on barrier layer 140 can be about 10nm.
Refer again to Figure 10, source/drain region 160 can be formed on barrier layer 140.Source/drain region 160 can use epitaxial growth technology to be formed, and barrier layer 140 can be used as crystal seed layer.To understand, epitaxial growth technology can be carried out to form barrier layer 140 and source/drain region 160 in identical processing chamber.
Source/drain region 160 can by In
z1ga
1-z1as is formed, and the value of z1 can be greater than 0.53.In some embodiments, the value of z1 can in the scope of about 0.6-about 1.In some embodiments, the value of z1 can be about 1, and therefore source/drain region 160 can be made up of pure InAs.In some embodiments, source/drain region 160 can comprise the part comprising substantially pure InAs being adjacent to contact zone 180.In some embodiments, the part comprising substantially pure InAs of source/drain region 160 can contact described contact zone 180.
Refer again to Fig. 2, grid 240 can be formed on channel region 120.In some embodiments, such as replacement grid technique grid 240 can be used to replace preliminary grid 220.When using replacement grid technique, described method can be included on channel region 120 and on the sidewall of preliminary grid 220 and form interlayer insulating film.Sept can be formed on the contrary sidewall of preliminary grid 220 before the described interlayer insulating film of formation.Can use etch process, wet method and/or dry method etch technology remove preliminary gate insulation layer 214, preliminary gate electrode 216 and mask pattern 218, to form groove in described interlayer insulating film.Then gate insulation layer 236 and gate electrode 238 can be formed in the trench.
Disclosed theme will be considered to illustrative above, and not be restrictive, and claims intention cover all fall into the present invention's design true spirit and scope in all modification in this wise, lifting and other execution mode.Therefore, to allowing at utmost by law, the widest admissible explanation by claims and equivalent thereof determines by described scope, and should by aforementioned detailed description constraint or restriction.
Claims (22)
1. form the method for fin FETs, described method comprises:
Substrate is formed the fin-shaped channel region comprising indium (In);
Form the deep/source drain extensions being adjacent to described channel region on the substrate; With
Source/drain extension area is formed between described channel region and described deep/source drain extensions, wherein:
The contrary sidewall of described source/drain extension area contacts described channel region and described deep/source drain extensions respectively; With
Described source/drain extension area comprises In
yga
1-yas, and y is in the scope of about 0.3-about 0.5.
2. the indium concentration that the process of claim 1 wherein in described channel region is greater than the indium concentration in described source/drain extension area.
3. the method for claim 2, wherein forms described channel region and comprises formation and comprise In
xga
1-xthe channel region of As, and x is in the scope of about 0.5-about 0.6.
4. the method for claim 3, wherein x is about 0.53.
5. the method for claim 4, wherein y is about 0.4.
6. the method for claim 3, the indium concentration in wherein said deep/source drain extensions is greater than the indium concentration in described channel region.
7. the method for claim 6, wherein forms described deep/source drain extensions and comprises formation and comprise In
zga
1-zthe deep/source drain extensions of As, z is in the scope of about 0.6-about 1.
8. the method for claim 6, comprise the contact zone of the upper face forming the described deep/source drain extensions of contact further, a part for wherein said deep/source drain extensions contacts described contact zone and comprises pure InAs.
9. the method for claim 3, wherein said substrate comprises at the bottom of InP-base or In
aga
1-aas, and a is about 0.53 or less.
10. the method for claim 3, wherein:
Described substrate comprises at the bottom of InP-base; With
In is comprised described in formation
xga
1-xthe channel region of As comprises the In formed at the bottom of Lattice Matching to described InP-base
xga
1-xas pattern.
11. the process of claim 1 wherein that the described channel region of formation and described source/drain extension area comprise:
Form preliminary channel region on the substrate;
Described preliminary channel region forms mask pattern;
Use described mask pattern as the described preliminary channel region of etching mask etching to form described channel region; With
Use described channel region as source/drain extension area described in crystal seed layer epitaxial growth.
12. the process of claim 1 wherein that forming described deep/source drain extensions comprises the described source/drain extension area of use as deep/source drain extensions described in crystal seed layer epitaxial growth.
13. the process of claim 1 wherein:
Form described deep/source drain extensions and comprise the first deep/source drain extensions being formed and be adjacent to the first side wall of described channel region, make the contrary sidewall of described source/drain extension area contact the first side wall of described channel region and the sidewall of described first deep/source drain extensions respectively; With
Described method comprises the second dark second source/drain region of the second sidewall forming the contact described channel region contrary with the first side wall of described channel region further.
14. the process of claim 1 wherein that described source/drain extension area is about 10nm at the width on from described channel region to the direction of described deep/source drain extensions.
The method of 15. claims 1, comprise the gate electrode being formed and overlay on above described channel region further, wherein contact one of contrary sidewall of the described source/drain extension area of the sidewall of described channel region substantially to align with the sidewall of described gate electrode, make to form knot in described source/drain extension area.
The method of 16. formation fin FETs, described method comprises:
Substrate is formed the fin-shaped channel region comprising the first semi-conducting material;
Source/drain region is formed on the substrate on the sidewall of described channel region; With
Barrier layer is formed between the sidewall of the sidewall in described channel region and described source/drain region, wherein:
Described barrier layer comprises described first semi-conducting material and the second semi-conducting material; With
The first semi-conducting material concentration in described barrier layer is less than the first semi-conducting material concentration in described channel region.
The method of 17. claims 16, the first semi-conducting material concentration in wherein said source/drain region is different with the described first semi-conducting material concentration in described barrier layer.
The method of 18. claims 17, wherein:
Described first semi-conducting material comprises indium (In), and described second semi-conducting material comprises gallium (Ga); With
Described first semi-conducting material concentration in described source/drain region is greater than the described first semi-conducting material concentration in described channel region.
The method of 19. claims 18, wherein forms described channel region and comprises formation and comprise In
xga
1-xthe channel region of As, and x is in the scope of about 0.5-about 0.6.
The method of 20. claims 16, wherein forms described channel region and described barrier layer and comprises:
Form preliminary channel region on the substrate;
Described preliminary channel region forms mask pattern;
Use described mask pattern as the described preliminary channel region of etching mask etching to form described channel region; With
Use described channel region as barrier layer described in crystal seed layer epitaxial growth.
The method of 21. claims 16, wherein:
Formed on the first side wall that described source/drain region is included in described channel region and form the first source/drain region, make described barrier layer be arranged between the first side wall of described channel region and the sidewall of described first source/drain region; With
Described method comprises the second source/drain region of the second sidewall forming the contact described channel region contrary with the first side wall of described channel region further.
The method of 22. claims 16, wherein said barrier layer is about 10nm at the width on from described channel region to the direction of described source/drain region.
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| KR102175767B1 (en) | 2020-11-06 |
| KR20150126310A (en) | 2015-11-11 |
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