CN203386754U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203386754U CN203386754U CN201320502762.2U CN201320502762U CN203386754U CN 203386754 U CN203386754 U CN 203386754U CN 201320502762 U CN201320502762 U CN 201320502762U CN 203386754 U CN203386754 U CN 203386754U
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Abstract
The utility model discloses an array substrate and a display device. The array substrate comprises a substrate, a pixel zone, and a peripheral zone, wherein the pixel zone and the peripheral zone are respectively formed on the substrate, and the peripheral zone is located at the periphery of the pixel zone. The pixel zone comprises an amorphous silicon film transistor. The peripheral zone comprises a low-temperature polysilicon structure. The display device comprises the array substrate. In the technical scheme of the utility model, the array substrate comprises the substrate, the pixel zone, and the peripheral zone, wherein the pixel zone and the peripheral zone are respectively formed on the substrate, and the peripheral zone is located at the periphery of the pixel zone. The pixel zone comprises the amorphous silicon film transistor. The peripheral zone comprises the low-temperature polysilicon structure. Because the pixel zone employs the amorphous silicon film transistor, a problem that leak current in the pixel zone of a low-temperature polysilicon array substrate in the prior art is too high is solved, thereby reducing the leak current of the pixel zone. An LTPS structure is disposed in the peripheral zone, thereby achieving a design of a narrow frame of the display device.
Description
Technical field
The utility model relates to the Display Technique field, particularly a kind of array base palte and display unit.
Background technology
In the Display Technique field, (Low Temperature Poly-silicon, be called for short: LTPS) the technology application is comparatively extensive for amorphous silicon (a-Si) technology and low temperature polycrystalline silicon.Wherein, along with the development of Display Technique, the LTPS technology relies on its high-effect and characteristics high definition, has obtained application more and more widely.
In prior art, when adopting the LTPS technology to make array base palte, there is the excessive problem of leakage current in its pixel region; When adopting amorphous silicon (a-Si) technology to make array base palte, the picture construction of its surrounding zone makes display unit be difficult to realize narrow frame design.
In sum, in prior art, also do not have a kind ofly when reducing the pixel region leakage current, can make display unit realize the technical scheme of narrow frame design.
The utility model content
The utility model provides a kind of array base palte and display unit, for reducing the leakage current of pixel region, and realizes the narrow frame design of display unit.
For achieving the above object, the utility model provides a kind of array base palte, comprise: underlay substrate and be formed at pixel region and the surrounding zone on described underlay substrate, described surrounding zone is positioned at the periphery of described pixel region, described pixel region comprises: amorphous silicon film transistor, described surrounding zone comprises: the low temperature polycrystalline silicon structure.
Alternatively, described amorphous silicon film transistor comprises the bottom gate type amorphous silicon film transistor.
Alternatively, described low temperature polycrystalline silicon structure comprises low-temperature polysilicon film transistor.
Alternatively, described low-temperature polysilicon film transistor comprises the top gate type low-temperature polysilicon film transistor.
Alternatively, on described underlay substrate, be formed with resilient coating, described resilient coating is positioned at described pixel region and described surrounding zone.
Alternatively, described amorphous silicon film transistor comprises amorphous silicon active layer figure, and described low-temperature polysilicon film transistor comprises low temperature polycrystalline silicon active layer figure, and described amorphous silicon active layer figure and described low temperature polycrystalline silicon active layer figure arrange with layer.
For achieving the above object, the utility model provides a kind of display unit, comprising: above-mentioned array base palte.
The utlity model has following beneficial effect:
In the array base palte that the utility model provides and the technical scheme of display unit, array base palte comprises underlay substrate and is formed at pixel region and the surrounding zone on underlay substrate, surrounding zone is positioned at the periphery of pixel region, pixel region comprises the a-si thin-film transistor, surrounding zone comprises the LTPS structure, because pixel region has adopted the a-si thin-film transistor, therefore overcome the excessive problem of pixel region leakage current that in the prior art, the LTPS array base palte exists, thereby reduced the leakage current of pixel region.Be provided with the LTPS structure in surrounding zone, thereby realized the narrow frame design of display unit.
The accompanying drawing explanation
The structural representation of a kind of array base palte that Fig. 1 provides for the utility model embodiment mono-;
The flow chart of the manufacture method of a kind of array base palte that Fig. 2 provides for the utility model embodiment tri-;
Fig. 3 a forms the schematic diagram of the grid of a-Si thin-film transistor in embodiment tri-;
Fig. 3 b forms the schematic diagram of gate insulation layer in embodiment tri-;
Fig. 3 c forms the schematic diagram of a-Si material layer in embodiment tri-;
Fig. 3 d forms the schematic diagram of LTPS material layer in embodiment tri-;
Fig. 3 e forms the schematic diagram of a-Si figure and LTPS figure in embodiment tri-;
Fig. 3 f forms the schematic diagram of gate insulation figure in embodiment tri-;
Fig. 3 g forms the schematic diagram of the grid of LTPS thin-film transistor in embodiment tri-;
Fig. 3 h forms the schematic diagram of LDD figure in embodiment tri-;
Fig. 3 i is the schematic diagram that forms N-shaped doping figure in embodiment tri-;
Fig. 3 j is the schematic diagram that forms p-type doping figure in embodiment tri-;
Fig. 3 k forms the schematic diagram of ILD figure in embodiment tri-;
Fig. 3 l is the schematic diagram that forms source electrode, drain electrode and source-drain electrode figure in embodiment tri-;
Fig. 3 m forms the schematic diagram of passivation layer in embodiment tri-.
Embodiment
For making those skilled in the art understand better the technical solution of the utility model, the array base palte and the display unit that the utility model are provided below in conjunction with accompanying drawing are described in detail.
The structural representation of a kind of array base palte that Fig. 1 provides for the utility model embodiment mono-, as shown in Figure 1, this array base palte comprises: underlay substrate 1 and be formed at pixel region and the surrounding zone on underlay substrate 1, surrounding zone is positioned at the periphery of pixel region, pixel region comprises: amorphous silicon (a-si) thin-film transistor, surrounding zone comprises: low temperature polycrystalline silicon (LTPS) structure.
It should be noted that: the pixel region in Fig. 1 and surrounding zone have all only drawn part-structure, it should be apparent to those skilled in the art that in Fig. 1 that drawn pixel region and surrounding zone all should not become the restriction to pixel region structure and surrounding zone structure; In addition, the dotted line in Fig. 1, only in order clearly to express pixel region and surrounding zone, is not the part of array base-plate structure.
In the present embodiment, preferably, the a-Si thin-film transistor comprises bottom gate type a-Si thin-film transistor, and the LTPS structure comprises the LTPS thin-film transistor.Wherein, the LTPS thin-film transistor comprises top gate type LTPS thin-film transistor.
In actual applications, alternatively, the a-Si thin-film transistor can also comprise: top gate type thin film transistor, and the LTPS thin-film transistor can also comprise: bottom gate type LTPS thin-film transistor.
In the present embodiment, the a-Si thin-film transistor comprises a-Si active layer figure, and the LTPS thin-film transistor comprises LTPS active layer figure.Preferably, a-Si active layer figure and LTPS active layer figure arrange with layer.
Alternatively, be formed with resilient coating 2 on underlay substrate 1, resilient coating 2 is positioned at pixel region and surrounding zone.Resilient coating 2 can effectively improve the performance of LTPS thin-film transistor.
In the present embodiment, particularly, pixel region can comprise: the pixel cell that grid line and data wire limit, pixel cell comprises: a-Si thin-film transistor and the pixel electrode 3 be connected with this a-Si thin-film transistor.In the present embodiment, the a-Si thin-film transistor comprises bottom gate type a-Si thin-film transistor, particularly, the a-Si thin-film transistor can comprise: grid 4, a-Si active layer figure 5, source electrode 6 and drain 7, grid 4 is formed on resilient coating 2, a-Si active layer figure 5 is formed on grid 4, and source electrode 6 and drain electrode 7 all are formed on a-Si active layer figure 5, drains 7 with pixel electrode 3, to be connected.Wherein, a-Si active layer figure 5 comprises: a-Si figure 51 and be positioned at N+a-Si figure 52 and the N+a-Si figure 53 on a-Si figure 51, source electrode 6 is positioned on N+a-Si figure 52, drain electrode 7 is positioned on N+a-Si figure 53, N+a-Si figure 52 can reduce the contact resistance of source electrode 6, N+a-Si figure 53 7 the contact resistance that can reduce to drain.Array base palte also can comprise: gate insulation layer 8; gate insulation layer 8 is between grid 4 and a-Si active layer figure 5; gate insulation layer 8 covers whole underlay substrate 1; therefore gate insulation layer 8 is arranged in pixel region and surrounding zone, the performance that gate insulation layer 8 can be used for protecting the grid 4 of pixel region and promotes the LTPS thin-film transistor.Array base palte can also comprise: passivation layer 9, passivation layer 9 is positioned on source electrode 6 and drain electrode 7, and covers whole underlay substrate 1, so passivation layer 9 is arranged in pixel region and surrounding zone.Drain on the passivation layer 9 of 7 tops and be provided with via hole, pixel electrode 3 is filled in via hole, to realize pixel electrode 3, with drain electrode 7, is connected.
In the present embodiment, particularly, surrounding zone can comprise: LTPS thin-film transistor 10 and LTPS thin-film transistor 11.LTPS thin-film transistor 10 comprises: LTPS active layer figure 101, grid 102, source-drain electrode figure 103 and source-drain electrode figure 104, LTPS active layer figure 101 is positioned on gate insulation layer 8, source-drain electrode figure 103 and source-drain electrode figure 104 are positioned on LTPS active layer figure 101, grid 102 is positioned on LTPS active layer figure 101, and grid 102 is between source-drain electrode figure 103 and source-drain electrode figure 104.LTPS active layer figure 101 comprises: LTPS spirte 1011, the N-shaped doping figure 1012 that is positioned at LTPS spirte 1011 both sides and N-shaped doping figure 1013.LTPS thin-film transistor 11 comprises: LTPS active layer figure 111, grid 112, source-drain electrode figure 113 and source-drain electrode figure 114, LTPS active layer figure 111 is positioned on gate insulation layer 8, source-drain electrode figure 113 and source-drain electrode figure 114 are positioned on LTPS active layer figure 111, grid 112 is positioned on LTPS active layer figure 111, and grid 112 is between source-drain electrode figure 113 and source-drain electrode figure 114.LTPS active layer figure 111 comprises: LTPS spirte 1111, the p-type doping figure 1112 that is positioned at LTPS spirte 1111 both sides and p-type doping figure 1113.Array base palte also comprises: gate insulation figure 12, gate insulation figure 12 is positioned on LTPS active layer figure 101 and LTPS active layer figure 111, and is positioned under grid 102 and grid 112.Array base palte also comprises: (Inter Layer Dielectric, be called for short: ILD) figure 13, and ILD figure 13 is positioned on grid 102 and grid 112 for inner protective layer.Be provided with a plurality of via holes on gate insulation figure 12 and ILD figure 13, source-drain electrode figure 103 is filled in via hole to realize that source-drain electrode figure 103 is connected with N-shaped doping figure 1012, source-drain electrode figure 104 is filled in via hole to realize that source-drain electrode figure 104 is connected with N-shaped doping figure 1013, source-drain electrode figure 113 is filled in via hole to realize that source-drain electrode figure 113 and p-type doping figure 1112 are connected, and source-drain electrode figure 114 is filled in via hole to realize that source-drain electrode figure 114 and the p-type figure 1113 that adulterates is connected.In the present embodiment, LTPS active layer figure 101 and LTPS active layer figure 111 are one-body molded, and source-drain electrode figure 104 and source-drain electrode figure 113 are one-body molded.In actual applications, source-drain electrode figure 104 and source-drain electrode figure 113 can also arrange separately, and source-drain electrode figure 104 does not contact with source-drain electrode figure 113; In actual applications, LTPS active layer figure 101 and LTPS active layer figure 111 also can arrange separately, and LTPS active layer figure 101 does not contact with LTPS active layer figure 111.As a kind of preferred version, in the present embodiment, source-drain electrode figure 103 can be drain electrode, and source-drain electrode figure 104 can be source electrode, and source-drain electrode figure 113 can be source electrode, and source-drain electrode figure 114 can be drain electrode.
In the present embodiment, because LTPS active layer figure 101 comprises: N-shaped doping figure 1012 and N-shaped doping figure 1013, LTPS active layer figure 111 comprises: p-type doping figure 1112 and p-type doping figure 1113, therefore LTPS thin-film transistor 10 and LTPS thin-film transistor 11 form complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, hereinafter to be referred as: CMOS), the advantage of this CMOS is low in energy consumption.
In actual applications, alternatively, all can only comprise N-shaped doping figure in LTPS active layer figure in all LTPS thin-film transistors of surrounding zone, or all can only comprise p-type doping figure in the LTPS active layer figure in all LTPS thin-film transistors of surrounding zone.
In actual applications, alternatively, the LTPS structure can also comprise: LTPS active layer figure and metal wire, preferably, metal wire is positioned on LTPS active layer figure.Metal wire can comprise: metallic test line and/or metal lead wire.It should be noted that: this kind of situation no longer specifically draws.
The array base palte that the present embodiment provides comprises underlay substrate and is formed at pixel region and the surrounding zone on underlay substrate, surrounding zone is positioned at the periphery of pixel region, pixel region comprises the a-si thin-film transistor, surrounding zone comprises the LTPS structure, because pixel region has adopted the a-si thin-film transistor, therefore overcome the excessive problem of pixel region leakage current that in the prior art, the LTPS array base palte exists, thereby reduced the leakage current of pixel region.Be provided with the LTPS structure in surrounding zone, thereby realized the narrow frame design of display unit.
The utility model embodiment bis-provides a kind of display unit, and this display unit comprises: array base palte.Wherein, array base palte can adopt the array base palte in above-described embodiment one, no longer specifically describes herein.Preferably, display unit can for senior super Wei Chang conversion, (Advanced Super Dimension Switch be called for short: ADS) device.
The utility model embodiment tri-provides a kind of manufacture method of array base palte, and the method comprises: form pixel region and surrounding zone on underlay substrate, surrounding zone is positioned at the periphery of pixel region, and pixel region comprises the a-Si thin-film transistor, and surrounding zone comprises the LTPS structure.
In the present embodiment, preferably, the LTPS structure comprises the LTPS thin-film transistor.On underlay substrate, formation pixel region and surrounding zone specifically can comprise: form a-Si thin-film transistor and LTPS thin-film transistor on underlay substrate.Wherein, on underlay substrate, formation a-Si thin-film transistor and LTPS thin-film transistor comprise: form grid, source electrode, drain electrode and the amorphous silicon active layer figure of amorphous silicon film transistor and grid, source-drain electrode figure and the low temperature polycrystalline silicon active layer figure of LTPS thin-film transistor on underlay substrate, amorphous silicon active layer figure and low temperature polycrystalline silicon active layer figure arrange with layer.
The manufacture method of the array base palte that the present embodiment provides is included on underlay substrate and forms pixel region and surrounding zone, surrounding zone is positioned at the periphery of pixel region, pixel region comprises the a-Si thin-film transistor, surrounding zone comprises the LTPS structure, because pixel region has adopted the a-si thin-film transistor, therefore overcome the excessive problem of pixel region leakage current that in the prior art, the LTPS array base palte exists, thereby reduced the leakage current of pixel region.Be provided with the LTPS structure in surrounding zone, thereby realized the narrow frame design of display unit.
The manufacture method of the array base palte provided below by tri-pairs of the utility model of embodiment is described in detail.The present embodiment be take the a-Si thin-film transistor and is comprised that bottom gate type a-Si thin-film transistor and LTPS thin-film transistor comprise that top gate type LTPS thin-film transistor is described as example.
The flow chart of the manufacture method of a kind of array base palte that Fig. 2 provides for the utility model embodiment tri-, as shown in Figure 2, the method comprises:
Fig. 3 a forms the schematic diagram of the grid of a-Si thin-film transistor in embodiment tri-, as shown in Figure 3 a, on underlay substrate 1, form gate metal layer, and gate metal layer is carried out to composition technique, forms grid 4 on underlay substrate 1.Alternatively, before forming grid 4, can also form resilient coating 2 on underlay substrate 1, this resilient coating 2 is positioned at the below of grid 4.
Fig. 3 b forms the schematic diagram of gate insulation layer in embodiment tri-, as shown in Fig. 3 b, form gate insulation layer 8 by chemical vapor deposition above grid 4.
In the present embodiment, step 103 specifically comprises:
Step 1031, form the a-Si material layer above gate insulation layer.
Fig. 3 c forms the schematic diagram of a-Si material layer in embodiment tri-, as shown in Figure 3 c, form a-Si material layer 14 by chemical vapor deposition on gate insulation layer 8.
Step 1032, by UV substrate (glass), pixel region is blocked, the a-Si material layer that is positioned at surrounding zone is carried out to the laser crystallization processing, to form the LTPS material layer in surrounding zone.
Fig. 3 d forms the schematic diagram of LTPS material layer in embodiment tri-, as shown in Figure 3 d, by UV substrate (glass), pixel region is blocked, and the a-Si material layer that is positioned at surrounding zone is carried out to the laser crystallization processing, to form LTPS material layer 15 in surrounding zone.
Step 1033, the a-Si material layer that is positioned at pixel region and the LTPS material layer that is positioned at surrounding zone are carried out to composition technique, at pixel region, form the a-Si figure and form the LTPS figure in surrounding zone.
Fig. 3 e forms the schematic diagram of a-Si figure and LTPS figure in embodiment tri-, as shown in Figure 3 e, by composition technique, at pixel region, form a-Si figure 51 and form LTPS figure 16 in surrounding zone.Alternatively, if a-Si active layer figure 5 also comprises: N+a-Si figure 52 and N+a-Si figure 53, after step 1033, also comprise: form the N+a-Si material layer by chemical vapor deposition above a-Si figure 51, the N+a-Si material layer is carried out to composition technique, to form N+a-Si figure 52 and N+a-Si figure 53 on a-Si figure 51.
Fig. 3 f forms the schematic diagram of gate insulation figure in embodiment tri-, as shown in Fig. 3 f, by chemical vapor deposition, above the LTPS figure, form gate insulation layer, and gate insulation layer is carried out to composition technique, to form gate insulation figure 12 above LTPS figure 16.The material of gate insulation figure 12 is SiNx.
Fig. 3 g forms the schematic diagram of the grid of LTPS thin-film transistor in embodiment tri-, as shown in Fig. 3 g, form gate metal layer by physical vapor deposition above gate insulation figure 12, gate metal layer is carried out to composition technique, form grid 102 and grid 112 on gate insulation figure 12.
In the present embodiment, step 106 specifically comprises:
Step 1061, LTPS figure 16 is carried out to lightly doped drain (Lightly Doped Drain region, be called for short: LDD) doping, the LTPS spirte 1011 and the LTPS spirte 1111 that is positioned at grid 112 belows that form LDD figure 161 and be positioned at grid 102 belows, as shown in Fig. 3 h, Fig. 3 h forms the schematic diagram of LDD figure in embodiment tri-.
Particularly, apply one deck photoresist on underlay substrate, by composition technique, form photoetching offset plate figure in pixel region, this photoetching offset plate figure covers pixel region, with each structure graph for the protection of in pixel region; LTPS figure 16 is carried out to the LDD doping; Remove photoetching offset plate figure.
Step 1062, LDD figure 161 is carried out to the N-shaped doping, form N-shaped doping figure 1012 and N-shaped doping figure 1013, as shown in Fig. 3 i, Fig. 3 i is the schematic diagram that forms N-shaped doping figure in embodiment tri-.
Particularly, apply one deck photoresist on underlay substrate, by composition technique, in non-doped region, form photoetching offset plate figure, this photoetching offset plate figure covers non-doped region, with each structure graph for the protection of in non-doped region; LDD figure 161 is carried out to the N-shaped doping; Remove photoetching offset plate figure.
Step 1063, LDD figure 161 is carried out to the p-type doping, form p-type doping figure 1112 and p-type doping figure 1113, as shown in Fig. 3 j, Fig. 3 j is the schematic diagram that forms p-type doping figure in embodiment tri-.
Particularly, apply one deck photoresist on underlay substrate, by composition technique, in non-doped region, form photoetching offset plate figure, this photoetching offset plate figure covers non-doped region, with each structure graph for the protection of in non-doped region; LDD figure 161 is carried out to the p-type doping; Remove photoetching offset plate figure.
In sum, the LTPS active layer figure 101 formed by step 106 comprises: LTPS spirte 1011, the N-shaped doping figure 1012 that is positioned at LTPS spirte 1011 both sides and N-shaped doping figure 1013, the LTPS active layer figure 111 of formation comprises: LTPS spirte 1111, the p-type doping figure 1112 that is positioned at LTPS spirte 1111 both sides and p-type doping figure 1113.
Fig. 3 k forms the schematic diagram of ILD figure in embodiment tri-, as shown in Fig. 3 k, above grid 102 and grid 112, deposition ILD material layer, carry out composition technique to the ILD material layer, forms ILD figure 13.
Figure 31 is the schematic diagram that forms source electrode, drain electrode and source-drain electrode figure in embodiment tri-, as shown in figure 31, step 109 specifically comprises: form the source-drain electrode metal level above the ILD figure, the source-drain electrode metal level is carried out to composition technique, form source electrode 6, drain 7, source-drain electrode figure 103, source-drain electrode figure 104, source-drain electrode figure 113 and source-drain electrode figure 114.Further, before execution step 109, also comprise: form a plurality of via holes on the ILD figure, source-drain electrode figure 103 is filled in via hole to realize that source-drain electrode figure 103 is connected with N-shaped doping figure 1012, source-drain electrode figure 104 is filled in via hole to realize that source-drain electrode figure 104 is connected with N-shaped doping figure 1013, source-drain electrode figure 113 is filled in via hole to realize that source-drain electrode figure 113 and p-type doping figure 1112 are connected, and source-drain electrode figure 114 is filled in via hole to realize that source-drain electrode figure 114 and the p-type figure 1113 that adulterates is connected.
Fig. 3 m forms the schematic diagram of passivation layer in embodiment tri-, as shown in Fig. 3 m, at source electrode 6, drain 7, source-drain electrode figure 103, source-drain electrode figure 104, source-drain electrode figure 113 and source-drain electrode figure 114 above form passivation layer 9, this passivation layer 9 covers whole array base palte.
As shown in Figure 1, step 111 specifically can comprise: form via hole on passivation layer 9, via hole is positioned at drain electrode 7 tops; Form the pixel electrode material layer on passivation layer 9; The pixel electrode material layer is carried out to composition technique, form pixel electrode 3, this pixel electrode 3 is filled in via hole to realize and drains 7 be connected.
Preferably, composition technique described in the utility model can comprise: the techniques such as photoresist coating, exposure, development, etching, photoresist lift off.
It should be noted that: in the present embodiment, the execution sequence of each step can be changed according to actual needs.
The manufacture method of the array base palte that the present embodiment provides is included on underlay substrate and forms pixel region and surrounding zone, surrounding zone is positioned at the periphery of pixel region, pixel region comprises the a-Si thin-film transistor, surrounding zone comprises the LTPS structure, because pixel region has adopted the a-si thin-film transistor, therefore overcome the excessive problem of pixel region leakage current that in the prior art, the LTPS array base palte exists, thereby reduced the leakage current of pixel region.Be provided with the LTPS structure in surrounding zone, thereby realized the narrow frame design of display unit.
Be understandable that, above execution mode is only the illustrative embodiments adopted for principle of the present utility model is described, yet the utility model is not limited to this.For those skilled in the art, in the situation that do not break away from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement also are considered as protection range of the present utility model.
Claims (7)
1. an array base palte, comprise: underlay substrate and be formed at pixel region and the surrounding zone on described underlay substrate, described surrounding zone is positioned at the periphery of described pixel region, it is characterized in that, described pixel region comprises: amorphous silicon film transistor, described surrounding zone comprises: the low temperature polycrystalline silicon structure.
2. array base palte according to claim 1, is characterized in that, described amorphous silicon film transistor comprises the bottom gate type amorphous silicon film transistor.
3. array base palte according to claim 1, is characterized in that, described low temperature polycrystalline silicon structure comprises low-temperature polysilicon film transistor.
4. array base palte according to claim 3, is characterized in that, described low-temperature polysilicon film transistor comprises the top gate type low-temperature polysilicon film transistor.
5. array base palte according to claim 1, is characterized in that, on described underlay substrate, is formed with resilient coating, and described resilient coating is positioned at described pixel region and described surrounding zone.
6. array base palte according to claim 3, it is characterized in that, described amorphous silicon film transistor comprises amorphous silicon active layer figure, described low-temperature polysilicon film transistor comprises low temperature polycrystalline silicon active layer figure, and described amorphous silicon active layer figure and described low temperature polycrystalline silicon active layer figure arrange with layer.
7. a display unit, is characterized in that, comprising: the arbitrary described array base palte of the claims 1 to 6.
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| CN201320502762.2U CN203386754U (en) | 2013-08-16 | 2013-08-16 | Array substrate and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456739A (en) * | 2013-08-16 | 2013-12-18 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN108682372A (en) * | 2018-04-03 | 2018-10-19 | 京东方科技集团股份有限公司 | Array substrate and its driving method, display device |
-
2013
- 2013-08-16 CN CN201320502762.2U patent/CN203386754U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456739A (en) * | 2013-08-16 | 2013-12-18 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2015021708A1 (en) * | 2013-08-16 | 2015-02-19 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, display panel, and display apparatus |
| US9508757B2 (en) | 2013-08-16 | 2016-11-29 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display panel and display apparatus |
| CN108682372A (en) * | 2018-04-03 | 2018-10-19 | 京东方科技集团股份有限公司 | Array substrate and its driving method, display device |
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