CN107180764B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

Info

Publication number
CN107180764B
CN107180764B CN201610140142.7A CN201610140142A CN107180764B CN 107180764 B CN107180764 B CN 107180764B CN 201610140142 A CN201610140142 A CN 201610140142A CN 107180764 B CN107180764 B CN 107180764B
Authority
CN
China
Prior art keywords
semiconductor substrate
source
ldd
region
hard mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610140142.7A
Other languages
Chinese (zh)
Other versions
CN107180764A (en
Inventor
赵猛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201610140142.7A priority Critical patent/CN107180764B/en
Publication of CN107180764A publication Critical patent/CN107180764A/en
Application granted granted Critical
Publication of CN107180764B publication Critical patent/CN107180764B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the method comprises the following steps: providing a semiconductor substrate, and performing source-drain injection and annealing to form a source-drain injection region in the semiconductor substrate; forming a patterned hard mask layer on the source and drain injection region, and etching the source and drain injection region which is not shielded by the hard mask layer until the semiconductor substrate is exposed; forming a side wall on the side wall of the groove formed by etching; forming a gate structure to completely fill the remaining portion of the trench; after removing the side wall and the hard mask layer, performing LDD injection to form LDD injection regions in the semiconductor substrate at two sides of the grid structure; and forming a contact hole etching stop layer to cover the gate structure and the semiconductor substrate. According to the invention, the LDD implantation can obtain a shallower LDD implantation area so as to effectively inhibit the short channel effect; meanwhile, larger stress can be obtained in a channel region, so that the performance of the MOS device is obviously improved.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
As the feature size of MOS devices continues to decrease, the control of sufficiently effective channel lengths for MOS devices during their fabrication becomes increasingly challenging. Therefore, the method for forming the ultra-shallow junction and the abrupt junction in the MOS device can improve the short channel effect of the core device. However, in the process of forming ultra-shallow junctions and abrupt junctions, it is also a very challenging task to find a more reasonable balance point between suppressing short channel effects and improving the performance of MOS devices.
Therefore, a method is needed to solve the above problems.
Disclosure of Invention
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and performing source-drain injection and annealing to form a source-drain injection region in the semiconductor substrate;
forming a patterned hard mask layer on the source-drain injection region, and etching the source-drain injection region which is not shielded by the hard mask layer until the semiconductor substrate is exposed;
forming a side wall on the side wall of the groove formed by etching;
forming a gate structure to completely fill the remaining portion of the trench;
and after removing the side wall and the hard mask layer, performing LDD injection to form LDD injection regions in the semiconductor substrate at two sides of the grid structure.
In one example, a height of the gate structure is greater than a depth of the trench.
In one example, the gate structure includes a gate dielectric layer and a gate material layer stacked from bottom to top.
In one example, the side wall and the hard mask layer are made of the same material.
In one example, the removing is performed using wet etching.
In one example, after the LDD implantation is performed, a step of forming a contact hole etch stop layer covering sidewalls of the gate structure and the semiconductor substrate is further included.
In one example, before the source and drain implantation is performed, a step of performing well region implantation to form a well region in the semiconductor substrate is further included.
In one example, for NMOS, the dopant ions of the LDD implant are phosphorous ions or arsenic ions; for PMOS, the dopant ions for the LDD implant are either boron or indium ions.
In one embodiment, the present invention also provides a semiconductor device manufactured by the above method.
In one embodiment, the present invention also provides an electronic apparatus including the semiconductor device.
According to the invention, the height of the formed gate structure is larger than the depth of the formed groove, and the LDD implantation can obtain a shallower LDD implantation area, so that a shallower implantation junction can be obtained compared with the prior art, and the short channel effect can be effectively inhibited; meanwhile, larger stress can be obtained in a channel region, so that the performance of the MOS device is obviously improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a schematic cross-sectional view of a device obtained after LDD implantation and source-drain implantation are performed in sequence according to the prior art;
fig. 2A-2G are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention;
FIG. 3 is a flowchart illustrating sequential steps performed by a method according to a first exemplary embodiment of the present invention;
fig. 4 is a schematic diagram of an electronic device according to a third exemplary embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As shown in fig. 1, which is a schematic cross-sectional view of a device obtained after LDD implantation and source-drain implantation are sequentially performed according to the prior art.
A gate structure 110 is formed on the semiconductor substrate 100, and the gate structure 110 includes, as an example, a gate dielectric layer, a gate material layer, and a gate hard mask layer, which are sequentially stacked. The gate dielectric layer comprises an oxide layer, such as silicon dioxide (SiO)2) And (3) a layer. The gate material layer comprises one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer and a metal silicide layer, wherein the metal layer can be made of tungsten (W), nickel (Ni) or titanium (Ti); the conductive metal nitride layer includes a titanium nitride (TiN) layer; the conductive metal oxide layer comprises iridium oxide (IrO)2) A layer; the metal silicide layer includes a titanium silicide (TiSi) layer. The gate hard mask layer comprises one or more of an oxide layer, a nitride layer, an oxynitride layer and amorphous carbon, wherein the oxide layer is made of Boron Phosphorus Silicon Glass (BPSG), Phosphorus Silicon Glass (PSG), Tetraethoxysilane (TEOS), Undoped Silicon Glass (USG), spin-on glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); the nitride layer comprises silicon nitride (Si)3N4) A layer; the oxynitride layer includes a silicon oxynitride (SiON) layer. The gate dielectric layer, the gate material layer, and the gate hard mask layer may be formed by any conventional technique known to those skilled in the art, preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD). Sidewall structures 111 are also formed on the semiconductor substrate 100 on both sides of the gate structure 110 and next to the gate structure 110, wherein the sidewall structures 111 are made of oxide, nitride or a combination of the two.
LDD implant regions 101 are formed in the semiconductor substrate 100 on both sides of the gate structure 110. In the prior art, a MOS transistor is taken as an example, and LDD implantation is performed on a semiconductor substrate 100 using a gate structure 110 as a mask to form an LDD implantation region 101.
When the MOS transistor is an NMOS transistor, the doping ions implanted by the LDD may be phosphorus ions or arsenic ions.
By way of example, when the doping ions of the LDD implant are phosphorus ions, the energy range of the ion implantation is 1keV-20keV, and the dose of the ion implantation is 1.0 × e14-1.0×e15cm-2When the doped ion of the LDD implant is arsenic ion, the energy range of the ion implantation is 2keV-35keV, and the dose of the ion implantation is 1.0 × e14-1.0×e15cm-2。
When the MOS transistor is a PMOS transistor, the doping ions for LDD implantation may be boron ions or indium ions.
By way of example, when the dopant ions of the LDD implant are boron ions, the energy range of the ion implantation is 0.5keV to 10keV, and the dose of the ion implantation is 1.0 × e14-1.0×e15cm-2When the doping ions of the LDD implant are indium ions, the energy range of the ion implantation is 10keV-70keV, and the dose of the ion implantation is 1.0 × e14-1.0×e15cm-2。
After the LDD implantation is performed, a pocket ion implantation step is performed on the semiconductor substrate 100 to form a pocket in the semiconductor substrate 100, which encloses the LDD implantation region 101. The pocket region ion implantation has a depth slightly greater than that of the LDD implantation, and the ion conductivity type of the pocket region ion implantation is opposite to that of the LDD implantation. Under the selected ion implantation angle, the rotation implantation is carried out, so that the shadow effect can be reduced and symmetrical impurity distribution is formed, the ion implantation energy, the dosage and the angle are correspondingly matched with the energy, the dosage and the angle of the low-doped ion implantation, and the implantation energy ensures that the formed pocket region wraps the LDD implantation region 101, so that the short channel effect caused by Drain Induced Barrier Lowering (DIBL) is effectively inhibited.
When the MOS transistor is an NMOS transistor, the dopant ions implanted into the pocket region may be boron ions or indium ions.
By way of example, when the doped ions of the pocket region ion implantation are boron ions, the energy range of the ion implantation is 3keV-20keV, and the dose of the ion implantation is 1.0 × e13-9.0×e13cm-2The incident direction of the ion implantation is shifted by a certain angle with respect to a direction perpendicular to the semiconductor substrate 100, and the angle ranges from 0 degree to 45 degrees.
As an example, when the doped ions of the pocket region ion implantation are indium ions, the energy range of the ion implantation is 100keV to 150keV, and the dose of the ion implantation is 1.0 × e13-9.0×e13cm-2The incident direction of the ion implantation is shifted by a certain angle with respect to a direction perpendicular to the semiconductor substrate 100, and the angle ranges from 0 degree to 45 degrees.
When the MOS transistor is a PMOS transistor, the dopant ions implanted into the pocket region may be phosphorus ions or arsenic ions.
As an example, when the doped ions of the pocket region ion implantation are phosphorus ions, the energy range of the ion implantation is 5keV to 35keV, and the dose of the ion implantation is 1.0 × e13-1.0×e14cm-2The incident direction of the ion implantation is shifted by a certain angle with respect to a direction perpendicular to the semiconductor substrate 100, and the angle ranges from 0 degree to 45 degrees.
By way of example, when the doped ions of the pocket region ion implantation are arsenic ions, the energy range of the ion implantation is 10keV-50keV, and the dose of the ion implantation is 1.0 × e13-1.0×e14cm-2The incident direction of the ion implantation is shifted by a certain angle with respect to a direction perpendicular to the semiconductor substrate 100, and the angle ranges from 0 degree to 45 degrees.
After forming the sidewall structure 111, a source/drain implant region 112 is formed in the semiconductor substrate 100 outside the sidewall structure 111. Then, an annealing process is performed to activate the implanted ions and to eliminate defects generated by the ion implantation.
As the feature size of semiconductor devices is continuously reduced, the length of the channel region defined between the source and drain implant regions 112 is continuously reduced, and when an annealing process is performed to activate the implanted ions, the diffusion effect of the implanted ions causes the generation of a short channel effect, which increases junction leakage and causes the degradation of device performance.
In order to improve the short channel effect of the core device and simultaneously improve the performance of the MOS device, various methods, such as pre-amorphization ion implantation, stress techniques, etc., are adopted in the prior art to improve the short channel effect of the core device and further improve the performance of the MOS device. However, these methods have some disadvantages, such as that the pre-amorphization ion implantation does not well control the doping profile of the source/drain regions of the MOS device, and the stress technique only improves the carrier mobility of the MOS device by providing additional stress to the channel region of the MOS device. The above-described deficiencies further limit the technological advancement space to determine a better balance between suppressing short channel effects and improving the performance of MOS devices.
As shown in fig. 3, the present invention provides a method for manufacturing a semiconductor device, which can obtain a more stress in a channel region while obtaining an LDD implantation region having a shallower depth.
The semiconductor device manufacturing method includes:
in step 301, providing a semiconductor substrate, performing source-drain implantation and annealing, and forming a source-drain implantation region in the semiconductor substrate;
in step 302, a patterned hard mask layer is formed on the source/drain implantation region, and the source/drain implantation region not shielded by the hard mask layer is etched until the semiconductor substrate is exposed;
in step 303, forming a side wall on the side wall of the trench formed by the etching;
in step 304, a gate structure is formed to completely fill the remaining portion of the trench;
in step 305, after removing the spacers and the hard mask layer, performing LDD implantation to form LDD implantation regions in the semiconductor substrate at both sides of the gate structure;
in step 306, a contact hole etch stop layer is formed overlying the gate structure and the semiconductor substrate.
According to the manufacturing method of the semiconductor device, the height of the formed gate structure is larger than the depth of the formed groove, and the LDD injection is carried out to obtain a shallower LDD injection area, so that a shallower injection junction can be obtained compared with the prior art to effectively inhibit the short channel effect; meanwhile, larger stress can be obtained in a channel region, so that the performance of the MOS device is obviously improved.
Next, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to an exemplary embodiment.
[ exemplary embodiment one ]
Referring to fig. 2A-2G, there are shown schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.
First, as shown in fig. 2A, a semiconductor substrate 200 is provided, and as an example, a constituent material of the semiconductor substrate 200 may be undoped single crystal silicon, impurity-doped single crystal silicon, Silicon On Insulator (SOI), or the like. As an example, in the present embodiment, the semiconductor substrate 100 is made of a single crystal silicon material. An isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, is formed in the semiconductor substrate 200, and is not shown in the drawings for simplicity.
Next, well region implantation is performed to form a well region in the semiconductor substrate 200. For NMOS, the doping type of the well region is P type; for PMOS, the doping type of the well region is N type.
Next, source-drain implantation is performed to form a source-drain implantation region 201 in the semiconductor substrate 200. Since a trench needs to be formed in the source/drain implantation region 201 and then a gate structure needs to be formed in the trench, the depth of the source/drain implantation region 201 should be lower than the height of the gate structure to be formed later. Because the gate structure formed later can be a dummy gate structure, and can be removed in the subsequent dummy gate-metal gate process, and further replaced by a metal gate structure with better performance, the depth of the source/drain injection region 201 is set to be lower than the height of the gate structure formed later, so that the surface of the source/drain injection region and the LDD injection region formed later can be protected while the contact hole etching stop layer formed later exposes the top of the gate structure.
After the source-drain implantation is performed, an annealing process is performed to activate the implanted ions and repair defects generated by the implantation, wherein the annealing process can be laser annealing, temperature equalization annealing, peak annealing and the like.
Next, as shown in fig. 2B, a hard mask layer 202 patterned with a trench 203 is formed on the source-drain implantation region 201. By way of example, the hard mask layer 202 is first deposited on the semiconductor substrate 200, preferably by Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), etc.; then, a photoresist layer with a pattern of the groove 203 is formed on the hard mask layer 202 by adopting processes of spin coating, exposure, development and the like; performing dry etching to form a pattern of a trench 203 in the hard mask layer 202 with the photoresist layer as a mask; and removing the photoresist layer through an ashing process.
Next, using the hard mask layer 202 patterned with the trench 203 as a mask, the source/drain implantation region is etched until the semiconductor substrate 200 is exposed. As an example, the etching is plasma dry etching, and the etching gas includes a mixed gas of hydrogen and oxygen, or hexafluorobutadiene, or the like.
Next, as shown in fig. 2C, a sidewall 204 is formed on the sidewall of the trench 203. As an example, the material forming the sidewall 204 is formed by a deposition process, which preferably uses a chemical vapor deposition method, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc., to cover the hard mask layer 202 and the sidewalls and the bottom of the trench 203; then, performing blanket etching (blanket etch) to complete the manufacture of the sidewall 204; finally, wet cleaning is performed to remove etching residues and impurities. The material of the sidewall spacers 204 is preferably the same as the material of the hard mask layer 202, so that they can be removed in the same process in subsequent steps.
Next, as shown in fig. 2D, a gate structure is formed to completely fill the remaining portion of the trench 203.
As an example, the gate structure includes a gate dielectric layer 205 and a gate material layer 206 stacked from bottom to top. The constituent material of the gate dielectric layer 205 includes an oxide such as silicon dioxide (SiO)2) The gate dielectric layer 205 may be formed using a thermal oxidation or chemical oxidation process. The gate material layer 206 is made of one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal may be tungsten (W), nickel (Ni) or titanium (Ti), the conductive metal nitride includes titanium nitride (TiN), and the conductive metal oxide includes iridium oxide (IrO)2) The metal silicide includes titanium silicide (TiSi), and the gate material layer 206 may be formed using a selective epitaxial growth process, which may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
Because the formed gate structure can be a dummy gate structure, the gate structure can be removed in a subsequent dummy gate-metal gate process, and then replaced by a metal gate structure with better performance, so that the formation height of the gate structure is greater than the depth of the trench 203, that is, greater than the depth of the previously formed source and drain injection region 201, so that the surface of the source and drain injection region 201 and the LDD injection region formed later can be protected while the subsequently formed contact hole etching stop layer exposes the top of the gate structure.
Next, as shown in fig. 2E, the spacers 204 and the hard mask layer 202 are removed. As an example, the removing is performed by wet etching, and in order to improve the removing efficiency, the constituent materials of the sidewall 204 and the hard mask layer 202 should be the same, for example, silicon nitride, and when the constituent materials of the sidewall 204 and the hard mask layer 202 are silicon nitride, the etching solution of the wet etching is hot phosphoric acid. For the etching solution of the wet etching, the constituent materials of the sidewall 204 and the hard mask layer 202 should have a higher etching rate than the constituent material of the gate dielectric layer 205, so as to avoid unnecessary erosion to the gate dielectric layer 205 during the process of removing the sidewall 204 and the hard mask layer 202.
Next, as shown in fig. 2F, LDD implantation is performed to form LDD implantation regions 207 in the semiconductor substrate 200 at both sides of the gate structure. During the LDD implantation, the upper portion of the source/drain implantation region 201 is also implanted with dopant ions.
For example, when the dopant ion for LDD implantation is phosphorus ion, the energy range of ion implantation is 1keV-20keV, and the dose of ion implantation is 1.0 × e14-1.0×e15cm-2When the doped ion of the LDD implant is arsenic ion, the energy range of the ion implantation is 2keV-35keV, and the dose of the ion implantation is 1.0 × e14-1.0×e15cm-2。
For example, when the dopant ion for the LDD implant is boron, the energy range of the ion implant is 0.5keV to 10keV, and the dose of the ion implant is 1.0 × e14-1.0×e15cm-2When the doping ions of the LDD implant are indium ions, the energy range of the ion implantation is 10keV-70keV, and the dose of the ion implantation is 1.0 × e14-1.0×e15cm-2。
Then, an annealing process is performed to activate the implanted ions and to eliminate defects generated by the ion implantation.
Because the LDD implantation has a narrower implantation window compared with the prior art, a shallower LDD implantation area can be obtained, and a shallower implantation junction can be obtained compared with the prior art so as to effectively inhibit the short channel effect; meanwhile, larger stress can be obtained in a channel region, so that the performance of the MOS device is obviously improved.
Next, as shown in fig. 2G, a contact hole etch stop layer 208 is formed covering the gate structure and the semiconductor substrate 200. As an example, the contact hole etch stop layer 208 is formed by a deposition process, the deposition is preferably a chemical vapor deposition method, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc., and the material of the contact hole etch stop layer 208 may be SiCN, SiC, SiN, etc. Then, chemical mechanical polishing is carried out until the gate structure is exposed. In subsequent processes, such as a possible gate structure removal process, the contact hole etch stop layer 208 may protect the surface of the source drain implant region 201 and the LDD implant region 207.
To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. According to the invention, a shallower LDD injection region can be obtained, so that a shallower injection junction can be obtained compared with the prior art, and the short channel effect can be effectively inhibited; meanwhile, larger stress can be obtained in a channel region, so that the performance of the MOS device is obviously improved.
[ second exemplary embodiment ]
First, a semiconductor device obtained by the process steps performed by the method according to the first exemplary embodiment of the present invention is provided.
As shown in fig. 2G, includes: the semiconductor substrate 200, the semiconductor substrate 200 may be formed of undoped monocrystalline silicon, impurity-doped monocrystalline silicon, Silicon On Insulator (SOI), or the like, and an isolation structure, which is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, and various well structures are formed in the semiconductor substrate 200.
A gate structure formed on the semiconductor substrate 200, the gate structure including, as an example, a gate dielectric layer 205 and a gate material layer 206 stacked from bottom to top, the gate dielectric layer 205 being composed of an oxide such as silicon dioxide (SiO) as an example2) The gate dielectric layer 205 may be formed by a thermal oxidation or chemical oxidation process, and the gate material layer 206 may be formed of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicideWherein the metal may be tungsten (W), nickel (Ni) or titanium (Ti), the conductive metal nitride comprises titanium nitride (TiN), and the conductive metal oxide comprises iridium oxide (IrO)2) The metal silicide includes titanium silicide (TiSi), and the gate material layer 206 may be formed using a selective epitaxial growth process, which may employ one of low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, ultra high vacuum chemical vapor deposition, rapid thermal chemical vapor deposition, and molecular beam epitaxy.
A source-drain injection region 201 formed in the semiconductor substrate 200, wherein the source-drain injection region 201 and the bottom of the gate structure are located in the same plane; LDD implantation regions 207 formed in the semiconductor substrate 200 on both sides of the gate structure, wherein when the MOS transistor is an NMOS transistor, the LDD implantation doping ions may be phosphorus ions or arsenic ions, and when the MOS transistor is a PMOS transistor, the LDD implantation doping ions may be boron ions or indium ions; and contact hole etching stop layers 208 formed on two sides of the gate structure and covering the LDD injection regions 207 and the source drain injection regions 201, wherein the contact hole etching stop layers 208 can be made of SiCN, SiC, SiN and the like.
The source drain injection region 201 and the bottom of the gate structure are positioned in the same plane, and a shallower LDD injection region can be obtained by implementing LDD injection, so that a shallower injection junction can be obtained compared with the prior art, and the short channel effect can be effectively inhibited; meanwhile, larger stress can be obtained in a channel region, so that the performance of the MOS device is obviously improved.
Then, the fabrication of the whole semiconductor device is completed through the following processes, including: an interlevel dielectric layer is deposited on the semiconductor substrate 200, preferably by a chemical vapor deposition process such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc., and may be selected from a variety of low-k dielectric materials commonly used in the art, including but not limited to, silicate compounds with a k value of 2.5-2.9 (HSQ), Methyl silicate compounds with a k value of 2.2 (MSQ), and k valuesHOSP of 2.8TM(Low dielectric constant material based on a mixture of organic and silicon oxides manufactured by Honeywell Corp.) and SiLK with a k value of 2.65TM(a low dielectric constant material manufactured by Dow Chemical company) and the like, the interlayer dielectric layer is generally formed using an ultra low-k dielectric material, which means a dielectric material having a dielectric constant (k value) of less than 2.
Forming a contact hole in the interlayer dielectric layer to expose the source drain injection region 201 and the top of the gate structure; forming a contact plug in the contact hole by any conventional technique known to those skilled in the art, preferably by chemical vapor deposition, such as low temperature chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, etc.; forming a plurality of interconnection metal layers, which are usually completed by adopting a dual damascene process; and forming a metal bonding pad for wire bonding in the subsequent device packaging process.
[ exemplary embodiment III ]
The present invention also provides an electronic device including the semiconductor device according to the second exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device.
Wherein figure 4 shows an example of a handset. The exterior of the cellular phone 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
The internal element of the electronic device comprises the semiconductor device according to the second exemplary embodiment, which has a shallower LDD implantation region, so that a shallower implantation junction can be obtained relative to the prior art to effectively suppress the short channel effect; meanwhile, larger stress can be obtained in a channel region, so that the performance of the device is obviously improved. The electronic device has better performance due to the use of the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and performing source-drain injection and annealing to form a source-drain injection region in the semiconductor substrate;
forming a patterned hard mask layer on the source-drain injection region, and etching the source-drain injection region which is not shielded by the hard mask layer until the semiconductor substrate is exposed;
forming a side wall on the side wall of the groove formed by etching;
after the side wall is formed, a grid structure is formed to completely fill the rest part of the groove;
after the grid structure is formed, removing the side wall and the hard mask layer;
and after removing the side wall and the hard mask layer, performing LDD injection to form an LDD injection region in the semiconductor substrate at two sides of the gate structure, wherein the LDD injection region extends to the lower part of the source and drain injection region and is adjacent to the source and drain injection region, and the bottom surface of the LDD injection region is lower than that of the source and drain injection region.
2. The method of claim 1, wherein a height of the gate structure is greater than a depth of the trench.
3. The method of claim 2, wherein the gate structure comprises a gate dielectric layer and a gate material layer stacked from bottom to top.
4. The method of claim 1, wherein the sidewall and the hard mask layer are formed of the same material.
5. The method of claim 1, wherein the removing is performed using wet etching.
6. The method of claim 1, wherein after performing the LDD implant, further comprising the step of forming a contact hole etch stop layer, the contact hole etch stop layer covering sidewalls of the gate structure and the semiconductor substrate.
7. The method of claim 1, further comprising the step of performing a well region implant to form a well region in said semiconductor substrate prior to performing said source drain implant.
8. The method of claim 1 wherein for NMOS, the LDD implant dopant ions are either phosphorous or arsenic; for PMOS, the dopant ions for the LDD implant are either boron or indium ions.
9. A semiconductor device manufactured by the method of any one of claims 1 to 8.
10. An electronic device, characterized in that the electronic device comprises the semiconductor device according to claim 9.
CN201610140142.7A 2016-03-11 2016-03-11 Semiconductor device, manufacturing method thereof and electronic device Active CN107180764B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610140142.7A CN107180764B (en) 2016-03-11 2016-03-11 Semiconductor device, manufacturing method thereof and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610140142.7A CN107180764B (en) 2016-03-11 2016-03-11 Semiconductor device, manufacturing method thereof and electronic device

Publications (2)

Publication Number Publication Date
CN107180764A CN107180764A (en) 2017-09-19
CN107180764B true CN107180764B (en) 2020-09-04

Family

ID=59830106

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610140142.7A Active CN107180764B (en) 2016-03-11 2016-03-11 Semiconductor device, manufacturing method thereof and electronic device

Country Status (1)

Country Link
CN (1) CN107180764B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111192849B (en) * 2018-11-14 2022-09-09 长鑫存储技术有限公司 Method for forming semiconductor structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874341A (en) * 1996-10-30 1999-02-23 Advanced Micro Devices, Inc. Method of forming trench transistor with source contact in trench
CN101593775A (en) * 2009-04-22 2009-12-02 上海宏力半导体制造有限公司 Mos field effect transistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5472894A (en) * 1994-08-23 1995-12-05 United Microelectronics Corp. Method of fabricating lightly doped drain transistor device
US5491099A (en) * 1994-08-29 1996-02-13 United Microelectronics Corporation Method of making silicided LDD with recess in semiconductor substrate
CN101661886B (en) * 2008-08-25 2011-06-22 上海华虹Nec电子有限公司 Method for preparing source-drain injection structures in preparation of semiconductors
KR101714003B1 (en) * 2010-03-19 2017-03-09 삼성전자 주식회사 Method of forming semiconductor device having faceted semiconductor pattern and related device
CN102544096B (en) * 2010-12-29 2014-09-03 中芯国际集成电路制造(北京)有限公司 Metal oxide semiconductor device and forming method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5874341A (en) * 1996-10-30 1999-02-23 Advanced Micro Devices, Inc. Method of forming trench transistor with source contact in trench
CN101593775A (en) * 2009-04-22 2009-12-02 上海宏力半导体制造有限公司 Mos field effect transistor

Also Published As

Publication number Publication date
CN107180764A (en) 2017-09-19

Similar Documents

Publication Publication Date Title
US9991123B2 (en) Doped protection layer for contact formation
JP5385926B2 (en) Method for forming a device structure having a self-aligned damaged layer
US9059210B2 (en) Enhanced stress memorization technique for metal gate transistors
CN103378153A (en) Structure and method for finfet integrated with capacitor
CN103137624A (en) High gate density devices and methods
US20170062591A1 (en) Method to enhance 14nm finfet device performance by the sti oxide loss control
CN108231670B (en) Semiconductor element and manufacturing method thereof
US9379104B1 (en) Method to make gate-to-body contact to release plasma induced charging
US9257323B2 (en) Semiconductor device and method for forming the same
US20120205777A1 (en) Semiconductor device and method for fabricating the same
US20200328116A1 (en) Semiconductor device and method for fabricating the same
CN107799470B (en) Semiconductor device, manufacturing method thereof and electronic device
TWI668731B (en) Semiconductor device structures with multiple nitrided layers and methods of forming the same
CN107180764B (en) Semiconductor device, manufacturing method thereof and electronic device
US20070022941A1 (en) Method of forming a layer and method of manufacturing a semiconductor device using the same
US9954067B2 (en) Semiconductor device and manufacturing method thereof
CN108615731B (en) Semiconductor device and manufacturing method thereof
CN105470134A (en) Semiconductor device and manufacturing method thereof and electronic device
US20130049122A1 (en) Semiconductor device and method of manufacturing the same
CN105575900B (en) Semiconductor device, manufacturing method thereof and electronic device
CN107437504B (en) Semiconductor device, manufacturing method thereof and electronic device
US9871035B2 (en) Semiconductor device with metal silicide blocking region and method of manufacturing the same
CN116110956B (en) Memory device and preparation method thereof
CN104952725B (en) A kind of semiconductor devices and its manufacture method
WO2016168994A1 (en) Tunnelling transistor and tunnelling transistor manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant