CN102842614A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102842614A CN102842614A CN2011101652418A CN201110165241A CN102842614A CN 102842614 A CN102842614 A CN 102842614A CN 2011101652418 A CN2011101652418 A CN 2011101652418A CN 201110165241 A CN201110165241 A CN 201110165241A CN 102842614 A CN102842614 A CN 102842614A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000002955 isolation Methods 0.000 claims abstract description 63
- 239000000463 material Substances 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000013459 approach Methods 0.000 claims description 21
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- 239000010703 silicon Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
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- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
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- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 2
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- 229910005883 NiSi Inorganic materials 0.000 description 1
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- 229910052799 carbon Inorganic materials 0.000 description 1
- OEYIOHPDSNJKLS-UHFFFAOYSA-N choline Chemical compound C[N+](C)(C)CCO OEYIOHPDSNJKLS-UHFFFAOYSA-N 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
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- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
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- 238000004528 spin coating Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the steps as follows: forming an insulated isolation layer on a substrate; forming an insulated isolation layer trench in the insulated isolation layer; forming an active region layer in the insulated isolation layer trench; and forming semiconductor device structures in and on the active region layer. The manufacturing method is characterized in that the carrier mobility rate of the active region layer is higher than that of the substrate. According to the semiconductor device and the manufacturing method thereof, an active region different from a substrate material is used, and the carrier mobility rate of a channel region is increased, so that the response speed of the device is greatly increased and the performance of the device is enhanced. In addition, the manufacturing method is different from the conventional STI (Shallow Trench Isolation) manufacturing process, STI is formed at first and then the active region is formed by filling, so that the problem of holes in the STI is avoided and the reliability of the device is improved.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacturing approach thereof, particularly relate to a kind of by the semiconductor device and the manufacturing approach thereof of the Ge film of STI encirclement as raceway groove.
Background technology
Along with dimensions of semiconductor devices continues to dwindle, the mobility that strengthens channel carrier becomes very important technology.The characteristic of material different is different in the design of substrate stressor layers, and for example lattice constant, dielectric constant, energy gap, particularly carrier mobility or the like are as shown in table 1 below.
Table 1
Visible by table 1; In above-mentioned these possible backing materials; Ge has the highest hole mobility and higher electron mobility, uses Ge will strengthen carrier mobility greatly as the substrate of semiconductor device, thereby can make large scale integrated circuit (LSIC) faster.
In addition; Visible by table 1; Ge also has the lattice constant close with the Si material; Therefore Ge can more easily be integrated on the Si substrate commonly used in the semiconductor technology, makes to need not to make the just better semiconductor device of ability manufacturing property of significant improvement for technology, has also reduced cost when having promoted performance.
In semiconductor device and the IC design thereof, isolate, often adopt shallow trench isolation to leave (STI) for the insulation between a plurality of devices that are produced in the substrate.The preparation method of known STI comprises and earlier in substrate, etches groove, adopts method deposition in the groove that forms such as chemical vapor deposition (CVD) for example to be the dielectric film of oxide then.Along with device dimensions shrink; The depth-to-width ratio of corresponding STI is also increasing; The step coverage of oxide insulating film also promptly possibly more early engage and groove below it complete filling not as yet at narrower groove top edge oxide insulating film worse and worse, and this makes and has hole or space among the STI; Make the device isolation performance reduce the reliability variation.
Generally speaking, the low reliability of the performance of semiconductor device of the Si raceway groove that current STI surrounds is relatively poor, needs further to improve the channel region carrier mobility and eliminate the STI hole, to improve semiconductor device electric property and reliability.
Summary of the invention
Therefore, the objective of the invention is to further improve the channel region carrier mobility and eliminate the STI hole, to improve semiconductor device electric property and reliability.
The invention provides a kind of semiconductor device; Comprise: substrate, be formed on dielectric isolation layer on the substrate, be formed on the active region layer in the said dielectric isolation layer; It is characterized in that the carrier mobility of said active region layer is higher than the carrier mobility of said substrate.
Wherein, said substrate is a silicon, and said active region layer is epitaxially grown germanium, and said dielectric isolation layer is a silica.Wherein, be formed with the gate stack that gate insulator and gate material layers constitute on the said active region layer, be formed with source-drain area in the active region layer of said gate stack both sides, form active drain contact on the said source-drain area.Wherein, said gate material layers is polysilicon, metal, metal nitride and combination thereof.Wherein, said gate insulator is high k material, and said gate insulator does not contain the oxide of said substrate and/or said active region layer.Wherein, also has laying between said substrate and the said dielectric isolation layer.Wherein, said substrate layer is silicon nitride or silica.
The present invention also provides a kind of manufacturing approach of semiconductor device, comprising: on substrate, form dielectric isolation layer; In said dielectric isolation layer, form the dielectric isolation layer groove; In said dielectric isolation layer groove, be formed with source region layer; , said active region layer forms semiconductor device structure on neutralizing it; It is characterized in that the carrier mobility of said active region layer is higher than the carrier mobility of said substrate.
Wherein, said substrate is a silicon, and said active region layer is a germanium.Wherein, after forming dielectric isolation layer, also be included in and form laying on the substrate.Wherein, said substrate layer is silicon nitride or silica.Wherein, through HDP, LPCVD or SACVD method on said substrate cvd silicon oxide to form said dielectric isolation layer.Wherein, on said dielectric isolation layer, forming mask graph, is that the said dielectric isolation layer of mask etching is to form said dielectric isolation layer groove, until exposing substrate with this mask graph.Wherein, cross the upper surface of the said dielectric isolation layer of etching until etch substrate.Wherein, said mask graph is made up of photoresist or hard mask layer.Wherein, through RPCVD, UHVCVD or MBE method extension deposit Germanium in said dielectric isolation layer groove.Wherein, the temperature range of said epitaxial deposition is 250 ℃ to 600 ℃.Wherein, Said semiconductor device structure comprises: deposit the gate stack that gate insulator and gate material layers constitute on the said active region layer; Ion injects and is formed with source-drain area in the active region layer of said gate stack both sides, the active drain contact of deposition on the said source-drain area.Wherein, said gate material layers is polysilicon, metal, metal nitride and combination thereof.Wherein, said gate insulator is high k material, and does not contain the oxide of said substrate and/or said active region layer between said gate insulator and the said active region layer.
According to semiconductor device of the present invention and manufacturing approach thereof, used the active area that is different from backing material, improve the channel region carrier mobility, thereby significantly improved the response speed of device, strengthened the performance of device.In addition, be different from existing STI manufacturing process, the present invention forms earlier to fill behind the STI and is formed with the source region, has avoided occurring among the STI problem of hole, has improved the reliability of device.
Purpose according to the invention, and in these other unlisted purposes, in the scope of the application's independent claims, be able to satisfy.Embodiments of the invention are limited in the independent claims, and concrete characteristic is limited in its dependent claims.
Description of drawings
Followingly specify technical scheme of the present invention with reference to accompanying drawing, wherein:
Figure 1A, 2A, 3A, 4A, 5A have shown the generalized section according to each step of manufacturing method of semiconductor device of the present invention respectively; And
Figure 1B, 2B, 3B, 4B, 5B have shown the end face sketch map according to each step of manufacturing method of semiconductor device of the present invention respectively.
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention, semiconductor device and manufacturing approach thereof that STI surrounds the Ge raceway groove are disclosed.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score or the like can be used for modifying various device architectures or processing step.These are modified is not space, order or the hierarchical relationship of hint institute's modification device architecture or processing step unless stated otherwise.
At first, with reference to Figure 1A and Figure 1B, on substrate, form laying and dielectric isolation layer.Substrate 10 can be semiconductor silicon based substrates commonly used such as Si on body Si, the insulating barrier (SOI); Perhaps body Ge, ge-on-insulator (GeOI); Also can be compound semiconductor substrate such as SiGe, GaAs, GaN; Can also be dielectric substrate such as sapphire, SiC, AlN, the selection of substrate need and be set according to the electric property of the concrete semiconductor device that will make on it.In the present invention, the semiconductor device that embodiment lifted for example is field-effect transistor (MOSFET), therefore from considering that with the angle of other process compatibles and cost control preferred body silicon or SOI are as the material of substrate 10.On substrate 10, form laying 20 through common process such as CVD deposition, its material can be oxide, nitride or nitrogen oxide, concrete example such as silicon nitride (Si
3N
4Or SiNx, wherein x is 1～2) or silica (SiO or SiO
2).Laying 20 is used for the layer that stops of etching after a while, and with protection substrate 10, its thickness needs according to etching technics and sets.Deposition forms dielectric isolation layer 30 on laying 20 subsequently; Its material for example is silica, particularly silicon dioxide; Depositional mode can be low-pressure chemical vapor deposition (LPCVD), inferior aumospheric pressure cvd (SACVD), high density plasma chemical vapor deposition (HDP) or the like, selects suitable pressure and temperature with control uniformity, step coverage and deposition velocity.Dielectric isolation layer 30 is isolated as the insulation between a plurality of semiconductor device on the substrate 10, also is the filler of traditional STI, and its thickness need and be set according to insulation isolations.It should be noted that; Though in the top view of the profile of accompanying drawing 1A and accompanying drawing 1B; Substrate 10, laying 20 and dielectric isolation layer 30 areas equate; But also can be in actual the manufacturing and near the above-mentioned foundation structure of formation the center of active area or wafer (wafer) only according to layout design, below each step all similar, repeat no more.
Secondly, with reference to Fig. 2 A and Fig. 2 B, on dielectric isolation layer, form mask graph.On dielectric isolation layer 30, form mask layer and this mask layer of patterning to form mask graph 40.Mask layer can be a photoresist, is applied on the dielectric isolation layer 30 through modes such as for example spin coatings, forms the mask graph 40 of photoresist then through lithography steps such as exposure, developments.Mask layer also can be the hard mask layer of silicon nitride for example, form the soft mask of photoresist above that after etching form hard mask graph 40.Shown in accompanying drawing 2B; Mask graph 40 is complementary with the active area that will form; Also be that mask graph centers on active area and leaves the mask graph opening 41 that exposes dielectric isolation layer 30; The part of the dielectric isolation layer 30 of mask graph 40 belows will be used for forming STI after a while, so the width of mask graph 40 need and be set according to the STI width.
Once more, with reference to accompanying drawing 3A and 3B, be that mask etching forms the dielectric isolation layer groove with the mask graph.Form after mask graph 40 and the mask graph opening 41 thereof, SI semi-insulation separator 30 and the laying 20 that is exposed in the mask graph opening 41 carried out etching, form dielectric isolation layer groove 42.The remainder that dielectric isolation layer stays also promptly is equivalent to the STI of prior art as the insulation isolation structure of device.When dielectric isolation layer 30 is silica, can adopt rare hydrofluoric acid to come wet etching, can adopt also that for example carbon is fluorine-based, SF
6Or NF
3Plasma (also can be mixed with O
2, HBr, Cl
2Deng) dry etching.Etching is till exposing substrate 10.Also can cross etching a little, for example substrate 10 being crossed etch depth is 1～10nm, so that the upper surface of alligatoring substrate 10 helps the formation of Ge film after a while.
Subsequently, with reference to accompanying drawing 4A and 4B, in the dielectric isolation layer groove, be formed with source region layer.Form after the dielectric isolation layer groove 42, remove mask graph 40, and the surface of the substrate 10 that exposes of wet cleaning is to avoid impurity effect epitaxial growth after a while.When mask graph 40 is photoresist, can adopt the inorganic solvent of acetone and aromatic organic solvent or sulfuric acid and hydrogen peroxide solution to remove photoresist mask graph 40, also can adopt the oxygen plasma dry etching to remove.When mask graph 40 is silicon nitride, can adopt hot phosphoric acid to remove.For substrate 10, can adopt wet cleaning, cleaning agent can comprise ammoniacal liquor, hydrogen peroxide solution, deionized water, watery hydrochloric acid, dilute sulfuric acid, diluted hydrofluoric acid, rare nitric acid, choline, Ka Ruosi acid, ozonated water or the like and combination thereof.Subsequently, remove surperficial steam and C impurity through high-temperature baking again after, extension deposits source region layer 50 in dielectric isolation layer groove 42, its material is different from substrate 10, carrier mobility is higher than substrate 10.The material of active region layer 50 is Ge in an embodiment of the present invention, is preferably pure Ge film, can also select GaAs, InAs, InSb and SiGe or the like according to table 1 in addition.Epitaxial deposition can be adopted rpcvd (RPCVD), high vacuum chemical vapour deposition (UHVCVD), molecular beam epitaxy (MBE) or the like.Deposition is preferably low temperature depositing, and temperature range is 250 ℃ to 600 ℃.Can be in unstripped gas gas such as doping HCl to improve the selectivity of extension, also promptly make only deposition and on dielectric isolation layer 30, not depositing in insulation isolated groove 42 of active region layer.Epitaxial deposition is formed with after the source region layer 50, adopts cmp (CMP) and/or wet cleaning to remove the form of unnecessary active region layer material with control active region layer 50, also promptly removes that part that is higher than dielectric isolation layer 30.
At last, with reference to accompanying drawing 5A and 5B, in active area, form device architecture.The embodiment of the invention is example with MOSFET, can be on active region layer 50 earlier successively deposition form gate insulator 61, gate material layers 62, for example be the cap rock (not shown) of silicon nitride; Photoetching then/etching forms gate stack structure, is that mask carries out first time ion and injects with the cap rock on gate stack structure top, the low-doped source-drain area of formation in active area 50, and doping type is looked the PMOS/NMOS type and difference; Then deposition, etching form gate isolation side wall 63 in the grid both sides; With gate isolation side wall 63 is that mask carries out the ion injection second time, in active area 50, forms heavily doped source-drain area, finally forms source-drain area 64 for having the heavily doped region of lightly-doped source drain structure (LDD), is the channel region of device between the source-drain area 64; On source-drain area 64, form source drain contact 65.
The final device architecture that forms is shown in Fig. 5 A; On substrate 10, has dielectric isolation layer 30; Has active region layer 50 in the dielectric isolation layer 30; Wherein the carrier mobility of active region layer 50 is higher than the carrier mobility of substrate 10, in active region layer 50 and be formed with semiconductor device structure above that, comprising: the source-drain area 64 that has device in the active region layer 50; Have gate insulator 61, gate material layers 62, gate isolation side wall 63 on the active region layer 50, have source drain contact 65 on the source-drain area 64.Wherein, gate insulator 61 materials are preferably high dielectric constant material (hafnium, for example dielectric constant k is greater than 3.9), for example nitride such as SiN, AlN, AlHfN, for example Al
2O
3, Ta
2O
5, TiO
2, ZnO, ZrO
2, HfO
2, CeO
2, Y
2O
3Deng metal oxide, PZT (PbZr for example again
xTi
1-xO
3), BST (Ba
xSr
1-xTiO
3) wait the perovskite phase oxide, combination that also can above all these materials, for example range upon range of or mix.It should be noted that the oxide that does not contain substrate 10 and/or active region layer 50 between the Ge of gate insulator 61 and active area, also is oxygen-free silicon and/or germanium oxide, and promptly zero boundary layer (Zero Interface) is used for promoting the performance of high k material.The material of gate material layers 62 for example is a polysilicon, also can be the nitride of metal such as Al, Au, W, Ta, Ti and/or these metals, can also polysilicon, the combination of metal, metal nitride, and for example range upon range of or mix.Wherein can perhaps select the metal material of appropriate work function number to polysilicon doping, with the threshold voltage of control device.The material of source drain contact 65 can be metal and/or metal nitrides such as Al, Au, W, Ta, Ti, can also be that metal silicides such as NiSi, WSi are with further reduction contact resistance, source-drain series resistance.
Though the semiconductor device structure of being lifted in the embodiment of the invention is with the MOSFET of germanium film as active area, channel region on the silicon substrate; It is other semiconductor device of bipolar transistor, MESFET, HEMT, diode or the like of active area or substrate that but the present invention also goes for the other materials, as long as comprise the dielectric isolation layer that carrier mobility of the present invention is higher than the active area of substrate and is surrounded with the source region in its device architecture and the manufacturing approach.In addition, use the Ge material,, also can take the III-V compounds of group as active area, for example GaAs, GaN or the like for other devices such as for example NMOS though the embodiment of the invention has only been enumerated the PMOS active area.
According to semiconductor device of the present invention and manufacturing approach thereof, used the active area that is different from backing material, improve the channel region carrier mobility, thereby significantly improved the response speed of device, strengthened the performance of device.In addition, be different from existing STI manufacturing process, the present invention forms earlier to fill behind the STI and is formed with the source region, has avoided occurring among the STI problem of hole, has improved the reliability of device.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and various suitable changes and equivalents are made in technological process.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (20)
1. semiconductor device comprises: substrate, be formed on dielectric isolation layer on the substrate, be formed on the active region layer in the said dielectric isolation layer, it is characterized in that the carrier mobility of said active region layer is higher than the carrier mobility of said substrate.
2. semiconductor device as claimed in claim 1, wherein, said substrate is a silicon, and said active region layer is epitaxially grown germanium, GaAs, InAs, InSb or SiGe, and said dielectric isolation layer is a silica.
3. semiconductor device as claimed in claim 1; Wherein, Be formed with the gate stack that gate insulator and gate material layers constitute on the said active region layer, be formed with source-drain area in the active region layer of said gate stack both sides, form active drain contact on the said source-drain area.
4. semiconductor device as claimed in claim 3, wherein, said gate material layers is polysilicon, metal, metal nitride and combination thereof.
5. semiconductor device as claimed in claim 3, wherein, said gate insulator is high k material, and said gate insulator does not contain the oxide of said substrate and/or said active region layer.
6. semiconductor device as claimed in claim 1 wherein, also has laying between said substrate and the said dielectric isolation layer.
7. semiconductor device as claimed in claim 6, wherein, said substrate layer is silicon nitride or silica.
8. the manufacturing approach of a semiconductor device comprises:
On substrate, form dielectric isolation layer;
In said dielectric isolation layer, form the dielectric isolation layer groove;
In said dielectric isolation layer groove, be formed with source region layer;
, said active region layer forms semiconductor device structure on neutralizing it;
It is characterized in that the carrier mobility of said active region layer is higher than the carrier mobility of said substrate.
9. semiconductor device as claimed in claim 8, wherein, said substrate is a silicon, said active region layer is a germanium.
10. the manufacturing approach of semiconductor device as claimed in claim 8 wherein, also is included in after forming dielectric isolation layer and forms laying on the substrate.
11. the manufacturing approach of semiconductor device as claimed in claim 9, wherein, said substrate layer is silicon nitride or silica.
12. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, through HDP, LPCVD or SACVD method on said substrate cvd silicon oxide to form said dielectric isolation layer.
13. the manufacturing approach of semiconductor device as claimed in claim 8 wherein, forms mask graph on said dielectric isolation layer, be that the said dielectric isolation layer of mask etching is to form said dielectric isolation layer groove, until exposing substrate with this mask graph.
14. the manufacturing approach of semiconductor device as claimed in claim 13 wherein, is crossed the upper surface of the said dielectric isolation layer of etching until etch substrate.
15. the manufacturing approach of semiconductor device as claimed in claim 13, wherein, said mask graph is made up of photoresist or hard mask layer.
16. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, through RPCVD, UHVCVD or MBE method extension deposit Germanium in said dielectric isolation layer groove.
17. the manufacturing approach of semiconductor device as claimed in claim 16, wherein, the temperature range of said epitaxial deposition is 250 ℃ to 600 ℃.
18. the manufacturing approach of semiconductor device as claimed in claim 8; Wherein, Said semiconductor device structure comprises: deposit the gate stack that gate insulator and gate material layers constitute on the said active region layer; Ion injects and is formed with source-drain area in the active region layer of said gate stack both sides, the active drain contact of deposition on the said source-drain area.
19. the manufacturing approach of semiconductor device as claimed in claim 18, wherein, said gate material layers is polysilicon, metal, metal nitride and combination thereof.
20. the manufacturing approach of semiconductor device as claimed in claim 18, wherein, said gate insulator is high k material, and does not contain the oxide of said substrate and/or said active region layer between said gate insulator and the said active region layer.
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| PCT/CN2011/001994 WO2012174696A1 (en) | 2011-06-20 | 2011-11-29 | Semiconductor device and the manufacturing method thereof |
| US13/497,744 US8703567B2 (en) | 2011-06-20 | 2011-11-29 | Method for manufacturing a semiconductor device |
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| CN105590842A (en) * | 2014-11-17 | 2016-05-18 | 上海华力微电子有限公司 | Structure and method for reducing source-drain resistance |
| CN107464741A (en) * | 2016-06-03 | 2017-12-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN113690187A (en) * | 2021-08-17 | 2021-11-23 | 福建省晋华集成电路有限公司 | Semiconductor structure and forming method thereof |
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| US20050073028A1 (en) * | 2003-10-02 | 2005-04-07 | Grant John M. | Semiconductor device incorporating a defect controlled strained channel structure and method of making the same |
| CN1985358A (en) * | 2004-07-15 | 2007-06-20 | 英飞凌科技股份公司 | Formation of active area using semiconductor growth process without STI integration |
| US20070181977A1 (en) * | 2005-07-26 | 2007-08-09 | Amberwave Systems Corporation | Solutions for integrated circuit integration of alternative active area materials |
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| US20050104156A1 (en) * | 2003-11-13 | 2005-05-19 | Texas Instruments Incorporated | Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes |
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| US20050073028A1 (en) * | 2003-10-02 | 2005-04-07 | Grant John M. | Semiconductor device incorporating a defect controlled strained channel structure and method of making the same |
| CN1985358A (en) * | 2004-07-15 | 2007-06-20 | 英飞凌科技股份公司 | Formation of active area using semiconductor growth process without STI integration |
| US20070181977A1 (en) * | 2005-07-26 | 2007-08-09 | Amberwave Systems Corporation | Solutions for integrated circuit integration of alternative active area materials |
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| CN105590842A (en) * | 2014-11-17 | 2016-05-18 | 上海华力微电子有限公司 | Structure and method for reducing source-drain resistance |
| CN105590842B (en) * | 2014-11-17 | 2019-11-01 | 上海华力微电子有限公司 | Reduce the structures and methods of source electrode and drain electrode resistance |
| CN107464741A (en) * | 2016-06-03 | 2017-12-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN113690187A (en) * | 2021-08-17 | 2021-11-23 | 福建省晋华集成电路有限公司 | Semiconductor structure and forming method thereof |
| CN113690187B (en) * | 2021-08-17 | 2023-10-20 | 福建省晋华集成电路有限公司 | Semiconductor structure and forming method thereof |
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| WO2012174696A1 (en) | 2012-12-27 |
| CN102842614B (en) | 2015-11-25 |
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