CN105590842A - Structure and method for reducing source-drain resistance - Google Patents
Structure and method for reducing source-drain resistance Download PDFInfo
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- CN105590842A CN105590842A CN201410654361.8A CN201410654361A CN105590842A CN 105590842 A CN105590842 A CN 105590842A CN 201410654361 A CN201410654361 A CN 201410654361A CN 105590842 A CN105590842 A CN 105590842A
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Abstract
The present invention discloses a method for reducing a source-drain resistance. Through the method, the resistance of a source-drain region can be effectively reduced. The method comprises the steps of: forming a grid, a source-drain region, and a side wall on a substrate; forming a first side wall hard mask at the outer side of the side wall; forming a semiconductor layer on the source-drain region; forming a second side wall hard mask at the outer side of the first side wall hard mask; etching the semiconductor layer by using the second side wall hard mask as a mask layer; and removing the first side wall hard mask and the second side wall hard mask, so as to form a projection structure separated from the grid on the source-drain region.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to the structure and the method that reduce source-drain electrode resistance.
Background technology
Along with developing rapidly of nanofabrication technique, transistorized characteristic size has entered nanoscale. Pass through etc.The performance that the method that ratio is dwindled improves current main-stream silicon CMOS device is subject to more and more physics, techniqueRestriction. In order to make integrated circuit technique can continue the development speed that Moore's Law discloses, must exploitation withNew material, new construction and the new property of silicon technology compatibility.
Fig. 1 illustrates the cross-sectional view of the metal silicide forming on device in prior art. As shown in Figure 1,On grid 106 and source electrode and drain region 110, be coated with metal silicide film 112. These metal silicide films110 utilize self-registered technology to form. First, in wafer surface, conformal deposited layer of metal, passes through low temperatureThis metal of rta technique can with polysilicon or silicon substrate in the silicon formation metal silicide that reacts, andCan not react with silicon nitride or silica, next make contact resistance by high resistant by high temperature rapid thermal annealing techniqueChange mutually low-resistance phase into and then reduce contact resistance, then removing this metal by selective etch, due at gridWith in part outside source electrode and drain contact region, there is the barrier layer such as silica or silicon nitride, therefore metal is notCan react with polysilicon or silicon substrate and generate metal silicide, the therefore quilt in this step of the metal outside contact zoneRemove, and the metal silicide forming on grid and source electrode and drain contact region is retained formation metal silicationThing layer 112.
In CMOS technique, this self-registered technology can reduce source electrode and drain electrode contact resistance. But,Along with reducing of transistorized characteristic size, the contact area of source electrode and drain electrode constantly reduces, cause source electrode andDrain electrode contact resistance increases.
Therefore, need a kind of new construction, new technology, increase source electrode and drain area, thereby reduce source electrodeAnd drain resistance.
Summary of the invention
The object of this invention is to provide a kind of manufacture method and structure of semiconductor devices, by the method and knotStructure can reduce source electrode and drain resistance.
According to an aspect of the present invention, provide a kind of manufacture method of semiconductor devices, comprising: at substrateGrid, source electrode and drain region and the side wall of upper formation; Form the hard mask of the first side wall in described side wall outside;On described source electrode and drain region, form semiconductor layer; Form second in the hard mask of described the first side wall outsideThe hard mask of side wall; Using the hard mask of described the second side wall as semiconductor layer described in mask layer etching; RemoveThe hard mask of described the first side wall and the hard mask of the second side wall, thus on described source electrode and drain region, formThe bulge-structure separating with described grid.
According to an aspect of the present invention, in preceding method, semiconductor layer is silicon layer.
According to an aspect of the present invention, in preceding method, semiconductor layer comprises and described source electrode and drain regionThe directly SiGe layer of contact, the silicon layer on described SiGe layer.
According to an aspect of the present invention, in preceding method, semiconductor layer comprises and described source electrode and drain regionDirectly the first silicon layer of contact, SiGe layer on described the first silicon layer, on described SiGe layer secondSilicon layer.
According to an aspect of the present invention, in preceding method, semiconductor layer comprises with described described in etchingSiGe layer is as etching stop layer, the silicon layer described in etching on SiGe layer.
According to an aspect of the present invention, in preceding method, the thickness of SiGe layer is greater than 10 dusts.
According to an aspect of the present invention, preceding method is also included in described in etching after semiconductor layer, removesDescribed SiGe layer.
According to an aspect of the present invention, in preceding method, form the hard mask of the first side wall and comprise the following stepsIn at least one step: conformal deposited the first side wall hard mask material layer on described substrate; Pass through anisotropyEtching technics etching the first side wall hard mask material layer, due on described grid, source electrode and drain regionOne side wall hard mask material layer thickness is less than the thickness of mask layer on described side wall both sides, therefore etching awayState after the first side wall hard mask material layer on grid, source electrode and drain region, on described side wall both sides, formThe hard mask of the first side wall.
According to an aspect of the present invention, in preceding method, form the hard mask of the second side wall and comprise the following stepsIn at least one step: conformal deposited the second side wall hard mask material layer on described substrate; Pass through anisotropyEtching technics etching the second side wall hard mask material layer, due on described grid, source electrode and drain regionTwo side wall hard mask material layer thicknesses are less than the thickness of mask layer on the hard mask of described the first side wall both sides, thereforeAfter the second side wall hard mask material layer etching away on described grid, source electrode and drain region, described firstOn the hard mask of side wall both sides, form the hard mask of the second side wall.
According to an aspect of the present invention, in preceding method, the hard mask of the first side wall and described the second side wall are hardThe width of mask is greater than 30 dusts.
According to an aspect of the present invention, in preceding method, repeatedly repeat described the second side wall of described formation and coverThe step of rete and etching semiconductor layer, to form multistage scalariform source electrode and leakage on described source electrode and drain regionElectrode structure.
According to an aspect of the present invention, in preceding method, the hard mask of the first side wall and described the second side wall are hardMask is formed by any in following material: silica, silicon nitride, SiON, amorphous carbon or theyAny combination.
According to an aspect of the present invention, in preceding method, form described semiconductor layer by epitaxial growth method.
According to another aspect of the present invention, provide a kind of semiconductor devices, comprising: grid, source electrode and leakagePolar region and side wall, wherein said source electrode with on drain region, there is the bulge-structure separating with described grid.
Compared with prior art, contacting according to the source electrode of of the present invention formed semiconductor devices and drain electrodeArea significantly increases, and source electrode and drain electrode contact resistance significantly reduce.
Brief description of the drawings
In order further to illustrate above and other advantage and the feature of various embodiments of the present invention, with reference to accompanying drawingPresent the description more specifically of various embodiments of the present invention. Be appreciated that these accompanying drawings only describe the present inventionExemplary embodiments, therefore will not be considered to restriction on its scope. In the accompanying drawings, for cheer and bright,Amplify the thickness in layer and region. Identical or corresponding parts will represent with same or similar mark.
Fig. 1 illustrates the cross-sectional view of the metal silicide forming on device in prior art.
Fig. 2 A to Fig. 2 F illustrates according to the first embodiment of the present invention and forms projection at source electrode and drain regionThe generalized section of the process of structure.
Fig. 3 A to Fig. 3 F illustrates according to a second embodiment of the present invention and forms projection at source electrode and drain regionThe generalized section of the process of structure.
Fig. 4 A to Fig. 4 F illustrates that a third embodiment in accordance with the invention is by controlling etching silicon epitaxial layersThickness forms the generalized section of the process of bulge-structure in source electrode and drain region.
Fig. 5 illustrates and according to an embodiment of the inventionly in source electrode and drain region, forms bulge-structureFlow chart.
Detailed description of the invention
In the following description, with reference to each embodiment, present invention is described. But, the technology of this areaPersonnel by recognize can be neither one or the multiple specific detail in the situation that or with other replacement and/or attachedAdding method, material or assembly are implemented each embodiment together. In other situation, not shown or do not describe in detailKnown structure, material or operation are in order to avoid make the aspects of various embodiments of the present invention obscure. Similarly, forThe object of explaining, set forth specific quantity, material and configuration, to provide embodiments of the inventionComplete understanding. But the present invention can implement in the situation that there is no specific detail. In addition, should understand accompanying drawingShown in each embodiment be illustrative expression and not necessarily in proportion draw.
In order to increase source electrode and drain region contact area to reduce source electrode and drain electrode contact resistance, inventor's structureFind out one by form bulge-structure in source electrode and drain region, thereby increase source electrode and drain region contact-making surfaceLong-pending method.
Fig. 2 A to Fig. 2 F illustrates according to the first embodiment of the present invention and forms projection at source electrode and drain regionThe generalized section of the process of structure.
As shown in Figure 2 A, device 200 is included in the grid 202, source electrode and the drain electrode that on substrate 201, formDistrict 203 and side wall 204. Device 200 can form by multiple steps, for example comprises, shallow-trench isolation step,Polysilicon deposition step, gate pattern step, implantation step, annealing steps etc. Carry out shallow slot everyWith after forming multiple active areas, on substrate, form gate dielectric 205 deposit spathic silicon layer from step,Then carry out patterning to form grid 202. After forming side wall 204, carry out Implantation, with shapeBecome source electrode and drain region. For outstanding emphasis of the present invention, the forming process of device 200 is not carried out in detailDescribe.
Next, as shown in Figure 2 B, form the hard mask 206 of the first side wall in side wall 204 outsides. ?In an embodiment, the material that can be used for forming the hard mask 206 of the first side wall comprises silica, nitrogenizeSilicon, SiON, amorphous carbon or their any combination. In one embodiment, the hard mask of the first side wall206 width is greater than 30 dusts. Can utilize the technique similar to forming side wall 204 to form the first side wall hardMask 206. In one embodiment, first on wafer, conformal deposited one deck is used to form the first side wallThe material of hard mask 206, then by this material layer of anisotropic etch process etching. Due to levelOn face, the thickness of the first hard mask layer 206 is less than the thickness of hard mask layer 206 on side wall 204 both sides,Therefore after the hard mask layer 206 of removing on horizontal plane, the first side wall that leaves side wall 204 both sides is hardMask 206. In other embodiments, the hard mask 206 of the first side wall also can be by other material or otherTechnique forms.
Next, as shown in Figure 2 C, on source electrode and drain region 203, form certain thickness SiGe layer 207,And on SiGe layer 207, form Si layer 208. In one embodiment, the thickness of SiGe layer 207Be greater than 10 dusts. In one embodiment, can be by growth technology grow SiGe layer 207 and SiLayer 208. In one embodiment, the thickness of Si layer 208 can be between 30 to 100 dusts.
For example, the process gas that is used to form epitaxial growth SiGe layer 207 can comprise SiH4；GeH4；HCl；BH6; And H2, wherein H2Gas flow rate can be 0.1slm to 50slm, other gasThe flow velocity of body can be 1sccm to 1000sccm, and reaction temperature is at 500-800 DEG C, and pressure is at 5-50Holder, but the invention is not restricted to listed these process gas and technological parameter. Can change these worksSkill parameter, adjusts the Ge content in SiGe alloy.
Next, as shown in Figure 2 D, form the second side wall in the hard mask of the first side wall 206 outsides and firmly coverFilm 209. In one embodiment, the material that can be used for forming the hard mask 209 of the second side wall can be oxygenSiClx, silicon nitride, SiON, amorphous carbon or their any combination. The hard mask 209 of the second side wallThe forming process of forming process and the hard mask 206 of the first side wall is detailed, therefore, and no longer further in detailDescribe.
Next, utilize the hard mask 209 of the second side wall as mask layer, and SiGe layer 207 is doneFor etching stop layer, etching Si layer 208, thereby make not covered by the hard mask 209 of the second side wallSi layer 208 is removed, and forms structure as shown in Figure 2 E.
Finally remove the hard mask 206,209 of the first and second side walls, shape in the middle of source electrode and drain region 203Become bulge-structure, as shown in Figure 2 F, thereby increased the effective area of source electrode and drain region 203. Can lead toCross various dry method or wet etching method and remove the hard mask 206,209 of the first and second side walls. For example,In one embodiment of the invention, side wall 204 is the double-deck stepped construction of silica and silicon nitride,The material of the hard mask 206,209 of the first and second side walls is identical with side wall 204, can pass through four step wet methodsEtching technics is removed the hard mask 206,209 of the first and second side walls: the first hard mask 209 of etching the second side wallSilicon nitride layer and taking silicon oxide layer as etching stop layer, the then oxygen of the hard mask 209 of etching the second side wallSiClx layer taking the silicon nitride layer of the hard mask 206 of the first side wall as etching stop layer, then etching the first side wallThe silicon nitride layer of hard mask 206 taking the silicon oxide layer of the hard mask 206 of the first side wall as etching stop layer,Then the silicon oxide layer of the hard mask 206 of etching the first side wall taking the silicon nitride layer of side wall 204 as etch-stopOnly layer, thus remove the hard mask 206,209 of the first and second side walls completely. But, removal of the present inventionThe method of the hard mask 206,209 of the first and second side walls is not limited to this.
Owing to having SiGe layer 207 as etching stop layer, whole flow process does not touch substrate Si, soPerformance impact to device is less. In the present invention, SiGe layer 207 is as etching stop layer, thereby, canAfter having the source electrode of bulge-structure and drain region 203, formation removes the SiGe layer 207 exposing, but alsoCan retain the SiGe layer 207 of exposure.
Fig. 3 A to Fig. 3 F illustrates according to a second embodiment of the present invention and forms projection at source electrode and drain regionThe generalized section of the process of structure.
With the similar process shown in Fig. 2 A to Fig. 2 F, device 300 is included in the grid that form on substrate 301The utmost point 302, source electrode and drain region 303 and side wall 304. Difference is, as shown in Figure 3 C, and at source electrodeComprise with the semiconductor multilayer forming on drain region 303: with directly contact with drain region 303 at source electrodeThe first silicon layer 311, the SiGe layer 312 directly contacting with the first silicon layer 311 and with SiGe layer 312Directly the second silicon layer 313 of contact.
Because the lattice paprmeter of SiGe alloy is different from the lattice paprmeter of Si crystal, therefore SiGe alloy is logicalOften can make to produce stress in its silicon crystal around. Therefore, in SiGe layer 312 and source electrode and drain region 303Between form a Si layer 311 and can make SiGe layer 312 away from source electrode and drain region, reduce SiGe layer 312The effect of stress that device is produced. SiGe layer 312 is as the etching stop layer of etching the 2nd Si layer 313,Its thickness is greater than 10 dusts. In one embodiment, can be by the growth technology Si layer of growing311, SiGe layer 312 and the 2nd Si layer 313. In one embodiment, a Si layer 311 andThe thickness of two Si layers 313 can be between 30 to 100 dusts.
Similar process shown in the process of Fig. 3 D to 3F and Fig. 2 D to 2F, in order to simplify of the present invention retouchingState, and no longer describe in further detail.
Fig. 4 A to Fig. 4 E illustrates that a third embodiment in accordance with the invention is by controlling etching silicon epitaxial layersThickness forms the generalized section of the process of bulge-structure in source electrode and drain region.
Similar to Fig. 2 A to 2B, device 400 is included in the grid 402, the source electrode that on substrate 401, formWith drain region 403 and side wall 404, form the hard mask 406 of the first side wall in side wall 404 outsides.
Next, as shown in Figure 4 C, on source electrode and drain region 403, form certain thickness Si layer 411,In one embodiment, can be by the growth technology Si layer 411 of growing. In one embodiment,The thickness of Si layer 411 is between 30 dust to 100 dusts.
Next, as shown in Figure 4 D, form the second side wall in the hard mask of the first side wall 406 outsides and firmly coverFilm 409.
Next, utilize the hard mask 409 of the second side wall as mask layer, etching Si layer 411. SpyDetermine under process conditions, be constant to the etch rate of Si, therefore, do not forming etching stop layerIn situation, the degree of depth that can control etching by control etch period is to avoid transition etching or etching notFoot. Thereby the Si layer 411 not covered by the hard mask 409 of the second side wall is removed, forms as figureStructure shown in 4E.
Finally remove the hard mask 406,409 of the first and second side walls, form have bulge-structure source electrode andDrain region 403, as shown in Fig. 4 F, thereby has increased the effective area of source electrode and drain region 403. FirstDetailed with the method shown in removal method and Fig. 2 F of the hard mask 406,409 of the second side wall, therefore no longer enterOne step is described in detail.
In other embodiments of the invention, can form the hard mask structure of multiple the second side wall, and for oftenThe hard mask structure of individual the second side wall, carries out etching one time, thereby forms the source with multistage scalariform bulge-structureDistrict/drain structure.
Fig. 5 illustrates and according to an embodiment of the inventionly in source electrode and drain region, forms bulge-structureFlow chart.
First, in step 501, grid, source electrode and the drain region and the side wall that on substrate, form. In step502, form the hard mask of the first side wall in side wall outside. The first side wall mask layer utilizes its autoregistration characteristicForm. In step 503, on source electrode and drain region, form semiconductor layer. According to of the present invention first toThe 3rd embodiment, this semiconductor layer can be single layer structure or multilayer laminated structure. For example, can pass throughEpitaxial growth semiconductor layer, this semiconductor layer can be 1) monolayer silicon; 2) direct with source electrode and drain regionThe SiGe of contact and the silicon layer forming on it; The first silicon layer of 3) directly contacting with drain region with source electrode,The SiGe layer forming on the first silicon layer, the second silicon layer forming on SiGe layer. SiGe is as quarterLose stop-layer and away from raceway groove, reduce the effect of stress that SiGe layer produces raceway groove, form the source raisingThe utmost point and drain region (raisedsource/drain, RSD).
In step 504, form the hard mask of the second side wall in the hard mask of the first side wall outside.
In step 505, utilize the hard mask of the second side wall as mask layer etching semiconductor layer. In step506, remove the first and second side wall hard mask layers.
In the situation that semiconductor layer is monolayer silicon, can control by controlling etch period the degree of depth of etchingTo avoid transition etching or etching deficiency. It is the situation of the sandwich construction that comprises SiGe layer at semiconductor layerUnder, using SiGe layer as etching stop layer etching silicon layer. Complete after etching, optionally removing sudden and violentThe SiGe layer revealing. Thus, on source electrode and drain region, form bulge-structure, this bulge-structure and gridDistinguish from, the semiconductor multilayer and the raceway groove that form by epitaxial growth are separated.
Can many sides repeating step 504 and 505, form the hard mask structure of multiple the second side wall, and for oftenThe hard mask structure of individual the second side wall, carries out etching one time, thereby forms the source with multistage scalariform bulge-structureDistrict/drain structure.
Finally, on source electrode and drain region and gate regions, form metal silicide. Due in source electrode and drain electrodeIn district, there is bulge-structure, therefore increased the real area of source electrode and drain region, thus reduced source electrode andThe contact resistance of drain region.
Provide for the purpose of illustration and description the foregoing description of embodiments of the invention. Do not intend poorLift or limit the invention to disclosed precise forms. This description and claims comprise such as left,The right side, top, the end ... on ... under, top, bottom, first, second etc. term, thisOnly should not be construed as a bit restriction for the object of describing. For example, indicate the term of relative upright position to refer toBe that the device-side (or active surface) of substrate or integrated circuit is the situation of " top " face of this substrate; SubstrateCan be in fact in any direction, make " top " side of substrate in the referential of standard land can be lower than " end " sideAnd still drop in the implication on term " top ". As used in this term " ... on " (be included in rightIn requirement) do not indicate the ground floor on the second layer directly on the second layer and with the second layer, directly to contact,Like this unless expressly stated; Between the second layer on ground floor and ground floor, can there be the 3rd layer or other knotStructure. Can in multiple positions and direction, manufacture, use or transport the embodiment of device as herein described or goods.Those skilled in the relevant art can understand a lot of amendments and distortion is possible according to above teaching. AbilityThe technical staff in territory will recognize various equivalent combinations and the replacement of the each assembly shown in accompanying drawing. Therefore thisBright scope is not to be limited by this detail specifications but be defined by the following claims.
Some embodiment of the present invention have more than been described. But the present invention can be embodied as other concrete formAnd do not deviate from its spirit or substantive characteristics. It is only explanation that described embodiment should be considered in all respectsProperty and nonrestrictive. Therefore, scope of the present invention by appended claims but not aforementioned description limit.Fall into change in implication and the scope of equivalents of claims by the scope of claimsInstitute is contained.
Claims (15)
1. a manufacture method for semiconductor devices, comprising:
Grid, source electrode and the drain region and the side wall that on substrate, form;
Form the hard mask of the first side wall in described side wall outside;
On described source electrode and drain region, form semiconductor layer;
Form the hard mask of the second side wall in the hard mask of described the first side wall outside;
Using the hard mask of described the second side wall as semiconductor layer described in mask layer etching;
Remove the hard mask of described the first side wall and the hard mask of the second side wall, thereby in described source electrode and drain electrodeIn district, form the bulge-structure separating with described grid.
2. the method for claim 1, is characterized in that, described semiconductor layer is silicon layer.
3. the method for claim 1, is characterized in that, described semiconductor layer comprises and described sourceThe SiGe layer that the utmost point directly contacts with drain region, the silicon layer on described SiGe layer.
4. the method for claim 1, is characterized in that, described semiconductor layer comprises and described sourceThe first silicon layer that the utmost point directly contacts with drain region, SiGe layer on described the first silicon layer, at described SiGeThe second silicon layer on layer.
5. the method as described in claim 3 or 4, is characterized in that, semiconductor layer comprises described in etchingUsing described SiGe layer as etching stop layer, the silicon layer described in etching on SiGe layer.
6. the method as described in claim 3 or 4, is characterized in that, the thickness of described SiGe layer is greater than10 dusts.
7. the method as described in claim 3 or 4, is characterized in that, is also included in described in etching and partly leadsAfter body layer, remove described SiGe layer.
8. the method for claim 1, is characterized in that, form the first side wall hard mask comprise withAt least one step in lower step:
Conformal deposited the first side wall hard mask material layer on described substrate;
By anisotropic etch process etching the first side wall hard mask material layer, due to described grid, sourceThe first side wall hard mask material layer thickness on the utmost point and drain region is less than the thick of mask layer on described side wall both sidesDegree, therefore after the first side wall hard mask material layer etching away on described grid, source electrode and drain region,On described side wall both sides, form the hard mask of the first side wall.
9. the method for claim 1, is characterized in that, form the second side wall hard mask comprise withAt least one step in lower step:
Conformal deposited the second side wall hard mask material layer on described substrate;
By anisotropic etch process etching the second side wall hard mask material layer, due to described grid, sourceThe second side wall hard mask material layer thickness on the utmost point and drain region is less than on the hard mask of described the first side wall both sidesThe thickness of mask layer, therefore at the hard mask material of the second side wall etching away on described grid, source electrode and drain regionAfter the bed of material, on the hard mask of described the first side wall both sides, form the hard mask of the second side wall.
10. the method for claim 1, is characterized in that, the hard mask of described the first side wall and described inThe width of the hard mask of the second side wall is greater than 30 dusts.
11. methods as claimed in claim 8, is characterized in that, repeatedly repeat described formation described secondThe step of side wall mask layer and etching semiconductor layer, to form multistage scalariform source on described source electrode and drain regionThe utmost point and drain electrode structure.
12. the method for claim 1, is characterized in that, the hard mask of described the first side wall and described inThe hard mask of the second side wall is formed by any in following material: silica, silicon nitride, SiON, amorphousCarbon or their any combination.
13. the method for claim 1, is characterized in that, form described half by epitaxial growth methodConductor layer.
14. 1 kinds of semiconductor devices, comprise by the method described in any one in claim 1 to 13The structure of manufacturing.
15. 1 kinds of semiconductor devices, comprising:
Grid, source electrode and drain region and side wall,
Wherein said source electrode with on drain region, there is the bulge-structure separating with described grid.
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