CN109427559A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109427559A CN109427559A CN201710790571.3A CN201710790571A CN109427559A CN 109427559 A CN109427559 A CN 109427559A CN 201710790571 A CN201710790571 A CN 201710790571A CN 109427559 A CN109427559 A CN 109427559A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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Abstract
A kind of semiconductor devices and forming method thereof, method includes: that discrete top mask structure is formed in the firstth area of bottom mask layer, and top mask structure includes top mask layer, and top mask structure also extends to the part of the surface of marginal zone；To push up mask structure as exposure mask, marginal zone and third area to bottom mask layer are modified processing, form modified layer in the marginal zone and third area of bottom mask layer；Modified layer is removed, forms groove in the marginal zone of bottom mask layer and in third area, and the firstth area of bottom mask layer and middle area is made to form the bottom mask layer between adjacent grooves.The method simplifies patterned technical process.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
In the technique of semiconductor devices manufacture, patterning process is a kind of important processing step.
Patterning process generally includes: providing material layer to be etched；Mask layer is formed in material layer to be etched；With described
Mask layer is mask etching material layer to be etched, forms targeted graphical in material layer to be etched.During patterned, cover
The graphical quality of film layer has large effect to the quality of targeted graphical.
However, the process is more complicated for existing patterning process.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, with the patterned technique mistake of simplification
Journey.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide substrate, substrate
Upper to have bottom mask layer, bottom mask layer includes several firstth areas, and several firstth areas are along first direction and second direction
Arrangement, first direction and second direction are vertical, have the secondth area, the secondth area packet between adjacent firstth area arranged in the first direction
Middle area is included and positioned at the marginal zone of middle area two sides, from intermediate district center to marginal zone center parallel in first direction, along
There is third area between adjacent firstth area of two directions arrangement；Discrete top exposure mask knot is formed in the firstth area of bottom mask layer
Structure, top mask structure include top mask layer, and top mask structure also extends to the part of the surface of marginal zone；It is to cover to push up mask structure
Film, marginal zone and third area to bottom mask layer are modified processing, the marginal zone of mask layer and bottom of at
Modified layer is formed in 3rd area；Modified layer is removed, forms groove in the marginal zone of bottom mask layer and in third area, and make
The firstth area of bottom mask layer and middle area form the bottom mask layer between adjacent grooves.
Optionally, the top mask structure only includes top mask layer.
Optionally, the top mask structure includes pushing up mask layer and the side wall positioned at top mask layer side wall；The semiconductor
The forming method of device further include: after forming modified layer, remove side wall；After removing modified layer and side wall, removal top mask layer.
Optionally, the side wall is removed during removing the modified layer.
Optionally, after removing the side wall, the modified layer is removed.
Optionally, the top mask layer is located in the firstth area, and the top mask layer is with opposite the first side wall and relatively
Second sidewall, the both ends of second sidewall connect with opposite the first side wall respectively, and the first side wall is parallel with second direction, second
Side wall is parallel with first direction；The first side wall is parallel with the interface in the firstth area and marginal zone and connects；The first side wall surface
Side wall is located in the part of the surface of bottom mask layer marginal zone, and the side wall on second sidewall surface is located at bottom mask layer first
In area's part of the surface.
Optionally, the material of the side wall includes silica.
Optionally, the bottom mask layer with a thickness of 50 angstroms~300 angstroms；The material of the bottom mask layer includes
Silicon nitride.
Optionally, the step of modification includes: to adulterate in the marginal zone and third area of bottom mask layer
Modified ion.
Optionally, the modified ion includes hydrogen ion.
Optionally, the step of modification include: using plasma to the marginal zone of bottom mask layer and
Third area is bombarded.
Optionally, the plasma includes He plasma.
Optionally, the technique of the modification includes orienting band-like plasma-treating technology, and the orientation is band-like etc.
The band shaped plasma that gas ions treatment process uses has band-like extending direction；The band-like plasma-treating technology of orientation
Parameter include: the gas of use include H2, H2Flow be 50sccm~500sccm, source radio-frequency power be 100 watts~1000
Watt, bias voltage is 0 volt~200 volts, and chamber pressure is 5mtorr~100mtorr, and injection angle is 5 degree~25 degree, and the time is
10s~600s, the band-like extending direction are parallel with second direction；Alternatively, the band-like plasma-treating technology of orientation
Parameter includes: that the gas of use includes He, and the flow of He is 50sccm~500sccm, and source radio-frequency power is 100 watts~1000
Watt, bias voltage is 0 volt~200 volts, and chamber pressure is 5mtorr~100mtorr, and injection angle is 5 degree~25 degree, and the time is
10s~600s, the band-like extending direction are parallel with second direction.
Optionally, etching removal modified layer；The technique for removing modified layer is greater than to bottom exposure mask the etch rate of modified layer
The etch rate in material layer the firstth area and middle area.
Optionally, the technique for removing the modified layer includes wet-etching technique.
Optionally, the technique of modified layer is removed to modified layer relative to the etching selection ratio to the firstth area of bottom mask layer
Value is 10~100, removes the technique of modified layer to modified layer relative to the etching selection ratio to bottom mask layer middle area
It is 10~100.
Optionally, the material of the top mask layer is amorphous silicon or agraphitic carbon.
Optionally, it is described top mask structure with a thickness of 170nm~800nm；Secondth area is being parallel to first direction
On size be 80nm~120nm；The middle area is being parallel to first in the size and the secondth area being parallel on first direction
The ratio of size is 3/10~2/5 on direction.
Optionally, the substrate includes semiconductor substrate and the material layer to be etched in semiconductor substrate；Described half
The forming method of conductor device further include: after removing the modified layer, remove the top mask layer；Remove the top mask layer
Afterwards, using bottom mask layer as mask etching material layer to be etched.
The present invention also provides a kind of semiconductor devices formed using above-mentioned any one method.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, pass through the marginal zone to bottom mask layer
And modified remove again in third area is formed by modified layer, so as to form bottom mask layer.Adjacent bottom is covered in a first direction
The distance between film layer is less than the distance between adjacent top mask structure, keeps the density of bottom mask layer in a first direction larger,
To overcome the inaccessiable photolithography limitation of single composition.Due to only needing to form top mask structure, formation modified layer and going
Except modified layer can be achieved with forming bottom mask layer, without carrying out other photoetching processes, therefore patterned technique is simplified
Process.
Further, the technique of modified layer is removed to modified layer relative to the etching selection ratio to the firstth area of bottom mask layer
Value is 10~100, removes the technique of modified layer to modified layer relative to the etching selection ratio to bottom mask layer middle area
Be 10~100, thus remove modified layer technique to the etch rate of modified layer relative to the firstth area of bottom mask layer
Etching selection ratio is larger, removes the technique of modified layer to modified layer relative to the etching selection to bottom mask layer middle area
Ratio is larger, thus the etching in the firstth area of bottom mask layer and middle area is lost smaller.Therefore the work of modified layer is removed
Skill, it is smaller to the differential loss between at the top and bottom of the firstth area of bottom mask layer, at the top of the mask layer middle area of bottom
Differential loss between bottom is smaller.And bottom mask layer is formed by the firstth area of bottom mask layer and middle area, therefore bottom is covered
The edge roughness of film layer side wall is smaller.
Detailed description of the invention
Fig. 1 to Fig. 7 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention；
Fig. 8 to Figure 11 is the structural schematic diagram of semiconductor devices forming process in another embodiment of the present invention.
Specific embodiment
As described in background, the process is more complicated for the semiconductor devices that the prior art is formed.
A kind of forming method of semiconductor devices, comprising: material layer to be etched is provided；It is formed in material layer to be etched more
A discrete sacrificial layer；Form the first side wall and the second side wall in the side wall of sacrificial layer, the both ends of the second side wall respectively with it is adjacent
The connection of the first side wall, the second side wall and the first side wall structure annular in shape；Remove the second side wall；After removing the second side wall, removal
Sacrificial layer；After removing sacrificial layer, using first side wall as mask etching material layer to be etched, formed in material layer to be etched
Pattern.
However, the process is more complicated for the semiconductor devices of above method formation, it has been investigated that, reason is:
The above method realizes dual composition, to overcome the inaccessiable photolithography limitation of single composition.
The second side wall can be formed in the side wall of sacrificial layer during forming the first side wall, form the first side wall and second
The technique that side wall needs that the technique of material layer and etching phase is answered to answer material layer by sedimentary facies.Etch material layer to be etched it
Before, it is also necessary to the second side wall is removed.And remove the second side wall to be formed corresponding mask layer, with corresponding mask layer to cover
The step of film etches the second side wall and removes corresponding mask layer.As it can be seen that needing to increase work by more processing step
Skill complexity.
On this basis, the present invention provides a kind of forming method of semiconductor devices, in the firstth area of bottom mask layer
Discrete top mask structure is formed, top mask structure includes top mask layer, and top mask structure also extends to the part table of marginal zone
Face；To push up mask structure as exposure mask, marginal zone and third area to bottom mask layer are modified processing, in bottom exposure mask material
Modified layer is formed in the marginal zone and third area of the bed of material；Modified layer is removed, in the marginal zone of bottom mask layer and the
Groove is formed in 3rd area, and the firstth area of bottom mask layer and middle area is made to form the bottom mask layer between adjacent grooves.
The method simplifies patterned technical process.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 7 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
In conjunction with reference Fig. 1 and Fig. 2, Fig. 2 is the sectional view along cutting line M-N in Fig. 1, provides substrate 100, substrate 100
Upper have a bottom mask layer 110, and bottom mask layer 110 includes several firstth area A, several firstth area A along first direction X and
Second direction Y arrangement, first direction X and second direction Y are vertical, have the between the adjacent firstth area A of first direction X arrangement
Two area B, the second area B include middle area B1 and the marginal zone B2 positioned at the middle area two sides B1, from the middle area center B1 to marginal zone
B2 center parallel has third area C between the adjacent firstth area A of Y arrangement in a second direction in first direction X.
The substrate 100 includes semiconductor substrate 101 and the material layer to be etched 102 in semiconductor substrate 101.
The semiconductor substrate 101 provides technique platform to form semiconductor devices.
The material of the semiconductor substrate 101 can be monocrystalline silicon, polysilicon or amorphous silicon；The semiconductor substrate 101
It is also possible to the semiconductor materials such as silicon, germanium, SiGe, GaAs；The semiconductor substrate 101 can be single layer structure, can also
To be composite construction, such as silicon-on-insulator；The semiconductor substrate 101 can also be other semiconductor materials, not another here
One citing.In the present embodiment, the material of the semiconductor substrate 101 is monocrystalline silicon.
The material layer to be etched 102 is the subsequent material layer for needing to etch.The material layer to be etched 102 can be single
Layer or multilayer lamination structure.
The material of the material layer to be etched 102 can be semiconductor material, the material of the material layer 102 to be etched
It can be dielectric material, such as silica or low K (K is less than 3.9) dielectric material.In the present embodiment, the material layer 102 to be etched
Material be silica.
Semiconductor structure can also be formed in the material layer to be etched 102, as PMOS transistor, NMOS transistor,
Resistance or capacitor.
In the present embodiment, the substrate 100 further includes the middle layer 103 positioned at 102 surface of material layer to be etched.In described
The effect of interbed 103 includes: the stop-layer as subsequent etching removal modified layer.
The material of the middle layer 103 includes polysilicon.
In other embodiments, substrate does not include middle layer.
The bottom mask layer 110 is used to form bottom mask layer.In the present embodiment, bottom mask layer 110 is located at
103 surface of middle layer.
The material of the bottom mask layer 110 includes silicon nitride.
The bottom mask layer 110 with a thickness of 50 angstroms~300 angstroms, the thickness of bottom mask layer 110 selects this model
The meaning enclosed is: if the thickness of bottom mask layer 110 is excessive, will affect top and bottom Doped ions in successive modified layer
Distributional difference；If the thickness of bottom mask layer 110 is too small, cause the thickness of subsequent bottom mask layer too small, subsequent etching waits for
The exposure mask effect of mask layer at the bottom of when etachable material layer 102 is poor, and larger deformation occurs for 102 pattern of material layer to be etched.
Continuing with reference Fig. 1 and Fig. 2, discrete top mask structure is formed on 110 first area A of bottom mask layer,
Pushing up mask structure includes top mask layer 120, and top mask structure also extends to the part of the surface of marginal zone B2.
In the present embodiment, top mask structure only includes top mask layer 120.
In the present embodiment, the top mask structure also extends to the part of the surface of marginal zone B2, specifically, top mask layer
120 also extend to the part of the surface of marginal zone B2.
In the present embodiment, the top mask layer 120 has opposite the first side wall and opposite second sidewall, second sidewall
Both ends connected respectively at opposite the first side wall, the first side wall is parallel with second direction, and second sidewall is parallel with first direction.
In the present embodiment, second sidewall is parallel with the interface of third area C and the first area A and connects, the first side wall and the first area A and side
The interface of edge area B2 is parallel.
The material of the top mask layer 120 is amorphous silicon or agraphitic carbon.
In the present embodiment, the method for forming top mask structure includes: that top mask layer is formed in substrate 100；Figure
Change top mask layer, forms top mask structure.
In the present embodiment, it is described top mask structure with a thickness of 170nm~800nm；The secondth area B is being parallel to first
Size on the X of direction is 80nm~120nm；The middle area B1 is in the size and the second area B being parallel on first direction X flat
Row is 3/10~2/5 in the ratio of size on first direction X.
With reference to Fig. 3, Fig. 3 is schematic diagram on the basis of Fig. 2, to push up mask structure as exposure mask, to bottom mask layer 110
Marginal zone B2 and third area C be modified processing, the shape in the marginal zone B2 and third area C of bottom mask layer 110
At modified layer 130.
In the present embodiment, the step of modification includes: the marginal zone B2 and third in bottom mask layer 110
Doping vario-property ion in area C.Correspondingly, keeping the material of modified layer 130 different with the material of bottom mask layer 110.
The modified ion includes hydrogen ion.
In other embodiments, the step of modification includes: side of the using plasma to bottom mask layer
It edge area and is bombarded along third area.Correspondingly, making the hardness of modified layer 130 less than the hardness of bottom mask layer 110.Institute
Stating plasma includes He plasma.
During subsequent etching removes modified layer 130, etching of the technique to modified layer 130 of modified layer 130 is removed
Rate is greater than the etch rate to 110 first area A and middle area B1 of bottom mask layer.
The technique of the modification includes plasma-treating technology, and the plasma-treating technology is for generation etc.
Gas ions, generated plasma is for adulterating or for bombarding.
In one embodiment, the technique of the modification is to orient band-like plasma-treating technology (Directed
ribbon-beam processing)。
With reference to Fig. 4, band-like plasma-treating technology is oriented with injection direction D, the injection direction D and substrate 100
There is injection angle between surface normal；Orient the band shaped plasma (plasma that band-like plasma-treating technology uses
Ribbon-beam) there is band-like extending direction E, band-like extending direction E and injection direction D are vertical, and band-like extending direction E is used for
It is parallel with second direction.
The principle of the band-like plasma-treating technology of orientation includes: that plasma source chamber generates plasma source；
Plasma source is extracted from plasma source chamber using band-like crack, specifically, plasma source is after band-like crack,
Form band shaped plasma；Band shaped plasma enters in processing chamber housing, and each material layer to be processed is located in processing chamber housing, band
There is injection angle, band shaped plasma is used between 110 surface normal of injection direction D and bottom mask layer of shape plasma
In doping or for bombarding.Specifically, during orienting band-like plasma-treating technology, band shaped plasma it is band-like
Extending direction E is parallel to second direction, and to push up mask structure as exposure mask, band shaped plasma is doped into bottom with injection direction D and covers
The marginal zone B2 and third area C of membrane layers 110, alternatively, band shaped plasma is to push up mask structure as exposure mask with the side of injection
It is bombarded to marginal zone B2 and third area C of the D to bottom mask layer 110.
The advantages of modified layer 130 are formed using the orientation band-like plasma-treating technology include: orientation it is band-like it is equal from
The directionality of daughter treatment process is preferable, can be strict controlled in the injection angle of each region, preferable to control modified layer 130
Size.
In one embodiment, the parameter of the band-like plasma-treating technology of orientation includes: that the gas of use includes
H2, H2Flow be 50sccm~500sccm, source radio-frequency power be 100 watts~1000 watts, bias voltage be 0 volt~200 volts, chamber
Chamber pressure is 5mtorr~100mtorr, and injection angle is 5 degree~25 degree, and the time is 10s~600s, the band-like extending direction
It is parallel with second direction.
In another embodiment, the parameter of the band-like plasma-treating technology of orientation includes: the gas packet of use
He is included, the flow of He is 50sccm~500sccm, and source radio-frequency power is 100 watts~1000 watts, and bias voltage is 0 volt~200
Volt, chamber pressure are 5mtorr~100mtorr, and injection angle is 5 degree~25 degree, and the time is 10s~600s, described band-like to prolong
It is parallel with second direction to stretch direction.
It is schematic diagram on the basis of Fig. 3 with reference to Fig. 5, Fig. 5, removal modified layer 130 (refers to Fig. 3), in bottom mask material
Groove 140 is formed in the marginal zone B2 of floor 110 and in third area C, and makes 110 first area A of bottom mask layer and middle area
B1 forms the bottom mask layer 150 between adjacent grooves 140.
Etching removal modified layer 130, the technique for removing modified layer 130, which is greater than the etch rate of modified layer 130, covers bottom
The etch rate of membrane layers 110 first area A and middle area B1.
The technique for removing modified layer 130 includes wet-etching technique.
In the present embodiment, the material of the bottom mask layer 110 includes silicon nitride；Used by removing modified layer 130
The parameter of wet-etching technique includes: the etching solution that uses for hydrofluoric acid solution, and the mass percent concentration of hydrofluoric acid is 0.1%~
10%, etching temperature is 20 degrees Celsius~70 degrees Celsius.
In the present embodiment, the technique of removal modified layer 130 is to modified layer 130 relative to bottom mask layer 110 first
The etching selection ratio of area A is 10~100, and the technique of removal modified layer 130 is to modified layer 130 relative to bottom mask layer
The etching selection ratio of 110 middle area B1 is 10~100, therefore removes the technique of modified layer 130, to the etching of modified layer 130
Rate is larger relative to the etching selection ratio to 110 first area A of bottom mask layer, covers to modified layer 130 relative to the bottom of to
The etching selection ratio of 110 middle area B1 of membrane layers is larger, to bottom mask layer 110 first area A's and middle area B1
Etching loss is smaller.Therefore the technique for removing modified layer 130, between at the top and bottom of 110 first area A of bottom mask layer
Differential loss is smaller, smaller to the differential loss between at the top and bottom of 110 middle area B1 of bottom mask layer.And bottom mask layer
150 are formed by bottom mask layer 110 first area A and middle area B1, thus the edge roughness of 150 side wall of bottom mask layer compared with
It is small.
It is schematic diagram on the basis of Fig. 5 in conjunction with reference Fig. 6 and Fig. 7, Fig. 6, Fig. 7 is in Fig. 6 towards bottom mask layer 150
Top view, after removing the modified layer 130, removal top mask layer 120 (referring to Fig. 5).
The technique of removal top mask layer 120 is etching technics, such as remote plasma etching technics.
In the present embodiment, top mask layer 120 is removed using remote plasma etching technics, advantage includes: to bottom exposure mask
The etching loss of layer 150 is less.
In the present embodiment, further includes: after the mask layer 120 of removal top, with bottom mask layer 150 for mask etching corrosion material to be etched
Layer 102, forms target pattern in material layer 102 to be etched.
In the present embodiment, further includes: after the mask layer 120 of removal top, and be that mask etching is to be etched with bottom mask layer 150
Before material layer 102, with bottom mask layer 150 for mask etching middle layer 103.
In the present embodiment, in a first direction on X the distance between adjacent bottom mask layer 150 be less than adjacent top mask structure it
Between distance, keep density of the bottom mask layer 150 in a first direction on X larger, to overcome the inaccessiable light of single composition
Carve the limit.Due to only needing to form top mask structure, forming modified layer 130 and removal modified layer 130 can be achieved with forming bottom and cover
Film layer 150 without carrying out other photoetching processes, therefore simplifies patterned technical process.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method.
Another embodiment of the present invention also provides a kind of forming method of semiconductor devices, the present embodiment and previous embodiment
Difference is: the top mask structure includes pushing up mask layer and the side wall positioned at top mask layer side wall；The semiconductor devices
Forming method further include: after forming modified layer, remove side wall；After removing modified layer and side wall, removal top mask layer.About this reality
It applies in example with content identical in previous embodiment, is no longer described in detail.
Fig. 8 to Figure 11 is the structural schematic diagram of semiconductor devices forming process in another embodiment of the present invention.
With reference to Fig. 8, substrate 100 is provided, there is bottom mask layer 110 in substrate 100, bottom mask layer 110 includes
Several firstth area A, several firstth area A are arranged along first direction X and second direction Y, and first direction X and second direction Y are vertical, edge
First direction X arrangement adjacent firstth area A between have the second area B, the second area B include middle area B1 and be located at middle area B1 two
The marginal zone B2 of side, from the middle area center B1 to marginal zone B2 center parallel in first direction X, the phase that Y is arranged in a second direction
There is third area between the first area A of neighbour.
The substrate 100 includes semiconductor substrate 101 and the material layer to be etched 102 in semiconductor substrate 101.Institute
The material of semiconductor substrate 101 is stated referring to previous embodiment.The material of the material layer to be etched 102 is referring to previous embodiment.
In the present embodiment, the substrate 100 further includes the middle layer 103 positioned at 102 surface of material layer to be etched.In described
The effect of interbed 103 includes: the stop-layer as subsequent etching removal modified layer and side wall.The material packet of the middle layer 103
Include polysilicon.In other embodiments, substrate does not include middle layer.
Position, material and the thickness of the bottom mask layer 110 are referring to previous embodiment.
With continued reference to Fig. 8, discrete top mask structure 220 is formed on 110 first area A of bottom mask layer, pushes up exposure mask
Structure 220 includes top mask layer 221 and the side wall 222 positioned at top 221 side wall of mask layer, and top mask structure 220 also extends to side
The part of the surface of edge area B2.
The material and forming step of the top mask layer 221 are referring to the material and forming step for pushing up mask layer 120.The side
The material of wall 222 includes silica.
The effect of the side wall 222 includes: at the bottom that the figure for pushing up mask layer 221 is transferred to top 221 bottom of mask layer
During mask layer, make the dimension of picture phase of the bottom mask layer for pushing up 221 bottom of mask layer and dimension of picture and top mask layer 221
Difference is smaller.
The step of forming side wall 222 includes: the side wall and top surface and substrate in the top mask layer 221
Spacer material layer is formed on 100；Spacer material layer is etched back to until exposing the top surface and substrate 100 of top mask layer 221
Surface forms side wall 222.
The technique for forming the spacer material layer is depositing operation, such as atom layer deposition process or plasma enhanced chemical vapor
Depositing operation.
In the present embodiment, the technique for forming the spacer material layer is atom layer deposition process.Benefit includes: to make side wall material
The thickness uniformity of the bed of material is preferable.
In the present embodiment, the top mask layer 221 is located on the first area A, and the top mask layer 221 has opposite first
Side wall and opposite second sidewall, the both ends of second sidewall are connect with opposite the first side wall respectively, the first side wall and second party
To parallel, second sidewall is parallel with first direction；The first side wall is parallel with the interface of the first area A and marginal zone B2 and connects；
The side wall 222 on the first side wall surface is located in the part of the surface of 110 marginal zone B2 of bottom mask layer；The side on second sidewall surface
Wall 222 is located on 110 first area part A surface of bottom mask layer.
With reference to Fig. 9, with the marginal zone B2 and third area for pushing up mask structure 220 for exposure mask, to bottom mask layer 110
It is modified processing, forms modified layer 230 in the marginal zone B2 of bottom mask layer 110 and third area.
The process of modified layer 230 is formed referring to the process for forming modified layer 130.
With reference to Figure 10, modified layer 230 (referring to Fig. 9) is removed, in the marginal zone B2 of bottom mask layer 110 and third
Groove 240 is formed in area, and forms bottom mask layer 110 first area A and middle area B1 between adjacent grooves 240
Bottom mask layer 250.
Etching removal modified layer 230, the technique for removing modified layer 230, which is greater than the etch rate of modified layer 230, covers bottom
The etch rate of membrane layers 110 first area A and middle area B1.
The technique of removal modified layer 230 includes wet-etching technique, and parameter is referring to previous embodiment.
The technique for removing modified layer 230 selects modified layer 230 relative to the etching to 110 first area A of bottom mask layer
Selecting ratio is 10~100；First etching technics is to modified layer 230 relative to 110 middle area B1's of bottom mask layer
Etching selection ratio is 10~100.
In the present embodiment, further includes: after forming modified layer 230, removal side wall 222 (refers to Fig. 8).
In the present embodiment, the side wall 222 is removed during removing modified layer 230, simplifies technique.
In other embodiments, after removing side wall, modified layer is removed.
With reference to Figure 11, after removing modified layer 230 and side wall 222, removal top mask layer 221 (referring to Figure 10).
Technique of the technique of removal top mask layer 221 referring to removal top mask layer 120 in previous embodiment.
In the present embodiment, further includes: after the mask layer 221 of removal top, with bottom mask layer 250 for mask etching corrosion material to be etched
Layer 102, forms target pattern in material layer 102 to be etched.
In the present embodiment, further includes: after the mask layer 221 of removal top, and be that mask etching is to be etched with bottom mask layer 250
Before material layer 102, with bottom mask layer 250 for mask etching middle layer 103.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided, there is in substrate bottom mask layer, bottom mask layer includes several firstth areas, and several firstth areas are along the
One direction and second direction arrangement, first direction and second direction are vertical, have between adjacent firstth area arranged in the first direction
There is the secondth area, the secondth area includes middle area and positioned at the marginal zone of middle area two sides, is put down from intermediate district center to edge district center
It goes in first direction, there is third area between adjacent firstth area arranged in a second direction；
Discrete top mask structure is formed in the firstth area of bottom mask layer, top mask structure includes top mask layer, pushes up exposure mask
Structure also extends to the part of the surface of marginal zone；
To push up mask structure as exposure mask, marginal zone and third area to bottom mask layer are modified processing, in bottom exposure mask
Modified layer is formed in the marginal zone and third area of material layer；
Modified layer is removed, forms groove in the marginal zone of bottom mask layer and in third area, and make bottom mask layer
Firstth area and middle area form the bottom mask layer between adjacent grooves.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that the top mask structure only includes
Push up mask layer.
3. the forming method of semiconductor devices according to claim 1, which is characterized in that the top mask structure includes top
Mask layer and positioned at top mask layer side wall side wall；The forming method of the semiconductor devices further include: after forming modified layer, go
Except side wall；After removing modified layer and side wall, removal top mask layer.
4. the forming method of semiconductor devices according to claim 3, which is characterized in that in the mistake for removing the modified layer
The side wall is removed in journey.
5. the forming method of semiconductor devices according to claim 3, which is characterized in that after removing the side wall, removal
The modified layer.
6. the forming method of semiconductor devices according to claim 3, which is characterized in that the top mask layer is located at first
Qu Shang, the top mask layer have opposite the first side wall and opposite second sidewall, and the both ends of second sidewall are respectively and relatively
The first side wall connection, the first side wall is parallel with second direction, and second sidewall is parallel with first direction；The first side wall and the firstth area
And connection parallel with the interface of marginal zone；The side wall on the first side wall surface is located at the part of the surface of bottom mask layer marginal zone
On, the side wall on second sidewall surface is located in the firstth area of bottom mask layer part of the surface.
7. the forming method of semiconductor devices according to claim 3, which is characterized in that the material of the side wall includes oxygen
SiClx.
8. the forming method of semiconductor devices according to claim 1, which is characterized in that the thickness of the bottom mask layer
Degree is 50 angstroms~300 angstroms；The material of the bottom mask layer includes silicon nitride.
9. the forming method of semiconductor devices according to claim 1, which is characterized in that the step of modification wraps
It includes: the doping vario-property ion in the marginal zone and third area of bottom mask layer.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that the modified ion includes hydrogen
Ion.
11. the forming method of semiconductor devices according to claim 1, which is characterized in that the step of the modification
It include: that using plasma bombards the marginal zone of bottom mask layer and third area.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the plasma includes He
Plasma.
13. the forming method of semiconductor devices according to claim 1, which is characterized in that the technique of the modification
Including orienting band-like plasma-treating technology, the band shaped plasma tool that the band-like plasma-treating technology of orientation uses
There is band-like extending direction；
The parameter of the band-like plasma-treating technology of orientation includes: that the gas of use includes H2, H2Flow be 50sccm~
500sccm, source radio-frequency power be 100 watts~1000 watts, bias voltage be 0 volt~200 volts, chamber pressure be 5mtorr~
100mtorr, injection angle is 5 degree~25 degree, and the time is 10s~600s, and the band-like extending direction is parallel with second direction；
Alternatively, the gas that the parameter of the band-like plasma-treating technology of orientation includes: use includes He, the flow of He is
50sccm~500sccm, source radio-frequency power are 100 watts~1000 watts, and bias voltage is 0 volt~200 volts, and chamber pressure is
5mtorr~100mtorr, injection angle is 5 degree~25 degree, and the time is 10s~600s, the band-like extending direction and second party
To parallel.
14. the forming method of semiconductor devices according to claim 1, which is characterized in that etching removal modified layer；Removal
The technique of modified layer is greater than the etch rate to bottom mask layer the firstth area and middle area to the etch rate of modified layer.
15. the forming method of semiconductor devices according to claim 14, which is characterized in that remove the work of the modified layer
Skill includes wet-etching technique.
16. the forming method of semiconductor devices according to claim 14, which is characterized in that remove the technique pair of modified layer
Modified layer is 10~100 relative to the etching selection ratio to the firstth area of bottom mask layer, removes the technique of modified layer to changing
Property layer relative to the etching selection ratio to bottom mask layer middle area be 10~100.
17. the forming method of semiconductor devices according to claim 1, which is characterized in that the material of the top mask layer
For amorphous silicon or agraphitic carbon.
18. the forming method of semiconductor devices according to claim 1, which is characterized in that the thickness of the top mask structure
Degree is 170nm~800nm；Secondth area is 80nm~120nm in the size being parallel on first direction；The middle area exists
The ratio of the size and the secondth area size on being parallel to first direction that are parallel on first direction is 3/10~2/5.
19. the forming method of semiconductor devices according to claim 1, which is characterized in that the substrate includes semiconductor
Substrate and the material layer to be etched in semiconductor substrate；The forming method of the semiconductor devices further include: described in removal
After modified layer, the top mask layer is removed；After removing the top mask layer, using bottom mask layer as mask etching corrosion material to be etched
Layer.
20. a kind of according to claim 1 to the semiconductor devices that 19 any one methods are formed.
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