CN105845568B - A kind of semiconductor devices and preparation method thereof - Google Patents
A kind of semiconductor devices and preparation method thereof Download PDFInfo
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- CN105845568B CN105845568B CN201510014277.4A CN201510014277A CN105845568B CN 105845568 B CN105845568 B CN 105845568B CN 201510014277 A CN201510014277 A CN 201510014277A CN 105845568 B CN105845568 B CN 105845568B
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, which comprises provides semiconductor substrate, is formed with multiple dummy gate structures on the surface of a semiconductor substrate, forms matcoveredn on the top surface of dummy gate structure；Masking layer is formed on the surface of protective layer, the surrounded surface of dummy gate structure exposure and semiconductor substrate exposure；Deposition forms sacrificial layer covering semiconductor substrate, wherein top surface of the top surface of sacrificial layer lower than the masking layer on protective layer；Ion implanting is carried out to the masking layer of exposure on protective layer；Remove sacrificial layer and the part masking layer on semiconductor substrate surface；Semiconductor substrate is etched, to form groove in the semiconductor substrate of the two sides of the dummy gate structure；Stressor layers are formed in the groove.Production method according to the present invention plays better protective effect to dummy gate structure, avoids the pollution problem in the generation and polysilicon gate removal process of the mushroom effect of polysilicon dummy gate to device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof.
Background technique
With the continuous development of semiconductor technology, the raising of performance of integrated circuits mainly passes through constantly diminution integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to that nanotechnology process node is partly led especially when dimensions of semiconductor devices drops to Nano grade
The preparation of body device receives the limitation of various physics limits.
When the size of semiconductor devices drops to Nano grade, gate critical dimension (gate CD) contracts accordingly in device
It is small.With the reduction of technology node, traditional gate dielectric layer is constantly thinning, and transistor leakage amount increases therewith, causes semiconductor
The problems such as device power consumption wastes.To solve the above problems, avoiding high-temperature process simultaneously, the prior art provides a kind of by high K
The solution of metal gates substitution polysilicon gate.
After existing high k/ during the making technology of metal gate, in order to improve the mobility of carrier, often in source
Drain extensions growth stress layer, such as compression material germanium silicon is used in the manufacturing method of PMOS device, in NMOS device
Tensile stress material carbon silicon is used in manufacturing method.
Before stressor layers production, need first to deposit one layer of silicon nitride layer, to protect dummy gate.The thickness of silicon nitride layer
More Bao Yuehao, however protection is lost to dummy gate during stressor layers recess etch since thickness is too thin and will lead to it and is made
With leading to mushroom effect (mushroom defect).Mushroom effect can have a negative impact to MEOL processing procedure, especially polycrystalline
When the removal of silicon dummy gate, it is easy to cause pollution problem, so that yield of devices and reduced performance.
Therefore, it is necessary to propose a kind of new production method, so as to solve the deficiencies in the prior art.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the embodiment of the present invention one provides a kind of production method of semiconductor devices, packet
It includes:
Semiconductor substrate is provided, multiple dummy gate structures are formed on the surface of the semiconductor substrate, in the puppet
Matcoveredn is formed on the top surface of gate structure；
On the surface of the protective layer, the surrounded surface of dummy gate structure exposure and semiconductor substrate exposure
Form masking layer；
Deposition forms sacrificial layer and covers the semiconductor substrate, wherein the top surface of the sacrificial layer is lower than on the protective layer
Masking layer top surface；
Ion implanting is carried out to the masking layer of exposure on the protective layer；
Remove the sacrificial layer and the part masking layer on the semiconductor substrate surface；
The semiconductor substrate is etched, to form groove in the semiconductor substrate of the two sides of the dummy gate structure；
Stressor layers are formed in the groove.
Optionally, the dummy gate structure includes gate dielectric from bottom to top and gate material layers.
Optionally, the injection ion of the ion implanting is selected from one or more of C or Si.
It optionally, further include being made annealing treatment before removing the sacrificial layer after the ion implanting step
Step.
Optionally, form the technique of the sacrificial layer the following steps are included:
Deposition forms sacrificial material layer on the semiconductor substrate, and the top surface of the sacrificial material layer is made to be higher than the guarantor
The top surface of masking layer on sheath；
Sacrificial material layer described in etch-back, to form sacrificial layer.
Optionally, the material of the sacrificial layer is polysilicon or oxide.
Optionally, after removing the sacrificial layer step, it further includes using at ozone that etching, which forms the groove before,
The step of managing the semiconductor substrate surface.
Optionally, the material of the protective layer is silica, silicon oxynitride or silica/silicon nitride stack, the masking
The material of layer is silicon nitride or silicon oxynitride.
Optionally, the material of the stressor layers is selected from SiN, SiGe and SiC any of them or combinations thereof.
Second embodiment of the present invention provides a kind of semiconductor devices of method production above-mentioned.
In conclusion production method according to the present invention, carries out ion implanting to the masking layer in dummy gate structure, increases
Its strong ability for resisting etching, plays better protective effect to dummy gate structure, avoids the mushroom of polysilicon dummy gate
Pollution problem in the generation and polysilicon gate removal process of effect (mushroom defect) to device, and then improve device
The yield and performance of part.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A -1G shows production method according to the present invention successively implementation steps institute acquisition device
The diagrammatic cross-section of part；
Fig. 2 shows the process flow charts of production method according to the present invention successively implementation steps.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
Embodiment one
It is described in detail below with reference to production method of Figure 1A -1G and Fig. 2 to semiconductor devices of the invention.
Firstly, providing semiconductor substrate 100 with reference to Figure 1A, it is formed on the surface of the semiconductor substrate 100 multiple
Dummy gate structure forms matcoveredn 104 on the top surface of the dummy gate structure.
The semiconductor substrate 100 can be following at least one of the material being previously mentioned: silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..Preferred silicon-on-insulator (SOI) in the present invention, the silicon-on-insulator
(SOI) it is followed successively by support substrate, oxide insulating layer and semiconductor material layer from the bottom up, but is not limited to above-mentioned show
Example.
Isolation structure 101 is formed in the semiconductor substrate 100, the isolation structure 101 is shallow trench isolation (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure.In the present embodiment, the isolation structure is fleet plough groove isolation structure.Institute
State the channel layer (not shown) that various traps (well) structure and substrate surface are also formed in semiconductor substrate 100.In general,
The ion doping conduction type for forming trap (well) structure is identical as channel layer ion doping conduction type, but concentration is compared with grid
Channel layer is low, and the depth of ion implanting is general to enclose relatively extensively, while need to reach the depth greater than isolation structure.
The dummy gate structure includes the gate dielectric 103 being formed in the semiconductor substrate 100 and is formed in institute
State the gate material layers 102 on gate dielectric 103.Gate dielectric 103 can be silica (SiO2) silicon oxynitride
(SiON).Further, gate dielectric 103 extends over the surface of entire semiconductor substrate 100.Gate material layers 102 can be with
For undoped polysilicon layer, the polysilicon and polysilicon-Ge alloy material that also may include doping are (that is, have from every cube
The doping concentration of centimetre about 1e18 to about 1e22 foreign atom) and polycide (polycide) material
(polysilicon of doping/metal silicide laminated material).Similarly, it can also be formed using any one of several methods aforementioned
Material.Non-limiting example includes self-aligned metal silicate method, process for chemical vapor deposition of materials and physical vapor deposition methods,
Such as, but not limited to: method of evaporating and sputtering method.In general, gate material layers 102 include having thickness from about 50 to about
2000 angstroms of polycrystalline silicon material.
It is formed to be formed on the top surface of matcoveredn namely gate material layers 102 on the top surface of the dummy gate structure and be protected
Sheath 104.Protective layer 104 may include any one of several protective layer materials, including but not limited to silica, silicon oxynitride
Or silica/silicon nitride stack, in the present embodiment, the material of the protective layer 104 is preferably silica/silicon nitride stack.
A is continued to refer to figure 1, in the protective layer 104, the surrounded surface and the semiconductor of dummy gate structure exposure
Masking layer 105 is formed on the surface of the exposure of substrate 100.
The constituent material of masking layer 105 can be SiN, SiON or their combination.As an example, in the present embodiment
Masking layer 105 is constituted using SiN.Any applicable deposition method can be used and form the masking layer 105, including but not limited to
The techniques such as chemical vapor deposition, atomic layer deposition, physical vapour deposition (PVD), for example, SiH can be used4、NH3And N2As source gas
Body forms SiN layer at 350~550 DEG C.Masking layer 105 can have different thickness, and usual range is 50 to 300 angstroms.It covers
Cover layer 105 its be mainly used for it is subsequent be etched or when ion implanting protection gate structure it is injury-free.
With reference to Figure 1B, deposition forms sacrificial material layer 106a in the semiconductor substrate 100, makes the sacrificial material layer
The top surface of 106a is higher than the top surface of the masking layer 105 on the protective layer 104.
Sacrificial material layer 106a may include several any one with the masking layer 105 with high etching selectivity
Material, including but not limited to: polysilicon or oxide material, oxide material include but is not limited to silica, silicon oxynitride etc.,
Preferably, including silica material.Sacrificial material layer 106a can be used including but not limited to: chemical vapor deposition method and object
The method of physical vapor deposition method is formed.
With reference to Fig. 1 C, sacrificial material layer 106a described in etch-back, to form sacrificial layer 106.
The etching selectivity that the etch back process has sacrificial material layer 106a high to masking layer 105, such as etching choosing
It selects than being greater than 50:1, to guarantee only to be etched sacrificial material layer 106a in etch-back process, without corroding masking layer
105。
In a specific embodiment of the invention, the etch back process, dry etching can be executed using dry etching
Technique includes but is not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as it adopts
With plasma etching, etching gas can be using based on oxygen (O2- based) gas.Specifically, using lower radio frequency
Energy simultaneously can generate low pressure and highdensity plasma gas to realize dry etching.As an example, using plasma
Body etching technics, for the etching gas used for the gas based on oxygen (O2-based), the range of flow of etching gas can be 50
Cc/min (sccm)~150 cc/min (sccm), reaction room pressure can be 5 millitorrs (mTorr)~20
Millitorr (mTorr).Wherein, the etching gas of dry etching can also be bromination hydrogen, carbon tetrafluoride gas or borontrifluoride
Nitrogen.It should be noted that above-mentioned engraving method is only exemplary, it is not limited to this method, those skilled in the art
Other common methods can also be selected.It is noted that the etch depth of etch-back depends on the height of dummy gate,
The numberical range of this not concrete restriction etch depth.
After etch back process, the top surface of the sacrificial layer 106 of formation is lower than the masking layer 105 on the protective layer 104
Top surface so that above dummy gate structure 105 part of masking layer exposure.
With reference to Fig. 1 D, ion implanting is carried out to the masking layer 105 of exposure on the protective layer 104.
The technique that any method well known to those skilled in the art carries out the ion implanting can be used.Illustratively, institute
The injection ion for stating ion implanting is selected from one or more of C or Si.By way of ion implanting, so that the masking of exposure
Injection ion in layer 105 increases, and in etching process later, etchant can also be reacted with the ion of injection, relatively
Reduction to the consumption of masking layer 105 so that masking layer 105 under the precursor for not increasing its thickness, can enhance its resistance
The ability of etching, and then better protective effect is played to dummy gate structure below.
After ion implanting, further include the steps that annealing, so that the ion of injection is uniformly distributed in masking layer.Show
Example property, the temperature range of the annealing is 300~800 DEG C.Any applicable annealing way can be used and carry out the annealing, example
Such as short annealing, pipe furnace annealing or laser annealing.
With reference to Fig. 1 E, the sacrificial layer 106 is removed.
Both the sacrificial layer 106 can be removed using dry ecthing method or using wet etch method.Dry ecthing method can be adopted
With the anisotropic etch process based on carbon fluoride gas.Wet etch method can use hydrofluoric acid solution, such as buffer oxide to lose
Carve agent (buffer oxide etchant (BOE)) or hydrofluoric acid buffer solution (buffer solution of
hydrofluoric acid(BHF)).Above-mentioned dry ecthing method or wet etch method all have high etching choosing of the sacrificial layer to masking layer
Select ratio.
With reference to Fig. 1 F, removal is located at the part masking layer 105 on 100 surface of semiconductor substrate.
Removal is located at the method for the part masking layer 105 on 100 surface of semiconductor substrate according to the material of masking layer
It is selected, dry ecthing method or wet etch method can also be adopted, for example, anisotropic dry etching, only etching removal correspondence is partly led
The masking layer 105 of the part of source/drain region in body substrate 100.
Later, also optionally with 100 surface of semiconductor substrate described in ozone treatment, so that semiconductor substrate surface
Gate dielectric 103 (namely oxide layer) is more uniform, and etching is damaged caused by it before repairing.
With reference to Fig. 1 G, the semiconductor substrate 100 is etched, in the semiconductor substrate of the two sides of the dummy gate structure
Groove is formed in 100, and stressor layers 107 are formed in the groove.
It is exposure mask with masking layer 105, etches the semiconductor substrate 100, the half of the two sides of the dummy gate structure
The part for making a reservation for be formed the source/drain region of the semiconductor device structure in conductor substrate 100 forms groove.The shape of the groove
It can be " ∑ " shape or " u "-shaped, be preferably formed as " ∑ " connected in star in the present invention.
The source-drain area part in semiconductor substrate 100 described in dry etching can be selected in this step, in the dry method
CF can be selected in etching4、CHF3, in addition add N2、CO2、O2One of as etching atmosphere, wherein gas flow be
CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure are 30-150mTorr, erosion
Time at quarter is 5-120s, preferably 5-60s, more preferably 5-30s.
Then, stressor layers 107 are formed in the groove.As an example, by extension (EPI) method growth stress layer 107,
The material of the stressor layers 107 can be but not limited to SiN, SiGe or SiC or their any combination.Alternatively,
Stressor layers 107 can be formed by chemical vapour deposition technique.Here it is to be noted that it can be according to semiconductor device structure
Polarity come the stress that selects deposited stressor layers 107 to have, for example, the stress that NMOS device structure needs to have tensile stress
Layer 107, can use SiH4、NH3And N2As source gas, the SiN layer with tensile stress is formed at 350~550 DEG C,
In, SiH4Flow velocity be 320~340sccm, NH3Flow velocity be 3000~3400sccm, N2Flow velocity be 3800~
4200sccm, the stressor layers 107 of NMOS device structure can also be SiC.
And the stressor layers 107 that PMOS device structure needs to have compression, such as germanium silicon layer, the deposition of the SiGe layer can
To select chemical vapor deposition (CVD) method, non-selective chemical vapor deposition (CVD) method physical vapour deposition (PVD) of selectivity
(PVD) low-pressure chemical vapor deposition (LPCVD) of the formation such as method or atomic layer deposition (ALD) method, laser ablation deposition (LAD) with
And one of selective epitaxy growth (SEG).Illustratively, SiH can be used4Or SiH2Cl2As silicon source gas and use
GeH4, HCl and H2Deng mixed gas as ge source gas, wherein the flow velocity of silicon source gas be 30~300sccm, ge source gas
Middle GeH4Flow velocity be 5~500sccm, and the flow velocity of preferably 5~50sccm, HCl be 50~200sccm, H2Flow velocity be 5
~50sccm.
Finally, removal masking layer, so that the semiconductor device structure comprising stressor layers is formed, it can be according to masking layer
Constituent material select minimizing technology appropriate, the method that removes various masking layers be it is well-known to those skilled in the art,
Details are not described herein.
The above method, the production for being not only suitable for PMOS device structure are also applied for the production of NMOS device structure, while
Suitable for FINFET device.
In conclusion production method according to the present invention, carries out ion implanting to the masking layer in dummy gate structure, increases
Its strong ability for resisting etching, plays better protective effect to dummy gate structure, avoids the mushroom of polysilicon dummy gate
Pollution problem in the generation and polysilicon gate removal process of effect (mushroom defect) to device, and then improve device
The yield and performance of part.
Referring to Fig. 2, the process flow chart for a step of specific embodiment of the invention is successively implemented is shown, for letter
The process of entire manufacturing process is shown.
In step 201, semiconductor substrate is provided, multiple dummy grid knots are formed on the surface of the semiconductor substrate
Structure forms matcoveredn on the top surface of the dummy gate structure；
In step 202, in the protective layer, the surrounded surface of dummy gate structure exposure and the semiconductor substrate
Masking layer is formed on exposed surface；
In step 203, deposition forms sacrificial layer and covers the semiconductor substrate, wherein the top surface of the sacrificial layer is lower than
The top surface of masking layer on the protective layer；
In step 204, ion implanting is carried out to the masking layer of exposure on the protective layer；
In step 205, the sacrificial layer and the part masking layer on the semiconductor substrate surface are removed；
In step 206, the semiconductor substrate is etched, in the semiconductor substrate of the two sides of the dummy gate structure
Form groove；
In step 207, stressor layers are formed in the groove.
Embodiment two
The present invention also provides a kind of semiconductor devices made of method in embodiment one.
Due to preceding method have the effect of it is excellent, using preceding method production semiconductor devices have it is higher
Performance And Reliability.
The semiconductor devices can be PMOS device, NMOS device or FINFET device etc., and above-mentioned part category is only
It illustratively, can also be other using the semiconductor devices of method production in embodiment one, therefore not to repeat here.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, multiple dummy gate structures are formed on the surface of the semiconductor substrate, in the dummy grid
Matcoveredn is formed on the top surface of structure；
It is formed on the surface of the protective layer, the surrounded surface of dummy gate structure exposure and semiconductor substrate exposure
Masking layer；
Deposition forms sacrificial layer and covers the semiconductor substrate, wherein the top surface of the sacrificial layer is lower than covering on the protective layer
Cover the top surface of layer；
Ion implanting is carried out to the masking layer of exposure on the protective layer, so that the injection ion in the masking layer of exposure increases
More, in etching process later, etchant can be reacted with injection ion, consumption of the opposite reduction to the masking layer
Amount, to enhance the ability that the masking layer resists etching；
Remove the sacrificial layer and the part masking layer on the semiconductor substrate surface；
The semiconductor substrate is etched, to form groove in the semiconductor substrate of the two sides of the dummy gate structure；
Stressor layers are formed in the groove.
2. manufacturing method according to claim 1, which is characterized in that the dummy gate structure includes grid from bottom to top
Dielectric layer and gate material layers.
3. manufacturing method according to claim 1, which is characterized in that the injection ion of the ion implanting is selected from C or Si
One or more of.
4. manufacturing method according to claim 1, which is characterized in that removed after the ion implanting step described sacrificial
Before domestic animal layer, further include the steps that being made annealing treatment.
5. manufacturing method according to claim 1, which is characterized in that the technique for forming the sacrificial layer includes following step
It is rapid:
Deposition forms sacrificial material layer on the semiconductor substrate, and the top surface of the sacrificial material layer is made to be higher than the protective layer
On masking layer top surface；
Sacrificial material layer described in etch-back, to form sacrificial layer.
6. manufacturing method according to claim 1, which is characterized in that the material of the sacrificial layer is polysilicon or oxidation
Object.
7. manufacturing method according to claim 1, which is characterized in that after removing the sacrificial layer step, etch shape
Further include the steps that before at the groove using semiconductor substrate surface described in ozone treatment.
8. manufacturing method according to claim 1, which is characterized in that the material of the protective layer is silica, nitrogen oxidation
Silicon or silica/silicon nitride stack, the material of the masking layer are silicon nitride or silicon oxynitride.
9. manufacturing method according to claim 1, which is characterized in that the material of the stressor layers be selected from SiN, SiGe and
SiC any of them or combinations thereof.
10. a kind of semiconductor devices made of method as claimed in one of claims 1 to 9.
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| CN113130312B (en) * | 2020-01-16 | 2023-04-28 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
| CN111799158B (en) * | 2020-07-17 | 2022-09-09 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of one-time programmable device |
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