CN105097457A - Formation method of semiconductor device - Google Patents
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- CN105097457A CN105097457A CN201410184449.8A CN201410184449A CN105097457A CN 105097457 A CN105097457 A CN 105097457A CN 201410184449 A CN201410184449 A CN 201410184449A CN 105097457 A CN105097457 A CN 105097457A
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Abstract
A formation method of a semiconductor device comprises the steps of providing a substrate, wherein a grid structure is formed on the surface of the substrate; etching to remove the partial thickness of substrate at the two sides of the grid structure to form grooves; carrying out the oxidation treatment on the surfaces of the grooves to form oxidation films, and repairing the crystal lattice damage on the surfaces of the grooves; removing the oxidation films to expose the surfaces of the grooves; adopting an epitaxy process to form the stress layers filling the grooves. According to the present invention, before the stress layers are formed, the oxidation treatment is carried out on the surfaces of the grooves, the materials having the crystal lattice damage on the surfaces of the grooves are transformed into the oxidation film materials, and then the oxidation films are removed, so that the exposed crystal lattices on the surfaces of the grooves are high in quality, and accordingly, the stress layers of high quality and few defects are conducive to being formed, the stress actions of the stress layers in a channel region are larger, and a driving current of the formed semiconductor device is improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly a kind of formation method of semiconductor device.
Background technology
Along with the development of semiconductor technology, carrier mobility strengthens technology and obtains investigation and application widely, and the carrier mobility improving channel region can increase the drive current of MOS device, improves the performance of device.
In existing semiconductor device fabrication process, because stress can change energy gap and the carrier mobility of silicon materials, the performance therefore improving semiconductor device by stress becomes more and more conventional means.Particularly, by suitable proof stress, charge carrier (electronics in nmos device, the hole in PMOS device) mobility can be improved, and then improve drive current, greatly improve the performance of semiconductor device with this.
At present, adopt embedded germanium silicon (EmbeddedSiGe) or/and embedded carbon silicon (EmbeddedSiC) technology, namely the formation source region of PMOS area and the region in drain region is being needed first to form germanium silicon material, and then carry out source region and the drain region that doping forms PMOS device, first form carbon silicon materials in the region in the source region of NMOS area and drain region, and then carry out source region and drain region that doping forms nmos device.Forming described germanium silicon material is to introduce the compression that between silicon and germanium silicon (SiGe), lattice mismatch is formed, to improve the performance of PMOS device.Forming described carbon silicon materials is to introduce the tension stress that between silicon and carbon silicon (SiC), lattice mismatch is formed, to improve the performance of nmos device.
Embedded germanium silicon and embedded carbon silicon technology be applied in the carrier mobility that can improve semiconductor device to a certain extent, but find in actual applications, the drive current of semiconductor device improves limitation.
Summary of the invention
The problem that the present invention solves is that the stressor layers how avoiding causing extension to be formed due to substrate inner fluted surface lattice damage is of poor quality, improves the quality of the stressor layers formed, thus the drive current of raising semiconductor device.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising: provide substrate, described substrate surface is formed with grid structure; The substrate that etching removes described grid structure two side portions thickness forms groove; Oxidation processes is carried out to described groove surfaces and forms oxide-film, repair the lattice damage of groove surfaces; Remove described oxide-film, expose groove surfaces; Epitaxy technique is adopted to form the stressor layers of filling full described groove.
Optionally, the treatment temperature of described oxidation processes is lower than 500 degree.
Optionally, adopt the deionized water solution containing ozone to carry out oxidation processes to groove surfaces, and the treatment temperature of described oxidation processes is 10 degree to 100 degree.
Optionally, in described deionized water solution, the concentration of ozone is 10 milligrams every milliliter to 100 milligrams every milliliter.
Optionally, using plasma oxygen bombardment groove surfaces carries out oxidation processes, and the treatment temperature of oxidation processes is 150 degree to 450 degree.
Optionally, the technological parameter of described plasma oxygen bombardment groove surfaces is: in reaction chamber, pass into O
2, and O
2flow is 10sccm to 300sccm, and reaction chamber pressure is 1 millitorr to 50 millitorr, and source power is 300 watts to 2000 watts, and bias power is 100 watts to 800 watts.
Optionally, the material of described oxide-film is silica.
Optionally, the thickness of described oxide-film is 10 dust to 100 dusts.
Optionally, also step is comprised: in the substrate of grid structure both sides, form light doping section.
Optionally, after oxidation processes, carry out prerinse process to described groove surfaces, described oxide-film is removed in described prerinse process.
Optionally, adopt wet-etching technology to carry out described prerinse process, the etch liquids of wet etching is hydrofluoric acid solution.
Optionally, before oxidation processes, prerinse process is carried out to described groove surfaces.
Optionally, adopt wet-etching technology etching to remove described oxide-film, the etch liquids of wet etching is hydrofluoric acid solution.
Optionally, selective epitaxial process is adopted to form described stressor layers.
Optionally, the material of described stressor layers is SiGe, SiGeB, SiC or SiCP, and wherein, when the material of described stressor layers is SiGe or SiGeB, in the material of stressor layers, Ge atomic percent is 10% to 55%; When the material of described stressor layers is SiC or SiCP, in the material of stressor layers, C atomic percent is 0.5% to 10%.
Optionally, when the material of described stressor layers is SiGeB, the technological parameter of selective epitaxial process is: reacting gas comprises silicon source gas, germanium source gas, boron source gas, HCl and H
2, silicon source gas is SiH
4, SiH
2cl
2or Si
2h
6, germanium source gas is GeH
4, boron source gas is B
2h
6, wherein, silicon source gas flow is 5sccm to 500sccm, and germanium source gas flow is 5sccm to 500sccm, and boron source gas flow is 5sccm to 500sccm, HCl gas flow is 1sccm to 300sccm, H
2flow is 1000sccm to 50000sccm, and reaction chamber pressure is that 0.05 holder to 50 is held in the palm, and chamber temp is 400 degree to 900 degree.
Optionally, when the material of described stressor layers is SiC, the technological parameter of selective epitaxial process is: reacting gas comprises silicon source gas and carbon-source gas, and silicon source gas is SiH
4or SiH
2cl
2, carbon-source gas is C
2h
4, C
3h
8or C
2h
6reacting gas also comprises HCl and H2, wherein, silicon source gas flow is 5sccm to 500sccm, carbon-source gas flow is 5sccm to 500sccm, HCl gas flow be 1sccm to 500sccm, H2 gas flow is 1000sccm to 50000sccm, reaction chamber temperature is 450 degree to 600 degree, and reaction chamber pressure is that 1 holder to 500 is held in the palm.
Optionally, also comprise step: re-oxidation process is carried out to described grid structure, form oxide layer on grid structure surface and substrate surface.
Optionally, described re-oxidation process is furnace process, and the technological parameter of furnace process is: reacting gas comprises O
2, O
2flow is 100sccm to 15000sccm, and reaction chamber temperature is 500 degree to 800 degree.
Optionally, the semiconductor device of formation is nmos pass transistor, PMOS transistor or CMOS transistor.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the embodiment of the present invention, remove the substrate formation groove of grid structure two side portions thickness in etching after, owing to usually containing charged particle or group in etching technics, described charged particle or group bombardment substrate are to form groove, therefore groove surfaces also receives the bombardment of charged particle or group, the lattice of the material of groove surfaces material under the bombardment of charged particle or group sustains damage, and therefore groove surfaces has lattice defect, such as point defect or dislocation; Carry out oxidation processes to groove surfaces, material converting groove surfaces with lattice defect is oxide-film, and after removing described oxide-film, the groove surfaces material lattice quality come out is high; Owing to having the characteristic along the growth of groove surfaces material lattice bearing of trend when epitaxy technique forms stressor layers, the lattice quality of embodiment of the present invention further groove surfacing is high, therefore the defect in the stressor layers formed is few, the stressor layers formed is made also to have higher quality, the effect of stress that stressor layers applies to semiconductor device channel district is comparatively large, thus the effective drive current improving semiconductor device.
Further, due to before oxidation processes, in usual semiconductor device, there is doped region, the ion concentration distribution of described doped region has comparatively strict restriction, such as, for alleviate hot carrier effect of semiconductor device and formed in substrate light doping section, for improving the threshold voltage adjustments district that threshold voltage of semiconductor device is formed in channel region, if the temperature of oxidation processes is too high, ion concentration then in described doped region there will be the problem distributed again, causes the electric property of semiconductor device to change; And in the embodiment of the present invention, the treatment temperature of oxidation processes is lower than 500 degree, lower than in the oxidation processes of 500 degree, the ion concentration distribution of doped region changes hardly, therefore, while formation has the groove surfaces of higher lattice quality, can prevent other electric properties of semiconductor device from changing.
Further, in the embodiment of the present invention, adopt the deionized water solution containing ozone to carry out oxidation processes to groove surfaces, and the treatment temperature of described oxidation processes is 10 degree to 100 degree; Because the oxidizability of ozone is stronger, therefore, it is possible to reduce the processing time of oxidation processes, prevent the long harmful effect brought of oxidation treatment time, and, because the oxidizability of ozone is stronger, make the treatment temperature of oxidation processes very low, thus prevent the harmful effect that brings because oxidation temperature is too high further, improve the electric property of the semiconductor device formed.
Further, in the embodiment of the present invention, also comprise step: carry out re-oxidation process to grid structure, described re-oxidation process can repair the damage in grid structure, keeps the integrality of grid structure, thus improves the electric property of semiconductor device further.
Accompanying drawing explanation
The schematic flow sheet of the method for forming semiconductor devices that Fig. 1 provides for an embodiment;
The cross-sectional view of the semiconductor device forming process that Fig. 2 to Figure 15 provides for another embodiment of the present invention.
Embodiment
From background technology, the limitation that in prior art, semiconductor device drive current improves.
Formation process for semiconductor device is studied, and finds that the formation process of semiconductor device comprises the steps, please refer to Fig. 1: step S1, provide Semiconductor substrate, and described Semiconductor substrate comprises first area and second area; Step S2, form first grid structure at described first area semiconductor substrate surface, form second grid structure at described second area semiconductor substrate surface, and described first grid structure, second grid structure both sides have offset side wall; The mask layer of step S3, formation covering Semiconductor substrate, first grid structure and second grid structure; Step S4, graphical described mask layer, with patterned mask layer for mask, etch the Semiconductor substrate adjacent with first grid structure and form groove; Step S5, employing selective epitaxial process form the stressor layers of filling full described groove; Remove described mask layer.
Said method is formed in the technical process of semiconductor device, general employing dry etch process etch semiconductor substrates forms groove, the etching gas of dry etch process has high-octane charged particle or charged group, described charged particle or charged group bombardment groove surfaces, impurity or lattice defect, such as point defect or dislocation etc. is formed in groove surfaces; When the lattice defect of described groove surfaces or impurity more time, defect in the stressor layers causing epitaxial growth to be formed is more, even form polycrystalline state or amorphous stressor layers, cause epitaxial growth failure, stressor layers is caused to improve the limited in one's ability of the carrier mobility of semiconductor device, the limitation of the drive current raising of semiconductor device.
Forming process for semiconductor device studies discovery further, before formation stressor layers, prerinse process is carried out to groove, the impurity of groove surfaces can be removed to a certain extent, reduce the content of groove surfaces impurity, but, described prerinse process is difficult to the lattice defect repairing groove surfaces, when the groove surfaces with lattice defect adopts selective epitaxial process to form stressor layers, still can existing defects in the stressor layers formed, even cause the stressor layers formed to be amorphous state or polycrystalline state, the quality of stressor layers still has much room for improvement.
For this reason, the invention provides a kind of formation method of semiconductor device, provide substrate, described substrate surface is formed with grid structure; Etching removes the substrate of described grid structure two side portions thickness, forms groove; Oxidation processes is carried out to described groove surfaces, forms oxide-film in groove surfaces, repair the lattice damage of groove surfaces; Remove described oxide-film and expose groove surfaces; Epitaxy technique is adopted to form the stressor layers of filling full described groove.The present invention is before formation stressor layers, remove the material that groove surfaces has lattice damage, improve the quality forming stressor layers, thus improve the stress intensity that stressor layers acts on channel region, and then improve the drive current of semiconductor device, optimize the electric property of semiconductor device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The cross-sectional view of the semiconductor device forming process that Fig. 2 to Figure 15 provides for the embodiment of the present invention.
The semiconductor device that the present invention is formed is nmos pass transistor, PMOS transistor or CMOS transistor, and the present embodiment does exemplary illustrated for the semiconductor device formed for CMOS transistor.
Please refer to Fig. 2, provide the substrate 200 comprising first area I and second area II, I substrate 200 surface, described first area is formed with first grid structure, and described second area II substrate 200 surface is formed with second grid structure.
Described substrate 200 is Si substrate, Ge substrate, SiGe substrate or GaAs substrate; Described substrate 200 surface can also form some epitaxial interface layers or strained layer to improve the electric property of semiconductor device.
In the present embodiment, described substrate 200 is Si substrate.
Described first area I is NMOS area or PMOS area, described second area II is NMOS area or PMOS area, the present embodiment for first area I be PMOS area, second area does exemplary illustrated for NMOS area, the position of described first area I and second area II can exchange.
In the present embodiment, in described substrate 200, also there is isolation structure 201, prevent electricity between first area I and second area II from connecting.The packing material of described isolation structure 201 can be one or more in silica, silicon nitride or silicon oxynitride.
Ion implantation can also be carried out to described substrate 200, in substrate 200, form doped well region or threshold voltage adjustments district.
First grid structure and second grid structure are replacement gate structure, metal gate structure or polysilicon gate construction.
First grid structure comprises: be positioned at the first grid oxide layer 211 on I substrate 200 surface, first area, be positioned at the first grid electrode layer 212 on first grid oxide layer 211 surface and be positioned at the first grid masking layer 213 on first grid electrode layer 212 surface; Second grid structure comprises: be positioned at the second gate oxide layer 221 on second area II substrate 200 surface, be positioned at the second gate electrode layer 222 on second gate oxide layer 221 surface and be positioned at the second gate masking layer 223 on second gate electrode layer 222 surface.
The material of described first grid oxide layer 211 and second gate oxide layer 221 is SiO
2or high K medium material, described high K medium material is HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO
2, Al
2o
3one or more.
Described first grid electrode layer 212 and second gate electrode layer 222 can be single layer structure or sandwich construction, and the material of described first grid electrode layer 212 and second gate electrode layer 222 is one or more in polysilicon, TiN, TaN, WAl, W, Al or Cu.
The material of described first grid masking layer 213 and second gate masking layer 223 is silicon nitride.Described first grid masking layer 213 plays the effect of protection first grid electrode layer 212; described second gate masking layer 223 plays the effect of protection second gate electrode layer 222, prevents follow-up etching technics from causing damage to first grid electrode layer 212 and second gate electrode layer 222.
In the present embodiment, the material of described first grid oxide layer 211 and second gate oxide layer 221 is silica, and the material of described first grid electrode layer 212 and second gate electrode layer 222 is polysilicon.
Please continue to refer to Fig. 2, (Re-Oxidation) technique is reoxidized to described first grid structure and second grid structure, forms oxide layer 202 on first grid body structure surface, second grid body structure surface, first area I substrate 200 surface and second area II substrate 200 surface.
Owing to comprising dry etch process in the formation process of first grid structure and second grid structure, described dry etch process easily causes damage to first grid structure and second grid structure, causes having defect in first grid structure and second grid structure; And in the present embodiment, re-oxidation process is carried out to described first grid structure and second grid structure, the damage that first grid structure and second grid structure are subject to can be repaired, repair the defect in first grid structure and second grid structure, improve the integrality of first grid structure and second grid structure, thus improve electric property and the reliability of semiconductor device.
The material of described oxide layer 202 is silica.In the present embodiment, described re-oxidation process is furnace process, and the technological parameter of described furnace process is: reacting gas comprises O
2, O
2flow is 1000sccm to 15000sccm, and reaction chamber temperature is 500 degree to 800 degree.
After formation oxide layer 202, can also step be comprised: the first ion implantation is carried out to the substrate 200 of first grid structure both sides, in first grid structure both sides substrate 200, form the first light doping section (not shown); Second ion implantation is carried out to the substrate 200 of second grid structure both sides, in second grid structure both sides substrate 200, forms the second light doping section (not shown).Described first light doping section and the second light dope have the effect of alleviation hot carrier's effect (HCE:HotCarrierEffect).
In other embodiments of the present invention, after formation oxide layer, side wall can also be formed in first grid structure side wall and second grid structure side wall.Concrete, the processing step forming side wall comprises: form side wall film at oxide layer surface and first grid masking layer and second gate masking layer surface; Return the described side wall film of etching, form the side wall of adjacent first grid structure side wall place's oxide layer and second grid structure side wall place oxide layer.
Please refer to Fig. 3, form the first mask layer 204 being covered in oxide layer 202 surface of first area I and second area II.
In the present embodiment, the first mask layer 204 is also covered in sidewall and the top of first grid masking layer 213 and second gate masking layer 223.
Described first mask layer 204 is single layer structure or laminated construction, when described first mask layer 204 is laminated construction, can improve the etching selection ratio of subsequent etching processes.The material of the first mask layer 204 is silicon nitride, silica or silicon oxynitride.
The present embodiment does exemplary illustrated for the first mask layer 204 for single layer structure, and the material of described first mask layer 202 is silicon nitride.
If the thickness of the first mask layer 204 is too small, follow-uply easily over etching is caused to substrate 200; If the thickness of the first mask layer 204 is excessive, then subsequent etching first mask layer 204 can be caused to expose overlong time needed for I substrate 200 surface, first area, be unfavorable for improving semiconductor production efficiency; Therefore, in the present embodiment, the thickness of the first mask layer 204 is 100 dust to 500 dusts.
In other embodiments, when re-oxidation process not being carried out to first grid structure and second grid structure, then form the first mask layer being covered in described first area and second area substrate surface, first grid body structure surface and second grid body structure surface.
Please refer to Fig. 4, form the first photoresist layer 205 being covered in second area II first mask layer 204 surface.
Acting as of described first photoresist layer 205: in follow-up etching technics, the substrate 200 of protection second area II and second grid structure, prevent second area II substrate 200 and second grid structure from sustaining damage.
As an embodiment, the forming step of described first photoresist layer 205 comprises: form initial lithographic glue-line on first mask layer 204 surface of first area I and second area II; Carry out exposure imaging technique to described initial lithographic glue-line, remove the initial lithographic glue-line being positioned at first area I, form patterned first photoresist layer 205, described first photoresist layer 205 is positioned at first mask layer 204 surface of second area II.
Please refer to Fig. 5, with described first photoresist layer 205 for mask, etching removes the first mask layer 204 being positioned at first grid structure both sides, exposes substrate 200 surface of first grid structure both sides.
Before formation first mask layer 204, oxide layer 202 is defined in the present embodiment, therefore, after etching removal is positioned at the first mask layer 204 of first grid structure both sides, also comprise step: etching removes the oxide layer 202 being positioned at first grid structure both sides, expose substrate 200 surface of first grid structure both sides.
Adopt described first mask layer of anisotropic etch process etching, as an embodiment, the etching gas that described anisotropic etch process adopts is CF
4and He.
Due to anisotropic etch process to the etch rate perpendicular to substrate 200 surface direction much larger than the etch rate being parallel to substrate 200 surface direction, therefore, after exposing substrate 200 surface of first grid structure both sides, the first grid masking layer 213 of segment thickness is etched removal, the thickness of first grid masking layer 213 reduces, and first area I also has the first mask layer 203 of adjacent first grid structure both sides.
Please refer to Fig. 6, with the first mask layer 204 of adjacent first grid structure side wall for mask, the substrate 200 of etching first grid structure two side portions thickness forms the first groove 206.
In etching process, second area II is covered by the first photoresist layer 205 (please refer to Fig. 6), prevents second area II substrate 200 to be etched.
The shape of described first groove 206 is: square, U-shaped or sigma (Σ) shape.The present embodiment is squarely do exemplary illustrated with the shape of the first groove 206 formed, and the technique of the substrate 200 of etching first grid structure two side portions thickness is anisotropic etch process.
As an embodiment, described anisotropic etching is reactive ion etching, and the technological parameter of described reactive ion etching process is: reacting gas comprises CF
4, SF
6and Ar, CF
4flow is 50sccm to 100sccm, SF
6flow is 10sccm to 100sccm, Ar flow is 100sccm to 300sccm, and source power is 50 watts to 1000 watts, and bias power is 50 watts to 250 watts, and chamber pressure is 50 millitorr to 200 millitorrs, and chamber temp is 20 degree to 90 degree.
In other embodiments, the etching gas that reactive ion etching process adopts is HBr, SF
6and He.
Because anisotropic etch process has perpendicular to the large feature of substrate 200 surface direction etch rate, after the first groove 206 is formed, the first grid masking layer 213 of segment thickness is etched removal, and the first mask layer 204 being positioned at first grid structure side wall is retained.
After the first groove 206 is formed, also comprise step: remove described first photoresist layer 205.As an embodiment, adopt cineration technics to remove described first photoresist layer 205, the technological parameter of described cineration technics is: podzolic gas is O
2, O
2flow is 100sccm to 250sccm, and ashing temperature is 150 degree to 300 degree.
Please refer to Fig. 7, the first oxidation processes 207 is carried out to described first groove 206, form the first oxide-film 217 on described first groove 206 surface, repair the lattice damage on the first groove 206 surface.
The effect of the first oxidation processes 207 is: because the technique forming the first groove 206 is dry etching, containing high-octane charged particle or group in the etching gas of dry etching, described charged particle or group bombardment substrate 200 surface, thus the substrate 200 that etching removes segment thickness forms the first groove 206, under charged particle or group bombardment, first groove 206 surface there will be lattice damage, and the material on the first groove 206 surface has lattice defect, such as point defect or dislocation; During due to follow-up formation the first stressor layers, first stressor layers has the characteristic along the first groove 206 surfacing lattice bearing of trend growth, if epitaxial growth first stressor layers is carried out on follow-up the first groove 206 surface having lattice defect, then can cause the of poor quality of the first stressor layers formed, defect can be produced in first stressor layers, the the first stressor layers material even causing formation is polycrystalline state or amorphous material, affects the raising of semiconductor device drive current.And in the present embodiment, after first oxidation processes 207 is carried out to the first groove 206, the material oxidation with lattice defect is formed the first oxide-film 217, after follow-up removal first oxide-film 217, the material lattice on the first groove 206 surface exposed was not subject to damage, thus repaired the lattice damage on the first groove 206 surface, therefore, the quality of the first stressor layers that the first groove 206 surface after removal first oxide-film 217 is formed is improved, the stress that first stressor layers applies to semiconductor device channel district improves, thus the drive current of semiconductor device is improved.
And, due to before carrying out the first oxidation processes 207, experienced by one or many ion implantation in semiconductor device and form doped region, the CONCENTRATION DISTRIBUTION of described doped region has strict restriction, such as, the first light doping section in first area I substrate 200, the second light doping section in second area II substrate 200, Doped ions CONCENTRATION DISTRIBUTION in substrate 200 in the threshold voltage adjustments district of channel region or doped region well region is strict restriction, if the temperature of the first oxidation processes 207 is too high, ion concentration in described doped region then can be caused to occur the problem distributed again, ion concentration distribution off-design standard in semiconductor device, the electric property of the semiconductor device that impact is formed.
For this reason, in the embodiment of the present invention, the treatment temperature of described first oxidation processes 207 is lower than 500 degree, when treatment temperature is lower than 500 degree, the impact that ion concentration distribution in semiconductor device is subject to is very little, therefore, while guaranteeing the damage of reparation first groove 206 lattice surface, unnecessary damage semiconductor device being caused to other can be avoided.
Because ozone has stronger oxidizability, namely oxidizability under normal temperature condition can meet the object of oxidation first groove 206 surfacing, when therefore adopting the deionized water solution containing ozone to carry out the first oxidation processes 207, the treatment temperature of described oxidation processes is very low, effectively can avoid the problem that ion concentration in semiconductor device distributes again.
In the present embodiment, adopt the deionized water solution containing ozone to carry out the first oxidation processes 207 to the first groove 206 surface, and the treatment temperature of described oxidation processes is 10 degree to 100 degree.As a specific embodiment, in described deionized water solution, the concentration of ozone is that 10 milligrams every milliliter (ppm) is to 100 milligrams every milliliter (ppm).
In an alternative embodiment of the invention, using plasma oxygen bombards the first groove 206 surface and carries out the first oxidation processes 207, and the temperature of oxidation processes is 150 degree to 450 degree.As a specific embodiment, the technological parameter that described plasma oxygen bombards the first groove 206 surface is: in reaction chamber, pass through O
2, and O
2flow is 10sccm to 300sccm, and reaction chamber pressure is 1 millitorr to 50 millitorr, and source power is 300 watts to 2000 watts, and bias power is 100 watts to 800 watts.
After the first oxidation processes 207 completes, first groove 206 surface has material oxidized formation first oxide-film 217 of lattice damage, because the material of substrate 200 is silicon in the present embodiment, then the material of described first oxide-film 217 is silica, and the thickness of described first oxide-film 217 is 10 dust to 100 dusts.
Please refer to Fig. 8, the first prerinse process 208 is carried out to described first groove 206, in the first prerinse process 208 process, remove described first oxide-film 217 (please refer to Fig. 7), expose the first groove 206 surface.
The object of described first prerinse process 208 is: on the one hand, after the first groove 206 is formed, dry etch process can produce etch residue on the first groove 206 surface, the etch residue on the first groove 206 surface affects the quality of follow-up formation first stressor layers, the surface of the first groove 206 is cleaner, the quality of the first stressor layers formed is better, therefore, before formation first stressor layers, first prerinse process 208 is carried out to the first groove 206, removes the etch residue be positioned at sidewall bottom the first groove 206; On the other hand, the first oxide-film 217 is removed in described first prerinse process 208, expose the first groove 206 surface, and the lattice quality on the first groove 206 surface exposed is high.
In the present embodiment, adopt wet-etching technology to carry out described first prerinse process 208, the etch liquids of wet etching is hydrofluoric acid solution.Adopt wet-etching technology to carry out described first prerinse process 208, can prevent from forming new lattice damage, such as point defect or dislocation on the first groove 206 surface.
As a specific embodiment, in described hydrofluoric acid solution, the volume ratio of hydrofluoric acid and deionized water is 1:100 to 1:700.
It should be noted that, in other embodiments of the present invention, first prerinse process was carried out before the first oxidation processes, the etch residue remaining in the first groove surfaces is removed in first prerinse process, the material that the first groove surfaces lattice preventing the existence due to etch residue from may cause sustains damage is not oxidized, therefore before the first oxidation processes, carry out the first prerinse process, that the lattice damage of the first groove surfaces can be repaired is more thorough; Follow-up after the first oxidation processes, adopt wet-etching technology etching removal first oxide-film, the etch liquids of wet etching is hydrofluoric acid solution, after removing the first oxide-film, the lattice damage of the first groove surfaces is less, therefore, it is possible to remove the defect of the first groove surfaces further, improve the quality of follow-up formation first stressor layers further.
Please refer to Fig. 9, form first stressor layers 209 of filling full first groove 206 (please refer to Fig. 8).
The present embodiment to flush with substrate 200 surface with the top of described first stressor layers 209 and does exemplary illustrated.In other embodiments of the present invention, in order to apply suitable effect of stress to channel region, first area, the top of described first stressor layers also can higher than substrate surface.
The material of described first stressor layers 209 is SiGe, SiGeB, SiC or SiCP.Wherein, when first area I is NMOS area, the material of described first stressor layers 208 is SiC or SiCP, and the channel region that described first stressor layers 209 is NMOS area provides action of pulling stress, thus improves NMOS area carrier mobility; When first area I is PMOS area, the material of described first stressor layers 209 is SiGe or SiGeB, and the channel region that described first stressor layers 209 is PMOS area provides action of compressive stress.
The present embodiment is with first area I for presenting a demonstration property of PMOS area illustrates, the material of described first stressor layers 209 is SiGe or SiGeB; When the material of described first stressor layers 208 is SiGe or SiGeB, in SiGe or SiGeB, the mass percent of Ge is 10% to 50%; When the material of described first stressor layers 209 is SiGeB, in SiGeB, B atomic concentration is 1E18atom/cm
3to 3E20atom/cm
3.
Selective epitaxial process is adopted to form described first stressor layers 209.
In the present embodiment, the material of described first stressor layers 209 is SiGeB, adopt the selective epitaxial process of original position autodoping (in-situ) to form described first stressor layers 209, the technological parameter of selective epitaxial process is: reacting gas comprises silicon source gas, germanium source gas, boron source gas, HCl and H
2, silicon source gas is SiH
4, SiH
2cl
2or Si
2h
6, germanium source gas is GeH
4, boron source gas is B
2h
6, wherein, silicon source gas flow is 5sccm to 500sccm, and germanium source gas flow is 5sccm to 500sccm, and boron source gas flow is 5sccm to 500sccm, HCl gas flow is 1sccm to 300sccm, H
2flow is 1000sccm to 50000sccm, and reaction chamber pressure is that 0.05 holder to 50 is held in the palm, and chamber temp is 400 degree to 900 degree.
Because the present embodiment is before formation first stressor layers 209, eliminate the material that the first groove 206 surface has lattice damage, repair the lattice damage on the first groove 206 surface, make the lattice quality on the first groove 206 surface high, therefore, described lattice quality high first groove 206 surface formed the first stressor layers 209 function admirable and compactness is good, the defect of the first stressor layers 209 formed is few, thus ensure that the first stressor layers 209 applies enough compression to channel region, and then improve the drive current of semiconductor device.
Please refer to Figure 10, remove described first mask layer 204 (please refer to Fig. 9).
Wet-etching technology etching is adopted to remove described first mask layer 204.
As an embodiment, the etch liquids of described wet-etching technology is phosphoric acid solution, and wherein solution temperature is 120 degree to 200 degree, and the mass percent of phosphoric acid is 65% to 85%.
Please refer to Figure 11, form the second mask layer 231 being covered in first area I and second area II oxide layer 202 surface and the first stressor layers 209 surface; Form the second photoresist layer (not shown) being covered in mask layer 231 surface, first area second; With described second photoresist layer for mask, etching removes the second mask layer 231 being positioned at second grid structure both sides, exposes the substrate surface of second grid structure both sides; With the second mask layer 231 of adjacent second grid structure side wall for mask, the substrate 200 of etching second grid structure two side portions thickness forms the second groove 232; Remove described second photoresist layer.
The material of described second mask layer 231 and the second groove 232 and forming step with reference to the material of the first mask layer 204 (please refer to Fig. 3) and the first groove 206 (please refer to Fig. 6) and forming step, can not repeat them here.
Please refer to Figure 12, the second oxidation processes 233 is carried out to described second groove 232, form the second oxide-film 227 on described second groove 232 surface, repair the lattice damage on the second groove 232 surface.
The effect of described second oxidation processes 233 and technique with reference to the effect of the first oxidation processes 207 (please refer to Fig. 7) and technique, can not repeat them here.
After the second oxidation processes 233 completes, the second groove 232 surface has material oxidized formation second oxide-film 227 of lattice damage, and the material of described second oxide-film 227 is silica, and the thickness of the second oxide-film 227 is 10 dust to 100 dusts.
Please refer to Figure 13, the second prerinse process 234 is entered to described second groove 232, remove described second oxide-film 227 (please refer to Figure 12) and expose the second groove 232 surface.
The effect of described second prerinse process 234 and technique with reference to the effect of the first prerinse process 208 (please refer to Fig. 8) and technique, can not repeat them here.
After the second prerinse process 234, remove the second oxide-film 227, make the lattice quality of the second groove 232 surfacing come out excellent, and the etch residue that the technique that described second prerinse process 234 can remove formation second groove 232 causes, makes the second groove 232 have clean surface.
Please refer to Figure 14, adopt selective epitaxial process to form second stressor layers 235 of filling full described second groove 232 (please refer to Figure 13).
In the present embodiment, for second area II for NMOS area does exemplary illustrated, the material of described second stressor layers 235 is SiC or SiCP.
Selective epitaxial process is adopted to form described second stressor layers 235.When the material of described second stressor layers 235 is SiC or SiCP, the mass percent 1% to 10% of C in SiC or SiCP; When the material of described second stressor layers 235 is SiCP, P atomic concentration is 1E15atom/cm
3to 5E18atom/cm
3.
As an embodiment, the technological parameter of described selective epitaxial process is: reacting gas comprises silicon source gas and carbon-source gas, and silicon source gas is SiH
4or SiH
2cl
2, carbon-source gas is C
2h
4, C
3h
8or C
2h
6, reacting gas also comprises HCl and H2, and wherein, silicon source gas flow is 5sccm to 500sccm, and carbon-source gas flow is 5sccm to 500sccm, HCl gas flow is 1sccm to 500sccm, H
2gas flow is 1000sccm to 50000sccm, and reaction chamber temperature is 450 degree to 600 degree, and reaction chamber pressure is that 1 holder to 500 is held in the palm.
Because the present embodiment is before formation second stressor layers 235, eliminate the material that the second groove 232 surface has lattice damage, make the lattice quality of the second groove 232 surfacing high, therefore, the defect of the second stressor layers 235 formed on described second groove 232 surface is few, the tension stress making the second stressor layers 235 act on channel region strengthens, thus improves the drive current of semiconductor device, optimizes the electric property of semiconductor device.
Please refer to Figure 15, remove described second mask layer 231 (please refer to Figure 14).
Wet-etching technology etching is adopted to remove described second mask layer 231.As a specific embodiment, the etch liquids of described wet-etching technology is phosphoric acid solution, and wherein, the percentage of phosphoric acid is 65% to 85%, and solution temperature is 120 degree to 200 degree.
Follow-up processing step also comprises: in the substrate 200 of first area I and second area II, form heavily doped region respectively.
To sum up, the technical scheme of the formation method of semiconductor device provided by the invention has the following advantages:
First, the present invention is after the substrate of etching grid structure division thickness forms groove, oxidation processes is carried out to groove surfaces and forms oxide-film, material converting groove surfaces with lattice damage is oxide-film material, described oxide-film is follow-up to be easily removed, thus repair the lattice damage of groove surfaces, make the groove surfaces lattice quality that comes out high; Owing to having the characteristic along the growth of groove surfaces material lattice bearing of trend when epitaxy technique forms stressor layers, the lattice quality of embodiment of the present invention further groove surfacing is high, therefore the defect in the stressor layers formed is few, the stressor layers formed is made also to have higher quality, the effect of stress that stressor layers applies to semiconductor device channel district is comparatively large, thus the effective drive current improving semiconductor device.
Secondly, due to before oxidation processes, in usual semiconductor device, there is doped region, the ion concentration distribution of described doped region has comparatively strict restriction, such as, for alleviating the light doping section that hot carrier effect of semiconductor device is formed in substrate, for improving the threshold voltage adjustments district that threshold voltage of semiconductor device is formed in channel region, in the embodiment of the present invention, the treatment temperature of oxidation processes is lower than 500 degree, lower than in the oxidation processes of 500 degree, the ion concentration distribution of doped region changes hardly, therefore, while formation has the groove surfaces of higher lattice quality, can prevent other electric properties of semiconductor device from changing.If the problem of oxidation processes is too high, then the ion concentration in described doped region there will be the problem distributed again, causes the electric property of semiconductor device to change;
Again, adopt the deionized water solution containing ozone to carry out oxidation processes to groove surfaces, and the treatment temperature of described oxidation processes is 10 degree to 100 degree; Because the oxidizability of ozone is stronger, therefore, it is possible to reduce the processing time of oxidation processes, prevent the long harmful effect brought of oxidation treatment time, and, because the oxidizability of ozone is stronger, make the treatment temperature of oxidation processes very low, thus prevent the harmful effect that brings because oxidation temperature is too high further, improve the electric property of the semiconductor device formed.
Further, adopt wet-etching technology etching to remove described oxide-film, avoid removing oxide film process and cause groove surfaces to occur new lattice damage.
Finally, also comprise step: carry out re-oxidation process to grid structure, described re-oxidation process can repair the damage in grid structure, keeps the integrality of grid structure, thus improves the electric property of semiconductor device further.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided substrate, described substrate surface is formed with grid structure;
The substrate that etching removes described grid structure two side portions thickness forms groove;
Oxidation processes is carried out to described groove surfaces and forms oxide-film, repair the lattice damage of groove surfaces;
Remove described oxide-film, expose groove surfaces;
Epitaxy technique is adopted to form the stressor layers of filling full described groove.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the treatment temperature of described oxidation processes is lower than 500 degree.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, adopt the deionized water solution containing ozone to carry out oxidation processes to groove surfaces, and the treatment temperature of described oxidation processes is 10 degree to 100 degree.
4. the formation method of semiconductor device as claimed in claim 3, it is characterized in that, in described deionized water solution, the concentration of ozone is 10 milligrams every milliliter to 100 milligrams every milliliter.
5. the formation method of semiconductor device as claimed in claim 2, is characterized in that, using plasma oxygen bombardment groove surfaces carries out oxidation processes, and the treatment temperature of oxidation processes is 150 degree to 450 degree.
6. the formation method of semiconductor device as claimed in claim 5, is characterized in that, the technological parameter of described plasma oxygen bombardment groove surfaces is: in reaction chamber, pass into O
2, and O
2flow is 10sccm to 300sccm, and reaction chamber pressure is 1 millitorr to 50 millitorr, and source power is 300 watts to 2000 watts, and bias power is 100 watts to 800 watts.
7. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described oxide-film is silica.
8. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness of described oxide-film is 10 dust to 100 dusts.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, also comprise step: in the substrate of grid structure both sides, form light doping section.
10. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, after oxidation processes, carry out prerinse process to described groove surfaces, described oxide-film is removed in described prerinse process.
The formation method of 11. semiconductor device as claimed in claim 10, is characterized in that, adopt wet-etching technology to carry out described prerinse process, the etch liquids of wet etching is hydrofluoric acid solution.
The formation method of 12. semiconductor device as claimed in claim 1, is characterized in that, before oxidation processes, carry out prerinse process to described groove surfaces.
The formation method of 13. semiconductor device as claimed in claim 1, is characterized in that, adopt wet-etching technology etching to remove described oxide-film, the etch liquids of wet etching is hydrofluoric acid solution.
The formation method of 14. semiconductor device as claimed in claim 1, is characterized in that, adopts selective epitaxial process to form described stressor layers.
The formation method of 15. semiconductor device as claimed in claim 14, it is characterized in that, the material of described stressor layers is SiGe, SiGeB, SiC or SiCP, wherein, when the material of described stressor layers is SiGe or SiGeB, in the material of stressor layers, Ge atomic percent is 10% to 55%; When the material of described stressor layers is SiC or SiCP, in the material of stressor layers, C atomic percent is 0.5% to 10%.
The formation method of 16. semiconductor device as claimed in claim 15, it is characterized in that, when the material of described stressor layers is SiGeB, the technological parameter of selective epitaxial process is: reacting gas comprises silicon source gas, germanium source gas, boron source gas, HCl and H
2, silicon source gas is SiH
4, SiH
2cl
2or Si
2h
6, germanium source gas is GeH
4, boron source gas is B
2h
6, wherein, silicon source gas flow is 5sccm to 500sccm, and germanium source gas flow is 5sccm to 500sccm, and boron source gas flow is 5sccm to 500sccm, HCl gas flow is 1sccm to 300sccm, H
2flow is 1000sccm to 50000sccm, and reaction chamber pressure is that 0.05 holder to 50 is held in the palm, and chamber temp is 400 degree to 900 degree.
The formation method of 17. semiconductor device as claimed in claim 15, it is characterized in that, when the material of described stressor layers is SiC, the technological parameter of selective epitaxial process is: reacting gas comprises silicon source gas and carbon-source gas, and silicon source gas is SiH
4or SiH
2cl
2, carbon-source gas is C
2h
4, C
3h
8or C
2h
6reacting gas also comprises HCl and H2, wherein, silicon source gas flow is 5sccm to 500sccm, carbon-source gas flow is 5sccm to 500sccm, HCl gas flow be 1sccm to 500sccm, H2 gas flow is 1000sccm to 50000sccm, reaction chamber temperature is 450 degree to 600 degree, and reaction chamber pressure is that 1 holder to 500 is held in the palm.
The formation method of 18. semiconductor device as claimed in claim 1, is characterized in that, also comprise step: carry out re-oxidation process to described grid structure, forms oxide layer on grid structure surface and substrate surface.
The formation method of 19. semiconductor device as claimed in claim 18, it is characterized in that, described re-oxidation process is furnace process, and the technological parameter of furnace process is: reacting gas comprises O
2, O
2flow is 100sccm to 15000sccm, and reaction chamber temperature is 500 degree to 800 degree.
The formation method of 20. semiconductor device as claimed in claim 1, it is characterized in that, the semiconductor device of formation is nmos pass transistor, PMOS transistor or CMOS transistor.
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