CN102800700B - Transistor and forming method thereof - Google Patents
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- CN102800700B CN102800700B CN201110139441.6A CN201110139441A CN102800700B CN 102800700 B CN102800700 B CN 102800700B CN 201110139441 A CN201110139441 A CN 201110139441A CN 102800700 B CN102800700 B CN 102800700B
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Abstract
The embodiment of the invention provides a transistor comprising a semiconductor substrate, a grid electrode structure located on the surface of the semiconductor substrate, and ditch grooves located in the semiconductor substrates on the two sides of the grid electrode structure, wherein the ditch grooves comprise a first ditch groove located on the two sides of the grid electrode structure and in contact with the grid electrode structure, a second ditch groove located on the bottom part of the first ditch groove and in contact with the first ditch groove, and a third ditch groove located on the bottom part of the second ditch groove and in contact with the second ditch groove, and the second ditch groove protrudes towards one side of the grid electrode structure; and stress layers located in the ditch grooves. The stress of the ditch region of the transistor provided by the embodiment of the invention is increased, the migration rate of charge carriers is improved, and the performance of the transistor is reinforced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of transistor and forming method thereof.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach higher arithmetic speed, larger memory data output and more function, semiconductor device is towards higher component density, higher integrated level future development, therefore, the grid of complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) transistor becomes more and more thinner and length becomes shorter than ever.In order to obtain good electric property, usually need to improve performance of semiconductor device by controlling carrier mobility.A key element of this technology controls the stress in transistor channel.Such as suitable proof stress, improves charge carrier (electronics in n-channel transistor, the hole in p-channel transistor) mobility, just can improve drive current.Thus stress greatly can improve the performance of transistor.
Stress liner technology forms tensile stress laying (tensile stress liner) on the nmos transistors, form compression laying (compressive stress liner) on the pmos transistors, thus increase the drive current of PMOS transistor and nmos pass transistor, improve the response speed of circuit.According to the study, use the integrated circuit of two stress liner technology that the speed of 24% can be brought to promote.
Because silicon, germanium have identical lattice structure, i.e. " diamond " structure, at room temperature, the lattice constant of germanium is greater than the lattice constant of silicon, so in the source of PMOS transistor, drain region formed SiGe (SiGe), the compression that between silicon and germanium silicon, lattice mismatch is formed can be introduced, improve compression further, improve the performance of PMOS transistor.Correspondingly, in the source of nmos pass transistor, drain region forms carbon silicon (CSi) and can introduce the tension stress that lattice mismatch between silicon and carbon silicon formed, and improves tension stress further, improves the performance of nmos pass transistor.
In prior art, the formation method of transistor is:
Please refer to Fig. 1, Semiconductor substrate 100 is provided, shallow channel isolation area 103 is formed in described Semiconductor substrate 100, formation is positioned at the surperficial gate insulation layer 105 of described Semiconductor substrate 100, formed and cover the gate electrode layer 107 of described gate insulation layer 105, formed on described Semiconductor substrate 100 surface and be positioned at described gate insulation layer 105, gate electrode layer 107 both sides and the side wall 109 be in contact with it;
Please refer to Fig. 2, is that mask forms opening 111 in described Semiconductor substrate 100 with described side wall 109;
Please refer to Fig. 3, in described opening 111, fill full SiGe, form source/drain region 113.
Then prior art is limited at the stress of the method formation of the source and drain areas formation germanium silicon of transistor, and the raising of the mobility of charge carrier is less, and the performance of transistor improves limited.
Manyly see that publication number is the application documents of " CN101789447A " about transistor and forming method thereof.
Summary of the invention
The problem that the present invention solves is transistor of the mobility improving charge carrier and forming method thereof.
For solving the problem, The embodiment provides a kind of transistor, comprising:
Semiconductor substrate;
Be positioned at the grid structure of described semiconductor substrate surface;
Be positioned at the groove of the described Semiconductor substrate of described grid structure both sides, described groove comprise be positioned at described grid structure both sides and the first groove contacted with described grid structure, be positioned at described first groove bottom and with the second groove of the first trench contact, be positioned at described second channel bottom and with the 3rd groove of described second trench contact, wherein, described second groove is outstanding to the side of described grid structure;
Be positioned at the stressor layers of described groove.
Alternatively, described second groove is to the outstanding 10nm ~ 40nm in side of described grid structure, and the degree of depth of described 3rd groove is 30nm ~ 100nm.
Alternatively, the material of described strained layer is SiGe, and described SiGe comprises the germanium atom of 20% ~ 35%.
Alternatively, the crystal orientation of described Semiconductor substrate is <110> or <100>.
Alternatively, described grid structure comprises the gate dielectric layer being positioned at described semiconductor substrate surface, the gate electrode layer being positioned at described gate dielectric layer surface, and is positioned at the side wall of semiconductor substrate surface of described gate dielectric layer and gate electrode layer both sides.
Additionally provide a kind of formation method of transistor in embodiments of the invention, comprising:
Semiconductor substrate is provided;
Formation is positioned at described semiconductor substrate surface grid structure;
Form the groove being positioned at the described Semiconductor substrate of described grid structure both sides, described groove comprise be positioned at described grid structure both sides and the first groove contacted with described grid structure, be positioned at described first groove bottom and with the second groove of the first trench contact, be positioned at described second channel bottom and with the 3rd groove of described second trench contact, wherein, described second groove is outstanding to the side of described grid structure;
Form the stressor layers being positioned at described groove.
Alternatively, the forming step of described groove is: form the hard mask layer covering described Semiconductor substrate and grid structure, described hard mask layer has the opening being positioned at grid structure both sides; With described hard mask layer for Semiconductor substrate described in mask etching forms the first groove; Etch the Semiconductor substrate of the first channel bottom and the side near described grid structure, form the second groove; The Semiconductor substrate etching described second channel bottom forms the 3rd groove.
Alternatively, the formation process of described first groove and the 3rd groove is dry etching; The formation process of described second groove is wet etching.
Alternatively, the forming step of described stressor layers is: adopt epitaxial growth technology in groove, form the monocrystalline silicon thin film that thickness is 3nm ~ 10nm; In the atmosphere of germanium atom comprising 20% ~ 35%, epitaxial growth technology is adopted to form germanium-silicon film on monocrystalline silicon thin film surface; Be under the process conditions of 800 DEG C ~ 1100 DEG C in temperature, employing is cured or rapid thermal anneal process heats 10s ~ 30min to described germanium-silicon film, forms the stressor layers flushed with described semiconductor substrate surface.
Alternatively, the forming step of described stressor layers is: adopt depositing operation in described groove, form the polysilicon membrane that thickness is 3nm ~ 10nm; Depositing operation is adopted to form on described polysilicon membrane surface the stressor layers flushed with described semiconductor substrate surface.
Compared with prior art, the present invention has the following advantages:
The transistor of the embodiment of the present invention, groove is formed in the Semiconductor substrate of described grid structure both sides, described groove comprise the bottom that is positioned at described first groove and with the second groove of the first trench contact, described second groove is outstanding to the side of described grid structure, the stress of transistor increases, and can improve the mobility of charge carrier; The groove of the embodiment of the present invention also comprise be positioned at the second channel bottom and with the 3rd groove of described second trench contact, the degree of depth of described groove increases, the stressor layers of follow-up formation increases, further increase the stress of transistor, the mobility of the channel region charge carrier of transistor is improved further, strengthens the performance of transistor.
Accompanying drawing explanation
Fig. 1 ~ Fig. 3 is the process schematic of the cross-section structure of the formation method of the transistor of prior art;
Fig. 4 is the schematic flow sheet of the formation method of the transistor of the embodiment of the present invention;
Fig. 5 ~ Fig. 9 is the process schematic of the cross-section structure of the formation method of the transistor of the embodiment of the present invention.
Embodiment
From background technology, the formation method of existing transistor in source, drain region forms mobility comparatively limited that SiGe improves charge carrier, cause the drive current of transistor less, thus make the poor-performing of transistor.
The inventor of the embodiment of the present invention finds, the formation method of the transistor of prior art, adopts the method for dry etching to form groove in grid structure both sides, in described groove, then fill the method existing problems that silicon germanium material forms stressor layers.The inventor of the embodiment of the present invention finds after further research, stress intensity in transistor channel and the shape of groove closely related, when described groove is outstanding to grid structure side, described slot trough reduces from the length of channel region, the stressor layers formed in such cases, comparatively large to the stress in transistor channel, be conducive to the mobility improving charge carrier.Further, the inventor of the embodiment of the present invention finds, the degree of depth of groove is also relevant with the stress intensity in transistor channel, can increase the degree of depth of groove to improve the stress in transistor channel, thus improves the mobility of charge carrier.
In order to make those skilled in the art better understand the present invention, below in conjunction with accompanying drawing and specific embodiment, the present invention is described in detail.
It should be noted that; Transistor forming method provided by the present invention both may be used for forming PMOS transistor; also may be used for forming nmos pass transistor; forming PMOS transistor and formed in the technique of nmos pass transistor; difference is that the material of stressor layers is different, and the material of the protective layer formed by oxidation technology is also different.In the present embodiment, exemplarily to form PMOS transistor, the present invention is set forth.
A kind of formation method inventor providing transistor of the embodiment of the present invention, please refer to Fig. 4, comprising:
Step S201, provides Semiconductor substrate;
Step S203, is formed and is positioned at described semiconductor substrate surface grid structure;
Step S205, form the groove being positioned at the described Semiconductor substrate of described grid structure both sides, described groove comprise the first groove contacted with described grid structure, the bottom being positioned at described first groove and with the second groove of the first trench contact, be positioned at described second channel bottom and with the 3rd groove of described second trench contact, wherein, described second groove is outstanding to the side of described grid structure;
Step S207, forms the stressor layers being positioned at described groove.
Perform step S201, please refer to Fig. 5, Semiconductor substrate 300 is provided.
The material of described Semiconductor substrate 300 is monocrystalline silicon, is formed with fleet plough groove isolation structure 303, for isolated transistor in described Semiconductor substrate 300.
In an embodiment of the present invention, the crystal orientation of described Semiconductor substrate 300 is <110> or <100>.
It should be noted that, in other embodiments of the invention, described Semiconductor substrate 300 also can be other crystal orientation, such as <101>, <001>, <010> etc.
Perform step S203, please continue to refer to Fig. 5, formed and be positioned at described Semiconductor substrate 300 surface gate structure (sign).
Described grid structure comprises the gate dielectric layer 305 being positioned at Semiconductor substrate 300 surface, the gate electrode layer 307 being positioned at described gate dielectric layer 305 surface and is positioned at described gate dielectric layer 305 and gate electrode layer 307 both sides and the side wall 309 on Semiconductor substrate 300 surface be in contact with it.
In an embodiment of the present invention, the forming step of described grid structure is: adopt depositing operation to form gate dielectric layer 305 on described Semiconductor substrate 300 surface; Depositing operation is adopted to form gate electrode layer 307 on described gate dielectric layer 305 surface; Deposition, etching technics is adopted to form side wall on Semiconductor substrate 300 surface of described gate dielectric layer 305 and gate electrode layer 307 both sides.
Wherein, the material of described gate dielectric layer is silicon dioxide, and the material of described gate electrode layer is polysilicon or metal, and the material of described side wall is silicon dioxide.
Perform step S205, please refer to Fig. 6 ~ Fig. 8, form the groove being positioned at the described Semiconductor substrate of described grid structure both sides, described groove comprise be positioned at described grid structure both sides and the first groove 311 contacted with described grid structure, be positioned at described first groove 311 bottom and the second groove 312 contacted with the first groove 311, be positioned at the 3rd groove 313 contacted bottom described second groove 312 and with described second groove 312, wherein, described second groove 312 is outstanding to the side of described grid structure.
Please refer to Fig. 6, formed and be positioned at described grid structure both sides and the first groove 311 contacted with described grid structure.
The forming step of described first groove 311 is: formed and cover described Semiconductor substrate 300, the top of grid structure and the hard mask layer (not shown) of both sides, described hard mask layer has the opening (not shown) being positioned at grid structure both sides; With described hard mask layer for Semiconductor substrate described in mask etching 300 forms the first groove 311.
In an embodiment of the present invention, the formation process of described first groove 311 is dry etching, the dark 30 ~ 60nm of described first groove 311.
Please refer to Fig. 7, form the bottom and the second groove 312 contacted with the first groove 311 that are positioned at described first groove 311, described second groove 312 is outstanding to the side of described grid structure.
For making the channel region of the stressor layers of follow-up formation to transistor, there is larger stress, can consider to make described second groove 312 outstanding to the side of described grid structure, described slot trough is reduced from the length of channel region, make the channel region of stressor layers to transistor have larger stress, thus improve the mobility of the charge carrier of transistor.
If consider too many outstanding to grid structure side of the second groove 312, then the second groove 312 of described grid structure both sides can be caused at a distance of too near, and the length of short channel is too little causes electric leakage; If too little outstanding to grid structure side of the second groove 312, then it is limited that the stress of the transistor of follow-up formation increases, and is difficult to the mobility improving charge carrier.Described second groove 312 is to the outstanding 10nm ~ 40nm in grid structure side, and especially within the scope of 16nm ~ 26nm, the stress of the transistor of follow-up formation is maximum, and the mobility of charge carrier is the highest.
The inventor of the embodiment of the present invention finds after research, adopt anisotropic dry etch process, the described Semiconductor substrate 300 of etching is continued in the bottom of described first groove 311, form the second groove 312 comparatively difficult, adopt isotropic wet-etching technology can well solve the problem forming second groove 312 outstanding to the side of described grid structure.In an embodiment of the present invention, take crystal orientation as the Semiconductor substrate 300 of <110> or <100> be example, the formation process of described second groove 312 is wet etching, chemical reagent in described wet etching corrodes described Semiconductor substrate 300 along crystal orientation <110> or <100> of monocrystalline silicon, namely along the crystal orientation <110> of monocrystalline silicon or <100> corrosion rate fast, then corrosion rate is slower to be different from other directions of crystal orientation <110> or <100> of described monocrystalline silicon.Therefore, the second groove 312 adopting wet-etching technology to be formed is outstanding to grid structure side.
Please refer to Fig. 8, formed and be positioned at the 3rd groove 313 contacted bottom described second groove 312 and with described second groove 312.
Consider that the stress of the side outstanding transistor increase only making the second groove 312 to grid structure is limited, the inventor of the embodiment of the present invention finds after research, increase the degree of depth of groove, make follow-up can fill more SiGes formed strained layer, thus make the stress of transistor larger, increase the mobility of charge carrier, improve transistor performance.Therefore, after formation second groove 312, continue the Semiconductor substrate 300 bottom etching second trenches 312, form the 3rd groove 313.
In an embodiment of the present invention, the formation process of described 3rd groove 313 is dry etching, and the degree of depth of described 3rd groove is 30nm ~ 100nm.
After above-mentioned steps completes, completing of groove, described groove is used for follow-up filling SiGe and forms stressor layers.
Perform step S207, please refer to Fig. 9, form the stressor layers 315 being positioned at described groove.
The material of described stressor layers 315 is SiGe, for making the stress of transistor channel region increase, improving the mobility of charge carrier, strengthening the performance of transistor.
In an embodiment of the present invention, the forming step of described stressor layers 315 is: adopt epitaxial growth technology in described groove, form the monocrystalline silicon thin film that thickness is 3nm ~ 10nm, the stress distribution being provided for the transistor channel region of follow-up formation is more even; In the atmosphere of germanium atom comprising 20% ~ 35%, epitaxial growth technology is adopted to form germanium-silicon film on monocrystalline silicon thin film surface; Be under the process conditions of 800 DEG C ~ 1100 DEG C in temperature, employing is cured or rapid thermal anneal process heats 10s ~ 30min to described germanium-silicon film, forms the stressor layers 315 flushed with described semiconductor substrate surface.
In another embodiment of the invention, the forming step of described stressor layers 315 is: adopt depositing operation in described groove, form the polysilicon membrane that thickness is 3nm ~ 10nm, the stress distribution being provided for the transistor channel region of follow-up formation is more even; Depositing operation is adopted to form on described polysilicon membrane surface the stressor layers 315 flushed with described semiconductor substrate surface.
It should be noted that, in PMOS transistor, can also doped with boron in described strained layer 315, or in nmos pass transistor Doping Phosphorus, for reducing the resistance of transistor.
Accordingly, the inventor of the embodiment of the present invention additionally provides a kind of transistor, incorporated by reference to reference to figure 8 and Fig. 9, comprising:
Semiconductor substrate 300;
Be positioned at the grid structure on described Semiconductor substrate 300 surface;
Be positioned at the groove of the described Semiconductor substrate 300 of described grid structure both sides, described groove comprise be positioned at described grid structure both sides and the first groove 311 contacted with described grid structure, be positioned at described first groove 311 bottom and the second groove 312 contacted with the first groove 311, be positioned at the 3rd groove 313 contacted bottom described second groove 312 and with described second groove 312, wherein, described second groove 312 is outstanding to the side of described grid structure;
Be positioned at the stressor layers 315 of described groove.
Wherein, the crystal orientation of described Semiconductor substrate 300 is <110> or <100>; Described grid structure comprises the gate dielectric layer 305 being positioned at described semiconductor substrate surface, the gate electrode layer 307 being positioned at described gate dielectric layer 305 surface, and is positioned at the side wall 309 on Semiconductor substrate 300 surface of described gate dielectric layer 305 and gate electrode layer 307 both sides; Described second groove 312 is to the outstanding 10nm ~ 40nm in side of described grid structure, and the degree of depth of described 3rd groove 313 is 30nm ~ 100nm; The material of described strained layer 315 is SiGe, and described SiGe comprises the germanium atom of 20% ~ 35%.
To sum up, the transistor of the embodiment of the present invention, groove is formed in the Semiconductor substrate of described grid structure both sides, described groove comprise the bottom that is positioned at described first groove and with the second groove of the first trench contact, described second groove is outstanding to the side of described grid structure, the stress of transistor increases, and can improve the mobility of charge carrier; The groove of the embodiment of the present invention also comprise be positioned at the second channel bottom and with the 3rd groove of described second trench contact, the degree of depth of described groove increases, the stressor layers of follow-up formation increases, further increase the stress of transistor, the mobility of the channel region charge carrier of transistor is improved further, strengthens the performance of transistor.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a transistor, comprising:
Semiconductor substrate;
Be positioned at the grid structure of described semiconductor substrate surface;
It is characterized in that, also comprise:
Be positioned at the groove of the described Semiconductor substrate of described grid structure both sides, described groove comprise be positioned at described grid structure both sides and the first groove contacted with described grid structure, be positioned at described first groove bottom and with the second groove of the first trench contact, be positioned at described second channel bottom and with the 3rd groove of described second trench contact, wherein, described second groove relative to the first groove and the 3rd groove outstanding to the side of described grid structure;
Fill the stressor layers of described groove.
2. transistor as claimed in claim 1, it is characterized in that, described second groove is to the outstanding 10nm ~ 40nm in side of described grid structure, and the degree of depth of described 3rd groove is 30nm ~ 100nm.
3. transistor as claimed in claim 1, it is characterized in that, the material of described stressor layers is SiGe, and described SiGe comprises the germanium atom of 20% ~ 35%.
4. transistor as claimed in claim 1, it is characterized in that, the crystal orientation of described Semiconductor substrate is <110> or <100>.
5. transistor as claimed in claim 1, it is characterized in that, described grid structure comprises the gate dielectric layer being positioned at described semiconductor substrate surface, the gate electrode layer being positioned at described gate dielectric layer surface, and is positioned at the side wall of semiconductor substrate surface of described gate dielectric layer and gate electrode layer both sides.
6. a formation method for transistor, comprising:
Semiconductor substrate is provided;
Formation is positioned at described semiconductor substrate surface grid structure;
It is characterized in that, also comprise:
Form the groove being positioned at the described Semiconductor substrate of described grid structure both sides, described groove comprise be positioned at described grid structure both sides and the first groove contacted with described grid structure, be positioned at described first groove bottom and with the second groove of the first trench contact, be positioned at described second channel bottom and with the 3rd groove of described second trench contact, wherein, described second groove relative to the first groove and the 3rd groove outstanding to the side of described grid structure;
Form the stressor layers of filling described groove.
7. the formation method of transistor as claimed in claim 6, it is characterized in that, the forming step of described groove is: form the hard mask layer covering described Semiconductor substrate and grid structure, described hard mask layer has the opening being positioned at grid structure both sides; With described hard mask layer for Semiconductor substrate described in mask etching forms the first groove; Etch the Semiconductor substrate of the first channel bottom and the side near described grid structure, form the second groove; The Semiconductor substrate etching described second channel bottom forms the 3rd groove.
8. the formation method of transistor as claimed in claim 7, it is characterized in that, the formation process of described first groove and the 3rd groove is dry etching; The formation process of described second groove is wet etching.
9. the formation method of transistor as claimed in claim 6, it is characterized in that, the forming step of described stressor layers is: adopt epitaxial growth technology in described groove, form the monocrystalline silicon thin film that thickness is 3nm ~ 10nm; In the atmosphere of germanium atom comprising 20% ~ 35%, epitaxial growth technology is adopted to form germanium-silicon film on monocrystalline silicon thin film surface; Be under the process conditions of 800 DEG C ~ 1100 DEG C in temperature, employing is cured or rapid thermal anneal process heats 10s ~ 30min to described germanium-silicon film, forms the stressor layers flushed with described semiconductor substrate surface.
10. the formation method of transistor as claimed in claim 6, it is characterized in that, the forming step of described stressor layers is: adopt depositing operation in described groove, form the polysilicon membrane that thickness is 3nm ~ 10nm; Depositing operation is adopted to form on described polysilicon membrane surface the stressor layers flushed with described semiconductor substrate surface.
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| CN105990342B (en) * | 2015-02-13 | 2019-07-19 | 上海华力微电子有限公司 | Semiconductor devices and its manufacturing process with the forming cavity for being embedded in germanium material |
| CN113571413A (en) * | 2020-04-29 | 2021-10-29 | 芯恩（青岛）集成电路有限公司 | Trench gate structure and forming method |
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| CN1574226A (en) * | 2003-05-30 | 2005-02-02 | 国际商业机器公司 | Formation of silicon-germanium substrate material on insulator, substrate material, and heterostructure |
| CN1797783A (en) * | 2004-12-28 | 2006-07-05 | 富士通株式会社 | Semiconductor device and fabrication method thereof |
| CN101208786A (en) * | 2005-06-30 | 2008-06-25 | 英特尔公司 | Transistor with improved tip profile and method of manufacture thereof |
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| US7442618B2 (en) * | 2005-07-16 | 2008-10-28 | Chartered Semiconductor Manufacturing, Ltd | Method to engineer etch profiles in Si substrate for advanced semiconductor devices |
| US20070026599A1 (en) * | 2005-07-27 | 2007-02-01 | Advanced Micro Devices, Inc. | Methods for fabricating a stressed MOS device |
| US7964910B2 (en) * | 2007-10-17 | 2011-06-21 | International Business Machines Corporation | Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure |
| US7781799B2 (en) * | 2007-10-24 | 2010-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain strained layers |
| US7851313B1 (en) * | 2007-11-09 | 2010-12-14 | Xilinx, Inc. | Semiconductor device and process for improved etch control of strained silicon alloy trenches |
| US20090302348A1 (en) * | 2008-06-10 | 2009-12-10 | International Business Machines Corporation | Stress enhanced transistor devices and methods of making |
| US9054130B2 (en) * | 2009-08-27 | 2015-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bottle-neck recess in a semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574226A (en) * | 2003-05-30 | 2005-02-02 | 国际商业机器公司 | Formation of silicon-germanium substrate material on insulator, substrate material, and heterostructure |
| CN1797783A (en) * | 2004-12-28 | 2006-07-05 | 富士通株式会社 | Semiconductor device and fabrication method thereof |
| CN101208786A (en) * | 2005-06-30 | 2008-06-25 | 英特尔公司 | Transistor with improved tip profile and method of manufacture thereof |
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