KR20010063867A - A method for forming a self aligned contact of a semiconductor device - Google Patents
A method for forming a self aligned contact of a semiconductor device Download PDFInfo
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- KR20010063867A KR20010063867A KR1019990061971A KR19990061971A KR20010063867A KR 20010063867 A KR20010063867 A KR 20010063867A KR 1019990061971 A KR1019990061971 A KR 1019990061971A KR 19990061971 A KR19990061971 A KR 19990061971A KR 20010063867 A KR20010063867 A KR 20010063867A
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 61
- 238000005530 etching Methods 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 42
- 150000004767 nitrides Chemical class 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 자기정렬적인 콘택 형성방법에 관한 것으로, 특히 삼층감광막을 이용하여 콘택패드를 용이하게 형성하고 그에 따른 후속공정으로 콘택공정을 용이하게 실시할 수 있도록 하여 반도체소자의 생산성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for forming a self-aligned contact of a semiconductor device, and in particular, by using a three-layer photoresist film, the contact pad can be easily formed, and the contact process can be easily performed in a subsequent process, thereby improving the productivity of the semiconductor device. It is about technology that can be made.
일반적으로, 메모리 소자에서 중요한 특성인 리프레쉬 타임 ( refresh time ) 은 주로 저장전극 노드와 트랜지스터의 드레인을 연결하는 저장전극 콘택공정시 상기 드레인이 손상되어 발생되는 누설전류에 의하여 결정된다.In general, a refresh time, which is an important characteristic of a memory device, is mainly determined by a leakage current generated by damaging the drain during a storage electrode contact process connecting the storage electrode node and the drain of the transistor.
현재 사용되고 있는 노광기술로는 16 M DRAM 까지 콘택홀을 형성할 때 콘택홀 측벽의 도전층과 절연불량이 발생하지 않고 소자를 형성할 수 있으나, 소자가 고집적화됨에 따라 단위셀의 크기가 축소되고, 그에 따라서 콘택홀과 도전층의 간격이 좁아지게 된다.In the current exposure technology, when forming a contact hole up to 16 M DRAM, a device can be formed without a poor insulation with the conductive layer of the sidewall of the contact hole. However, as the device is highly integrated, the unit cell size is reduced. As a result, the gap between the contact hole and the conductive layer is narrowed.
상기와 같이 좁아진 콘택홀을 형성하기 위하여 콘택의 크기를 축소시켜야 하고, 이를 위하여 노광방식을 바꾸거나, 마스크를 바꾸어서 어느 정도는 해결할 수 있었다. 또한, 자기정렬적인 콘택 ( self-aligned contact, 이하에서 SAC 라 함 ) 으로 이를 해결하기도 하였다.In order to form a narrowed contact hole as described above, the size of the contact should be reduced, and for this purpose, it was solved to some extent by changing the exposure method or changing the mask. In addition, self-aligned contact (hereafter referred to as SAC) was solved.
한편, SAC 공정중 가장 각광받는 것으로 산화막 식각공정시 식각장벽으로 질화막을 사용하는 자기정렬적인 콘택 ( nitride barrier SAC, 이하에서 NBSAC 이라 함 ) 공정을 사용한다.On the other hand, the most popular among the SAC process is a self-aligned contact (nitride barrier SAC, hereinafter referred to as NBSAC) process using a nitride film as an etching barrier during the oxide film etching process.
그리고, 상기 NBSAC 공정은 크게 산화막 식각공정과 질화막 식각공정으로 대별된다.The NBSAC process is roughly classified into an oxide layer etching process and a nitride layer etching process.
이중에서 산화막 식각 공정은, 질화막에 대하여 높은 식각 선택비를 얻기 위하여 폴리머 유발 가스인 C3F8이나 C4F8가스를 다량 사용한다. 상기 C3F8이나 C4F8가스는 많은 폴리머를 유발하여 질화막에 대한 식각 선택비는 확보할 수 있으나 콘택홀 내에서 산화막이 완전히 제거되지 않는 식각 멈춘 문제가 발생한다.In the oxide film etching process, a large amount of C 3 F 8 or C 4 F 8 gas, which is a polymer induced gas, is used to obtain a high etching selectivity with respect to the nitride film. The C 3 F 8 or C 4 F 8 gas may induce a large number of polymers to secure an etching selectivity for the nitride film, but there is a problem that the etch stop is not completely removed in the contact hole.
여기서, 질화막에 대한 선택비와 식각 멈춤은, 서로 상반된 현상으로 프로세스 윈도우 ( process window ) 를 좁게 하고 재현성을 악화시키는 요인이 된다.Here, the selectivity and the etch stop with respect to the nitride film are opposite to each other, which causes the process window to be narrowed and the reproducibility deteriorates.
상기 플로세스 윈도우를 확장하기 위해서는 폴리머 발생이 적은 조건을 사용하며, 이 경우 질화막의 두께를 증가하여야 한다. 그러나, 질화막의 두께를 증가시킬 경우 콘택면적의 감소를 초래하기 때문에 이를 보완하기 위해서 질화막을 등방성 식각하여야 한다.In order to extend the flow window, a condition in which polymer is generated is used. In this case, the thickness of the nitride film must be increased. However, if the thickness of the nitride film is increased, the contact area is reduced, so that the nitride film should be isotropically etched to compensate for this.
이외에 질화막 식각은, 질화막 아래의 산화막이 전기적 절연막으로 사용되기 때문에 산화막의 손상이 가능한 적어야 하며, 산화막에 대하여 높은 식각 선택비 차이가 필요하며, 주변회로 지역에 산화막 식각시 반도체기판이 노출되는 부분이 있어 상기 반도체기판의 식각을 최소화하는 조건을 필요로 한다.In addition, since the oxide layer under the nitride layer is used as an electrical insulating layer, the nitride layer has to be as little as possible to damage the oxide layer. A high etching selectivity difference with respect to the oxide layer is required, and the portion where the semiconductor substrate is exposed when the oxide layer is etched in the peripheral circuit area is required. There is a need for a condition that minimizes the etching of the semiconductor substrate.
그러나, 기존의 질화막 식각 장비의 하나인 이온 인듀스드 식각장비 ( ion induced etcher ) 는 등방성 식각과 산화막에 대하여 높은 식각 선택비를 얻을 수 없다.However, ion induced etcher, which is one of the conventional nitride film etching equipments, cannot obtain high etching selectivity for isotropic etching and oxide film.
그리고, 최근에 각광을 받고 있는 래디칼 식각장비 ( radical etcher ) 는 NF3, CF4, SF6등의 가스를 사용하고 있어 등방성 식각과 산화막에 대하여 높은 식각 선택비를 확보할 수 있으나 반도체기판인 실리콘에 대하여 높은 식각 선택비 확보는 불가능하다.In addition, the radical etcher, which has recently been in the spotlight, uses gases such as NF 3 , CF 4 , SF 6, etc., so it is possible to secure a high etching selectivity for isotropic etching and oxide films, but silicon as a semiconductor substrate It is not possible to secure high etch selectivity.
왜냐하면, 식각에 가장 큰 영향을 미치는 요인은 에천트 ( etchants ) 이지만 NF3, CF4, SF6등과 같이 주 에천트가 불소 ( fluorine ) 계열인 경우에 있어서, 상기 래디칼 식각장비는, 산화막, 질화막, 실리콘 모두 식각이 가능하기 때문에 박막의 결합력이 식각 속도를 결정하게 된다. 즉, 결합력이 산화막 > 질화막 > 실리콘 순서일 경우, 실리콘의 식각이 가장 빠르게 진행되기 때문에 질화막 식각공정시 실리콘에 에 대하여 높은 식각 선택비는 확보는 불가능하다.Because the most influential factor for etching is etchant, but in the case where the main etchant is a fluorine series such as NF 3 , CF 4 , SF 6, etc., the radical etching equipment is an oxide film or a nitride film. Since both silicon and silicon can be etched, the bonding force of the thin film determines the etching rate. That is, when the bonding force is in the order of oxide film> nitride film> silicon, since the etching of silicon proceeds fastest, it is impossible to secure a high etching selectivity with respect to silicon during the nitride film etching process.
결과적으로, 종래기술에 따른 NBSAC 공정은 고 선택비 확보 측면에서 공정을 진행하기 어렵고, 선택비를 확보한다고 해도 공정 마진을 확보하기 어려워 실제 양산 공정에 적용하기 어려운 문제점이 있다.As a result, the NBSAC process according to the prior art has a problem that it is difficult to proceed the process in terms of securing high selectivity, and even if the selectivity is secured, it is difficult to secure the process margin and thus it is difficult to apply to the actual production process.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하층감광막, 중간층 및 상층감광막의 적층구조로 형성되는 삼층 감광막을 이용하여 용이하게 패드 폴리를 형성함으로써 용이하게 SAC 공정을 양산화시킬 수 있는 반도체소자의 자기정렬적인 콘택 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, a semiconductor device that can easily mass-produce SAC process by easily forming a pad poly using a three-layer photosensitive film formed of a laminated structure of a lower photosensitive film, an intermediate layer and an upper photosensitive film Its purpose is to provide a self-aligned contact method.
도 1a 내지 도 1c 는 본 발명의 실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 게이트전극용 도전층11: semiconductor substrate 13: conductive layer for gate electrode
15 : 마스크산화막 17 : 절연막 스페이서15 mask oxide film 17 insulating film spacer
19 : 하부감광막 21 : 중간층19: lower photosensitive film 21: intermediate layer
23 : 상부감광막패턴 25 : 콘택홀23: upper photoresist pattern 25: contact hole
27 : 콘택패드 29 : 층간절연막27: contact pad 29: interlayer insulating film
50 : 언더컷50: undercut
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은,Self-aligned contact forming method of a semiconductor device according to the present invention to achieve the above object,
반도체기판 상에 마스크산화막과 절연막 스페이서가 구비되는 게이트전극을 형성하는 공정과,Forming a gate electrode having a mask oxide film and an insulating film spacer on the semiconductor substrate;
전체표면상부를 평탄화시키는 하층감광막을 형성하는 공정과,Forming a lower photosensitive film for flattening the entire upper surface thereof;
상기 하층감광막 상부에 중간층과 상층감광막패턴을 형성하여 삼층감광막 구조를 형성하는 공정과,Forming an intermediate layer and an upper photoresist pattern on the lower photoresist to form a three-layer photoresist structure;
상기 상층감광막패턴을 마스크로하여 상기 중간층과 하층감광막을 식각하여 상기 반도체기판을 노출시키는 콘택홀을 형성하는 동시에 상기 중간층 하부로 언더컷을 형성하는 공정과,Forming a contact hole for exposing the semiconductor substrate by etching the intermediate layer and the lower layer photoresist using the upper photoresist pattern as a mask, and simultaneously forming an undercut under the intermediate layer;
상기 언더컷을 매립하는 콘택패드용 폴리실리콘을 전체표면상부에 형성하는 공정과,Forming a contact pad for embedding the undercut on the entire surface thereof;
상기 평탄화식각공정으로 상기 콘택패드용 폴리실리콘과 중간층을 식각하여 콘택패드를 형성하는 공정과,Forming a contact pad by etching the contact pad polysilicon and the intermediate layer by the planarization etching process;
상기 하층감광막을 제거하고 상기 콘택패드의 예정된 영역을 노출시키는 층간절연막을 형성하는 공정을 포함하는 것을 특징으로한다.And removing the lower photosensitive film and forming an interlayer insulating film exposing a predetermined area of the contact pad.
이하, 첨부된 도면을 참고로 하여 본 발명은 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c 는 본 발명의 실시예에 따른 반도체소자의 자기정렬적인 콘택 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming self-aligned contacts in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 게이트전극용 도전층(13)를 형성하고, 그 상부에 마스크산화막(15)을 형성한다.First, a conductive layer 13 for a gate electrode is formed on the semiconductor substrate 11, and a mask oxide film 15 is formed on the semiconductor substrate 11.
그리고, 게이트전극 마스크를 이용한 사진식각공정으로 상기 마스크산화막(15)과 상기 도전층(13)을 식각하여 상기 반도체기판(11)의 활성영역 상에 도전층(13)과 마스크산화막(15)의 적층된 패턴을 형성한다.The mask oxide film 15 and the conductive layer 13 are etched by a photolithography process using a gate electrode mask to etch the conductive layer 13 and the mask oxide film 15 on the active region of the semiconductor substrate 11. Form a stacked pattern.
그 다음, 상기 적층된 패턴 측벽에 절연막 스페이서(17)를 형성한다. 이때, 상기 절연막 스페이서(17)는 전체표면상부에 일정두께의 절연막을 증착하고 이를증착된 두께 만큼 이방성식각하여 형성한다.Next, an insulating film spacer 17 is formed on the stacked pattern sidewalls. At this time, the insulating film spacer 17 is formed by depositing an insulating film having a predetermined thickness on the entire surface and anisotropically etched by the deposited thickness.
그리고, 전체표면상부를 평탄화시키는 하층감광막(19)을 형성한다.Then, the lower photosensitive film 19 for flattening the entire upper surface portion is formed.
그리고, 상기 하층감광막(19)을 베이킹 ( baking ) 하되, 85∼95 ℃ 에서 55∼65 초, 190∼210 ℃ 55∼65 초, 300∼340 ℃에서 55∼65 초 동안 실시한다.Then, the lower photosensitive film 19 is baked, and is performed at 85 to 95 ° C. for 55 to 65 seconds, 190 to 210 ° C. for 55 to 65 seconds, and 300 to 340 ° C. for 55 to 65 seconds.
그리고, 상기 하층감광막(19) 상부에 중간층(21)을 형성한다.In addition, an intermediate layer 21 is formed on the lower photosensitive layer 19.
그리고, 상기 중간층(21) 상부에 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성된 상층감광막패턴(23)을 형성함으로써 삼층 감광막을 형성한다. (도 1a)In addition, a three-layer photoresist layer is formed by forming an upper photoresist layer pattern 23 formed by an exposure and development process using a contact mask (not shown) on the intermediate layer 21. (FIG. 1A)
그 다음, 상기 상층감광막패턴(23)을 마스크로하여 상기 중간층(21)과 하층감광막(19)을 등방성식각하여 상기 반도체기판(11)을 노출시키는 콘택홀(25)을 형성하는 동시에 상기 중간층(21)과 마스크산화막(15)의 사이로 언더컷(50)을 형성한다.Then, using the upper photoresist pattern 23 as a mask, the contact hole 25 exposing the semiconductor substrate 11 is formed by isotropically etching the intermediate layer 21 and the lower photoresist layer 19 and at the same time the intermediate layer ( An undercut 50 is formed between 21 and the mask oxide film 15.
이때, 상기 등방성식각공정은 산소와 질소가스를 이용한 플라즈마 식각공정으로 실시하되, 상기 오거닉 로우-케이(19)의 식각공정에서는 아르곤이나 헬륨과 같은 비활성가스를 이용하여 실시함으로써 플라즈마의 안정성을 향상시킬 수 있다.In this case, the isotropic etching process is performed by a plasma etching process using oxygen and nitrogen gas, but in the etching process of the organic low-K 19 using an inert gas such as argon or helium to improve the stability of the plasma You can.
여기서, 상기 등방성식각공정 대신 비등방성식각공정으로 조건을 조절하여 언더컷을 형성할 수도 있다.Here, the undercut may be formed by adjusting the conditions using the anisotropic etching process instead of the anisotropic etching process.
한편, 상기 상층감광막패턴(23)은 상기 하층감광막(19)의 플라즈마 식각공정시 제거되며, 남아 있는 경우 별도의 식각공정으로 제거할 수 있다. (도 1b)Meanwhile, the upper photoresist layer pattern 23 may be removed during the plasma etching process of the lower photoresist layer 19, and may be removed by a separate etching process. (FIG. 1B)
그 다음, 상기 제1콘택홀(25)을 매립하는 폴리실리콘을 전체표면상부에 형성하되, 상기 언더컷(50)을 완전히 매립할 수 있도록 형성한다.Next, a polysilicon filling the first contact hole 25 is formed on the entire surface, and the undercut 50 is completely embedded.
이때, 상기 폴리실리콘은 도핑이 용이하도록 인슈트 공정으로 실시할 수도 있다.In this case, the polysilicon may be carried out in an in-shute process to facilitate doping.
그 다음, 상기 하층감광막(19)이 노출될때까지 상기 폴리실리콘 및 중간층(21)을 평탄화식각하여 상기 제1콘택홀(25)보다 넓은 마진을 확보할 수 있는 콘택패드(27)를 형성한다.Next, the polysilicon and the intermediate layer 21 are planarized and etched until the lower photosensitive layer 19 is exposed to form a contact pad 27 that can secure a wider margin than the first contact hole 25.
이때, 상기 평탄화식각공정은 CMP 공정이나 에치백공정으로 실시한다.In this case, the planarization etching process is performed by a CMP process or an etch back process.
그 다음, 후속공정으로 전체표면상부에 평탄화된 층간절연막(29)을 형성하고 이를 콘택마스크(도시안됨)를 이용한 사진식각공정으로 식각하여 상기 콘택패드(27)를 노출시킨다.Subsequently, a planarized interlayer insulating film 29 is formed on the entire surface in a subsequent process, and the contact pad 27 is exposed by etching the same by a photolithography process using a contact mask (not shown).
여기서, 상기 층간절연막(29)의 식각공정시 유발되는 폴리머는 건식 플라즈마를 이용하여 제거한다. (도 1c)Here, the polymer caused during the etching process of the interlayer insulating film 29 is removed using a dry plasma. (FIG. 1C)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 자기정렬적인 콘택 형성방법은, 삼층감광막을 이용하여 중첩마진이 향상된 콘택패드를 형성하고 이를 이용하여 콘택공정을 용이하게 실시할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, in the self-aligned contact forming method of a semiconductor device according to the present invention, a contact pad having an improved overlap margin is formed by using a three-layer photosensitive film and the contact process can be easily performed using the same. Provides the effect of improving the characteristics and reliability.
Claims (6)
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