JPH09199589A - Wiring pattern formation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of a substrate contact and a on-field electrode contact by an identical layer even when a self align contact(SAC) structure is employed. SOLUTION: Prior to formation of an interlayer insulating film 12, an SiN etching stop film 8 is previously selectively removed on a field region side, whereby an offset oxide film 5f on an on-field electrode 4f can be removed together at the time of etching the interlayer insulating film 12. The selective removal of the SiN etching stop film 8 is carried out by flattening a plasma- tetraethoxysilane(p-TEOS) film 10 by chemical-mechanical polishing(CMP). Thereby a contact hole 14a reaching a silicon substrate 1 and a via hole 14f reaching the on-field electrode 4f can be made simultaneously, metal plugs are buried into the holes, and an upper wiring pattern layer is formed thereon, completing contacts with use of the same layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method applied to, for example, semiconductor device manufacturing, and particularly when a self-aligned contact (SAC) structure is adopted, a substrate contact and an on-wiring contact in an active region are formed. To achieve the same layer.

[0002]

2. Description of the Related Art In semiconductor device manufacturing, in the generation where the design rule still has sufficient margin for the limit of fine processing technology and the opening diameter of the connection hole is sufficiently smaller than the size of the contact formation region, contact formation is required. Was generally performed by the aligned contact method.

FIG. 39 shows an example of application of the aligned contact method. This figure shows a silicon substrate 101 (S
i) A field oxide film 102 (SiO ₂ ) is formed in a predetermined two-dimensional pattern on the first oxide film 102, and a first layer polysilicon film (polySi / WS) is formed in each of the active region and the field region defined by the field oxide film 102.
ix) to form an active region upper electrode 104a and a field upper electrode 104f.
A contact hole 108a is formed on the active region side and a via hole 108f is formed on the field region side in the SiOx interlayer insulating film 107 covering 4f, and the impurity diffusion layer 106 is formed.
This shows a state in which the contact to the substrate (substrate contact) and the contact to the field electrode 104f (contact on the wiring) are achieved in the same layer.

Here, the active region upper electrode 104a is M
The portion that functions as the gate electrode of the OS transistor is formed on the silicon substrate 101 via the gate oxide film 103 (SiO ₂ ). The side wall 105a (SiOx) formed on the side wall surface of the active region upper electrode 104a is for making the structure of the impurity diffusion layer 106 an LDD structure, and is formed on the side wall surface of the upper field electrode 104f. Side wall 10
5f (SiOx) is formed in association with the sidewall 105a. In addition, the contact hole 1
The 08a and the via hole 108f are first provided with tungsten plugs 109a and 109f through a Ti-based barrier metal.
(W) is buried respectively, and an upper wiring 110 (Al) made of an Al-based multilayer film having a three-layer structure of, for example, a Ti-based adhesion layer / Al-1% Si film / TiN antireflection film is formed thereon.

In the process of manufacturing such a device, Si
Although there is some technical difficulty in simultaneously forming a contact hole and a via hole having different aspect ratios in dry etching of the Ox interlayer insulating film 107, the etching process itself is single. Therefore, conventionally,
This difficulty has been overcome by developing an etching process that provides a sufficiently large selectivity for silicon-based materials, and thus simultaneous formation of substrate contacts and on-wire contacts has been a practical technique.

However, in the manufacturing process of a fine semiconductor device to which the design rule of 0.3 μm or later is applied, if the design margin of the connection hole is determined in consideration of the variation in the alignment with the lower layer wiring, the connection hole There is a problem that the design size (= hole diameter + design margin) becomes too large. This variation in alignment is caused by insufficient alignment performance of a reduction projection exposure apparatus used in photolithography. However, this variation is an item that is particularly difficult to scale down among the various scaling factors included in the semiconductor process,
It is even said that it is a factor that determines the limit of exposure technology beyond resolution. If the design size of the connection hole becomes large, the line width of the lower wiring cannot be reduced, which is a major obstacle to miniaturization and high density of the semiconductor device. On the other hand, if it is attempted to suppress the increase in design size by reducing the hole diameter, the depth of focus will be insufficient in the current exposure equipment, and holes will not be formed in the resist film.
The problem occurs that the pattern cannot be formed.

From such a background, a self-aligned contact (SAC) method which can eliminate a design margin for alignment on a photomask is attracting attention. There are various kinds of this method, but the method most often studied is the method using a nitride film (SiN) as an etching stop layer because the number of exposure steps does not increase. Here, an application example of the SAC method will be described with reference to FIGS. 40 to 42.

In FIG. 40, a field oxide film 202 (SiO ₂ ) is formed according to a predetermined two-dimensional pattern on a silicon substrate 201 (Si), and an active region and a field region defined by the field oxide film 202 are formed. First-layer polysilicon film (polySi / WSi)
x), an active region upper electrode 204a and a field upper electrode 204f are formed, the surface of the substrate is covered with the SiOx interlayer insulating film 210, and the resist pattern 21 is formed thereon.
1 shows the state of the wafer on which 1 (PR) is formed. Since the active region upper electrode 204a is a gate electrode of a MOS transistor, the gate oxide film 203 (Si
It is formed on the silicon substrate 201 via O ₂ ).

Looking at the structure on this wafer, FIG.
There is a large difference in the structure in the vicinity of the electrodes as compared with the conventional example shown in FIG. That is, in the SAC method, the electrodes 204a, 20
Offset SiOx on 4f with common pattern with these
The films 205a and 205f are formed, and the offset Si
SiOx sidewalls 205a and 205f are formed on the sidewall surfaces of the pattern including the Ox films 205a and 205f. In particular, the side wall 206a on the active region side is LD
It plays an important role not only as an ion implantation mask for forming the D structure, but also assuring a withstand voltage between the tungsten plug buried in the contact hole formed later and the active region upper electrode 204a. .
Further, in the SAC method, these sidewalls 205a,
The entire electrode pattern including 205f is covered with the thin SiN etching stop film 208.

Using the resist pattern as a mask, S
FIG. 41 shows a state in which the SiOx interlayer insulating film 210 is subjected to RIE (reactive ion etching) under the condition that a selection ratio with respect to iN can be secured. By this dry etching, a contact hole 212a is formed on the active region side and a via hole 212f is formed halfway on the field region side. The reason for halfway is that this etching temporarily stops at the surface of the SiN etching stop film 208. In the illustrated example, the resist pattern 2 is caused by the limit of the control performance of the overlay accuracy of the stepper.
11 has a slight misalignment (toward the left in the figure), and a contact hole 212a that partially overlaps with the edge of the active region upper electrode 204a is formed. However, the presence of the SiN etching stop film 208 prevents the offset SiOx film 205a and the sidewalls 206a from being eroded. This prevention of erosion is the biggest reason for applying the SAC method.

However, since the contact cannot be completed as it is, next, as shown in FIG. 42, the contact hole 212a and the via hole 21 are formed.
RIE is performed to selectively remove the SiN etching stop film 208 exposed inside 2f.

[0012]

However, even if the SiN etching stop film 208 is selectively removed as described above, it is clear from FIG. 42 that the contact holes can be formed in the contact holes. 212a
Only. Regarding the via hole 212f facing the field upper electrode 204f, the electrode surface is still offset Si.
Since it is covered with the Ox film 205f, it is not in a state where contacts can be formed.

Therefore, as shown in FIG. 43, the contact hole 212a and the via hole 212f are filled with tungsten plugs 213a and 213f (W), respectively, and further, the upper wiring 21 made of an Al-based multilayer film is formed.
Even if 4 (Al) is formed, the substrate contact can be made, but the contact on the wiring cannot be made.

Therefore, in order to selectively remove the offset SiOx film 205f on the surface of the on-field electrode 204f, it is conceivable to carry out RIE under the condition that a sufficient selection ratio with respect to the silicon-based material can be secured. However, according to this method, it is preferable that the resist pattern 211 is not misaligned, but if it is generated as in this example, as shown in FIG. 44, an offset occurs at the bottom of the contact hole 212a. SiOx film 205a and S
The iOx sidewall 206a is eroded.
Therefore, in this state, the tungsten plug 213
When the a and 213f are embedded and the upper layer wiring 214 is formed, a breakdown voltage occurs inside the contact hole 212a instead of achieving the on-wiring contact through the via hole 212f. In the worst case, as shown in FIG. 45, the active region upper electrode 204a exposed in the contact hole 212a and the tungsten plug 213a are short-circuited.

As described above, even if the conventional method of forming a contact by the aligned contact method is directly applied to the contact formation by the SAC method, it is extremely difficult to achieve the substrate contact and the on-wiring contact in the same layer. . Therefore, an object of the present invention is to solve this problem and to provide a wiring forming method capable of achieving both contacts in the same layer even in the SAC method.

[0016]

The above-mentioned conventional problems are as follows.
This is because the SiN film is formed on the surface of the field upper electrode as well as the surface of the active region upper electrode. The present invention aims to achieve the above-mentioned object by providing an independent process for selectively removing the SiN film on the surface of the field electrode. Here, the SiN film on the surface of the field electrode in the present invention is not limited to the etching stop film described above, and may be an offset insulating film.

The concept of the wiring forming method of the present invention is roughly classified into two methods, that is, the SiN film on the surface of the field electrode is removed by a self-aligning method or is removed by patterning through photolithography. That is, the number of times required for photolithography is the same as that of the conventional method in the former way of thinking, and one more in the latter way of thinking.

The following method (I) is proposed as a method for removing the SiN etching stop film on the surface of the field electrode by a self-aligning method.

(I) The formation of the offset insulating film and the side wall of the SiOx film and the formation of the SiN etching stop film are carried out in the same manner as in the conventional method, and the interlayer insulating film is flattened and then the SiN etching on the surface of the field electrode is performed. Only the stop film is selectively exposed, and this exposed portion is removed.

Here, the following three methods are proposed as specific methods for flattening the interlayer insulating film.

(I-1) Chemical mechanical polishing (CMP) (I-2) After flattening the surface of the substrate with a resist film, etching back is performed.

(I-3) After the film formation is completed, an interlayer insulating film capable of achieving a substantially flattened shape is formed, and then etch back is performed.

On the other hand, as a method for removing the SiN film on the surface of the field electrode by patterning, the following (II)
And the method of (III) is proposed.

(II) Two kinds of etching masks are properly used when opening a contact hole and a via hole in the interlayer insulating film, and the contact hole is closed when the SiN film exposed in the via hole is selectively removed. A simple etching mask.

The following three methods are proposed as specific methods for realizing the method (II).

(II-1) The etching mask for contact holes and the etching mask for via holes are completely different masks. This method is also effective when the offset SiOx film and the SiN etching stop film are used together, or when the offset SiN film is also formed as the etching stop film.

(II-2) Using the common etching mask for the contact hole and the via hole, the interlayer insulating film and the Si
After the selective removal of the N etching stop film, another etching mask covering the completed contact hole is formed, and the offset SiOx film on the bottom surface of the via hole is selectively removed sequentially.

(II-3) Offset SiN using common etching mask for contact hole and via hole
After selectively removing the interlayer insulating film until the film is exposed, another etching mask covering the completed contact hole is formed, and the offset SiN film on the bottom surface of the via hole is selectively removed.

(III) Before the electrode is covered with the interlayer insulating film, the SiN etching stop film is formed only on the surface of the active region upper electrode, the sidewall is made of SiN, and the contact hole and the via hole are commonly etched. Performed using an etching mask. At this time, the photolithography for leaving the SiN etching stop film only on the active region before the electrode patterning is an increase over the conventional method.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below.

First Embodiment Here, according to the method (I-1) described above, the planarization of the interlayer insulating film for selectively exposing the SiN etching stopper film on the field region is performed by chemical mechanical polishing ( A wiring forming method using CMP will be described with reference to FIGS.

The subscript a of the reference numeral used in the figure is active.
Indicates a member on the (active) area, and the subscript f is a field (fie
ld) Represent a member on the area. Regarding the silicon oxide film (SiOx) that forms the interlayer insulating film, the conventional name of the film forming method is used as it is as the name of the film in consideration of the fact that the film characteristics differ depending on the film forming method. For example, a silicon oxide film formed by a plasma CVD method using tetraethoxysilane (TEOS) as a source gas is a plasma TEOS (p-TEOS) film, O ₃ -TEOS normal pressure C
The silicon oxide film formed by the VD method is O ₃ -TEOS.
A film, or a boron-phosphorus-silicate-glass (BPSG) film whose fluidity is enhanced by adding boron (B) or phosphorus (P) in the O ₃ -TEOS atmospheric pressure CVD method, is referred to as an O ₃ -BPSG film. I will call it.

First, as shown in FIG. 1, a field oxide film 2 (SiO ₂ ) is formed in a predetermined two-dimensional pattern on a silicon substrate 1 (Si), and an activity defined by the field oxide film 2 is formed. A wafer is prepared in which an active region upper electrode 4a and a field upper electrode 4f made of a first-layer polysilicon film are formed in the region and the field region, respectively. The active region upper electrode 4a and the field upper electrode 4f have a thickness of about 100 nm in order from the lower layer side.
Impurity-containing polysilicon film (polySi) and a tungsten silicide film (WSi) having a thickness of about 100 nm.
x) and are laminated. The active region upper electrode 4a is a gate electrode of a MOS transistor, and is formed on the Si substrate 1 via the gate oxide film 3 (SiO ₂ ).

Active area upper electrode 4a and field upper electrode 4
f is the offset SiOx film 5a,
5f (SiO ₂ ), side wall SiOx sidewall 6
By covering a and 6f respectively, insulation from the surroundings is achieved. Offset SiOx films 5a and 5f
Is patterned by commonly using an etching mask for patterning the electrodes 4a and 4f. In addition, the SiOx side walls 6a and 6f
Is obtained by anisotropically etching back a SiOx film formed over the entire surface of the substrate.

In the active region, the impurity diffusion layer 7 having the LDD structure is formed on the surface layer of the silicon substrate 1. This corresponds to the source / drain region of the MOS transistor. The impurity diffusion layer 7 is formed by low-concentration ion implantation immediately after the active region upper electrode 4a is patterned and high-concentration ion implantation immediately after the SiOx sidewalls 6a are formed on both sides thereof.

The entire surface of the substrate is, for example, plasma C
The film is covered with a SiN etching stop film 8 having a thickness of about 50 nm formed by the VD method. Then, for example, a thickness of about 30
A 0 nm O ₃ -TEOS film 9 is deposited on the entire surface. FIG.
Shows the steps up to here.

Next, as shown in FIG. 2, the O ₃ -
The TEOS film 9 is anisotropically etched back to form sidewalls 9SW on the outer sides of the SiOx sidewalls 6a and 6f. The sidewalls 9SW are formed for the purpose of compensating for the lack of local planarization characteristics due to the p-TEOS film 10 (see FIG. 3) and the CMP (chemical mechanical polishing) method described later.

Next, as shown in FIG. 3, a p-TEOS film 10 having a thickness of about 1 μm is deposited on the entire surface of the substrate. Then, the p-TEOS film 10 is subjected to CMP to flatten the surface of the substrate. As shown in FIG. 4, this CMP is stopped when the SiN etching stop film 8 is exposed on the side of the field region, but this stop is judged because the polishing rate of the SiN film is slower than that of the SiOx film. ,
It can be done relatively easily. At this time, in the active region, the p-TEOS film 10 remains above the active region upper electrode 4a with a thickness of about 100 to 150 nm.

Next, RIE (reactive ion etching) is performed under the condition that a sufficiently large etching selection ratio with respect to SiOx can be secured, and as shown in FIG.
The exposed portion of the N etching stop film 8 is selectively removed.
As a result, only the SiN etching stop film 8 on the surface of the field upper electrode 4f is selectively removed.

Next, as shown in FIG. 6, a p-TEOS film 11 having a thickness of about 400 nm is deposited on the entire surface of the substrate. The p-TEOS film 11 and the p-TEOS film 10 used for the flattening previously become the interlayer insulating film 12 on the present wafer. On this interlayer insulating film 12, a resist patterning is performed by usual photolithography and a developing process, and a resist layer for forming a first layer contact is formed.
A pattern 13 (PR) is formed. In this figure, there is a slight misalignment in the resist pattern 13,
The opening on the left side in the figure partially covers the edge of the active region upper electrode 4f.

Next, RIE of the interlayer insulating film 12 is performed under the condition that a sufficiently large selection ratio with respect to SiN can be secured, and contact holes 14a and via holes 14f are formed as shown in FIG. This RIE stops on the SiN etching stop film 8 on the active region side. However, since the offset SiOx film 5f is also etched on the field side, the via hole 14f reaching the field upper electrode 4f is formed. That is, unlike the conventional method, since only the SiN etching stop film 8 on the surface of the field electrode 4f is selectively removed before the formation of the interlayer insulating film 12, the offset SiOx film 5f is simultaneously etched at this stage. Therefore, it becomes possible to form contacts.

Next, in order to remove the SiN etching stop film 8 exposed on the bottom surface of the contact hole 14a, RIE is performed under the condition that the selection ratio with respect to silicon and silicon oxide is sufficiently large, as shown in FIG. Complete contact hole 14a. At this time, since the via hole 14f is already completed, it is not necessary to perform excessive overetching as in the conventional case, and therefore, the offset SiOx that covers the active region upper electrode 4a is not required.
There is no possibility that the film 5a and the SiOx sidewall 6a will be eroded. Further, it is needless to say that a sufficient selection ratio is secured also for the field upper electrode 4f exposed on the bottom surface of the via hole 14f. After that, the resist pattern 13 is removed by ashing.

In FIG. 9, the contact holes 14a and via holes 14f formed as described above are provided with tungsten plugs 15a and 15f through a Ti-based barrier metal.
The figure shows a state in which each is filled with (W) and further formed with an upper wiring 16 (Al) made of an Al-based multilayer film having a three-layer structure of, for example, a Ti-based adhesion layer / Al-1% Si film / TiN antireflection film. As can be seen from this figure, the substrate contact is achieved on the active region while ensuring a sufficient breakdown voltage between the active region upper electrode 4a and the upper layer wiring 16, and the field upper electrode 4f is formed on one field through the via hole 14f. The contact between the upper wiring 16 and the upper wiring 16 is ensured. That is, according to the present invention, it is possible to form a contact with the impurity diffusion layer in a self-aligning manner and at the same time make a contact with the field upper electrode 4f.

Second Embodiment Here, according to the method (I-2) described above, flattening of the interlayer insulating film for selectively exposing the SiN etching stop film on the field region is performed by resist etching back. A wiring forming method performed by using FIG.
This will be described with reference to FIG.

In FIG. 10, after the SiN etching stop film 8 is formed as described above in the first embodiment,
An O ₃ -BPSG film 17 having a thickness of about 300 nm is formed on the entire surface of the substrate.
It is shown that the surface is covered with and the surface thereof is planarized with a resist film 18 (PR).

Next, as shown in FIG.
The strike film 18 over the field area _Three -BPSG film 17
Etch back until exposed. Furthermore, the remaining cash register
O using the strike film 18 as a mask_Three -Etching of BPSG film 17
Chivac, as shown in FIG.
When the SiN etching stop film 8 is exposed on the area,
End this. At this point, the active area
O above the upper electrode 4a_Three -Approximately 200n of BPSG film 17
It remains in the thickness of m.

Next, under the condition that the etching of SiN proceeds while securing a sufficient selection ratio with respect to silicon oxide, R
By performing IE, as shown in FIG. 13, the SiN etching stop film 8 on the surface of the on-field electrode 4f is selectively removed.

Next, as shown in FIG. 14, after removing the remaining resist film 18 by O ₂ plasma ashing, about 30 O ₃ -BPSG film 19 is again formed on the entire surface of the substrate.
Deposit to a thickness of 0 nm and reflow at a temperature of 800-900 ° C. The O ₃ -TEOS film 19 and the O ₃ -BPSG film 17 formed previously become the interlayer insulating film 20 on the present wafer. A resist pattern 21 (PR) for forming a first layer contact is formed on the interlayer insulating film 20 by performing resist patterning by ordinary photolithography and development processing.

Next, RIE of the interlayer insulating film 20 and RIE of the SiN etching stop film 8 are sequentially performed to form connection holes, that is, contact holes 22a and via holes 22f, as shown in FIG. This RIE
The detailed procedure of is as described above in the first embodiment. Further, after ashing is performed to remove the resist pattern 21, both holes 22a and 22f are filled with tungsten plugs 23a and 23f (W), respectively, and the upper wiring 24 made of, for example, an Al-based multilayer film is patterned. 16 as shown in FIG.
The layer Al wiring is completed.

In the present embodiment, the etching back of the resist film 18 and the etching back of the O ₃ -BPSG film 17 are performed separately. However, if the end point can be accurately determined, these films are removed from the beginning. A constant speed etch back may be performed.

Third Embodiment Here, according to the method (I-3) described above, an inorganic SOG is used as an interlayer insulating film to be planarized to selectively expose the SiN etching stop film on the field region. A wiring forming method using a film will be described with reference to FIGS.

In FIG. 17, after the SiN etching stop film 8 is formed as described above in the first embodiment,
An inorganic SOG (spin-on-glass) film 25 (SOG) having a thickness of about 500 nm is applied and formed on the entire surface of the substrate to show a substantially flat surface. Next, as shown in FIG. 18, this inorganic SOG film 25 is formed on the field region by Si.
Anisotropically etch back until the N etching stop film 8 is exposed. At this point, in the active region, the inorganic SOG film 25 remains above the active region upper electrode 4a to a thickness of about 100 nm.

Next, under the condition that etching of SiN proceeds while securing a sufficient selection ratio with respect to silicon oxide, R
By performing the IE, as shown in FIG. 19, the SiN etching stop film 8 on the surface of the field upper electrode 4f is selectively removed.

Next, as shown in FIG. 20, a p-TEOS film 26 was deposited on the entire surface of the substrate to a thickness of about 400 nm. The p-TEOS film 26 and the inorganic SOG film 25 used for the flattening previously become the interlayer insulating film 27 on the present wafer. A connection hole, that is, a contact hole 28 is formed on the interlayer insulating film 27 through resist patterning.
After a and a via hole 28f are opened and resist ashing is performed, both holes 28a and 28f are filled with tungsten plugs 29a and 29f, respectively. Further, by patterning the upper layer wiring 30 made of an Al-based multilayer film, the first layer Al wiring is completed.

In this embodiment, inorganic SO is used as a constituent material of the interlayer insulating film capable of achieving substantially flattening at the time of film formation.
Although the G film is used, an organic SOG film may be used instead.

Fourth Embodiment In the present and subsequent embodiments, a method of adding a photolithography step once to the conventional method will be described, which is different from the above-described three embodiments. In the fourth embodiment, according to the method (II-1) described above, instead of using the SiN etching stop film as in the conventional method, a wiring forming method in which a contact hole and a via hole are opened in completely different etching steps. This will be described with reference to FIGS. 21 to 25.

In FIG. 21, after the SiN etching stop film 8 is formed as described above in the first embodiment,
A p-TEOS film 31 having a thickness of about 500 nm is formed on the entire surface of the substrate, and a resist pattern 32 for forming contact holes is formed on the surface of the p-TEOS film 31 by resist patterning.
The state where (PR) is formed is shown. However, unlike the previous three embodiments, the method described in this embodiment does not essentially utilize planarization of the interlayer insulating film. Therefore, the local flattening by the p-TEOS film 31 is not essential, and it is sufficient if the global flattening is almost achieved.

Next, RIE of the p-TEOS film 31 and the SiN etching stop film 8 is sequentially performed under the respective optimum conditions using the resist pattern 32 as a mask, so that the contact hole 3 is formed as shown in FIG.
Complete 3a.

Next, the resist pattern 32 is removed by ashing, and a resist pattern 34 (PR) for forming a via hole is newly formed as shown in FIG. The resist pattern 34 completely covers the already completed contact hole 33a.

Then, RIE of the p-TEOS film 31, the SiN etching stop film 8 and the offset SiOx film 5f is sequentially performed under the respective optimum conditions by using the resist pattern 34 as a mask, as shown in FIG. Thus, the via hole 33f is completed.

After that, the resist pattern 34 is removed by ashing. In the present embodiment, since the resist material enters the inside of the contact hole 4a, an ashing device that generates high-density plasma such as ECR plasma or helicon wave plasma should be used to prevent the occurrence of ashing residue during the ashing. Is desirable. After that, both holes 33a and 33f are filled with tungsten plugs 35a and 35f, respectively,
Further, by patterning the upper wiring 36 made of an Al-based multi-layer film, as shown in FIG.
Complete the wiring.

Although the process of forming the contact hole 33a first and forming the via hole 33f later is described in the present embodiment, the formation order may be reversed.

Fifth Embodiment Here, according to the above-mentioned method (II-3), the offset insulating film and the sidewall itself are made of SiN, so that the SiN etching stop film is omitted, and thereby the connection is made. FIG. 26 shows a wiring forming method capable of reducing the trouble of switching etching conditions when opening holes.
It will be described with reference to FIGS. In FIG. 26, the active region upper electrode 4a and the field upper electrode 4f made of the first-layer polysilicon film are formed in the active region and the field region defined by the field oxide film 2, respectively, and the entire surface of the substrate is p-TEOS. The p-TEOS film 39 is covered with a film 39 and a resist for forming a contact hole is formed on the surface of the p-TEOS film 39
The state where the pattern 40 (PR) is formed is shown.
However, unlike the previous embodiments, the active region upper electrode 4a and the field upper electrode 4f are coated with offset SiN films 37a and 37f (SiN 3) on their upper surfaces and SiN sidewalls 38a and 38f on their side surfaces, respectively. By doing so, insulation from the surroundings is achieved.
The offset SiN films 37a and 37f are formed on the electrodes 4 described above.
The patterning is performed by commonly using an etching mask for patterning a and 4f. Also, S
The iN sidewalls 38a and 38f are obtained by anisotropically etching back the SiN film formed so as to cover the entire surface of the base.

Next, as shown in FIG. 27, the p-TEOS film 39 is etched under the condition that a sufficiently high selection ratio can be secured for SiN and Si. By this etching, the contact hole 41a is completed on the active region side. On one field region side, the etching is stopped on the offset SiN film 37f, so that the via hole 41f is unfinished.

Therefore, in order to selectively remove the offset SiN film 37f, the resist pattern 40 is removed by ashing, and a resist pattern 42 (PR) for forming a via hole is newly formed as shown in FIG. To form. The resist pattern 42 completely covers the already completed contact hole 41a.

Then, the offset SiN film 37f is subjected to RIE using the resist pattern 42 as a mask to complete the via hole 41f as shown in FIG.

After that, these holes 41a, 4
1f is filled with tungsten plugs 43a and 43f, respectively, and the upper layer wiring 44 made of an Al-based multilayer film is patterned to complete the first layer Al wiring as shown in FIG.

In the present embodiment, the offset insulating film is made of the SiN film to simplify the etching. However, as described above, the SiN film is exposed during the opening etching of the contact hole and the via hole. Performing the steps up to the step itself is the same as offset SiOx film and Si
The same is possible when the N etching stop film is used together. This corresponds to the above method (II-2). That is, when the SiN etching stop film is exposed, the resist pattern is once peeled off to newly form a resist pattern covering the active region, and then the SiN etching stop film and the offset SiOx film are sequentially formed on the bottom surface of the via hole. It may be removed selectively.

Sixth Embodiment Here, according to the method of (III) described above, the SiN etching stop film is left only on the active region before the planarization by the interlayer insulating film, and the contact hole and the via hole are etched. A wiring forming method performed in a common process will be described with reference to FIGS.

First, as shown in FIG. 31, a field oxide film 2 is formed on a silicon substrate 1 (Si) according to a predetermined two-dimensional pattern, and the surface of an active region defined by the field oxide film 2 is heated. Gate oxide film 3 is formed by oxidation. Then, a tungsten polycide film 4 (polySi / WSix) having a thickness of about 200 nm,
Offset SiOx film 5 (SiO
x) and a SiN etching stop film 45 (SiN) having a thickness of about 50 nm were sequentially laminated. Here, the tungsten polycide film 4 has a thickness of about 10 in order from the lower layer side.
Impurity-containing polysilicon film of 0 nm and thickness of about 100 nm
And a WSix film of No. 3 are laminated. Further, resist patterning is performed on the surface of the SiN etching stop film 45, and a resist pattern 46 (PR) is formed in a range that substantially covers the active region. The photolithography performed at this time is one additional lithography addition to the conventional method.

Next, as shown in FIG. 32, using the resist pattern 46 as a mask, the SiN etching stop film 45 is etched under the RIE condition that can secure a sufficient selection ratio with respect to SiOx.

Next, resist patterning is performed to form a resist pattern 47 (PR) that follows the electrode pattern, as shown in FIG.

Then, using the resist pattern 47 as a mask, the offset SiOx film 5 and the tungsten polycide film 4 are sequentially etched under the respective optimum conditions, whereby the active region upper electrode 4a and the field upper electrode 4 are formed.
and f. Then, low-concentration ion implantation is performed to form LDD regions 7 _LDD in the surface layer portion of the silicon substrate 1. Furthermore, after etching the gate insulating film 3, a resist
The pattern 47 is removed by ashing. FIG. 34 shows a state in which the processes up to this point have been completed.

Next, for example, plasma CV is formed on the entire surface of the substrate.
A SiN film is formed by the D method and is anisotropically etched back to form SiN side walls 48a and 48f as shown in FIG. 35 on the side wall surfaces of the electrodes 4a and 4f, respectively. In this state, high concentration ion implantation is performed and LD
Source / drain regions having the D structure, that is, the impurity diffusion layers 7 are formed in a self-aligned manner.

Next, as shown in FIG. 36, a p-TEOS film 49 having a thickness of about 800 nm is formed on the entire surface of the substrate. Further, a resist pattern 50 is formed on the p-TEOS film 49. The resist pattern 50 is provided with an opening that follows the connection hole pattern, but there is a slight misalignment between the position of the opening and the positions of the electrodes 4a and 4f.

Next, as shown in FIG. 37, using the resist pattern 50 as a mask, p under the condition that a sufficient selection ratio can be secured with respect to SiN, Si, and WSix.
-The TEOS film 49 is etched. At this time, since the etching is stopped by the SiN etching stop film 45a and the SiN sidewall 48a on the active region side, the contact hole 51a is completed while sufficiently insulating the upper electrode 4f of the active region. On one side of the field region, the SiN film does not exist on the surface of the field upper electrode 4f from the beginning, so that the offset SiO 2 is formed by the above etching.
Since the x film 5f can be removed at the same time, the via hole 51f is completed.

Thereafter, ashing is performed to remove the resist pattern 50. Then, these holes 51
By filling the a and 51f with tungsten plugs 52a and 52f, respectively, and patterning the upper layer wiring 53 made of an Al-based multilayer film, the first layer Al wiring is completed as shown in FIG.

According to the present embodiment, since the contact hole 4a and the via hole 4f can be simultaneously formed in one dry etching step as described above, the fourth embodiment or the fifth embodiment is possible. Unlike the above, it is not necessary to form the resist pattern in such a manner that the resist material penetrates into the contact hole. Therefore, there is a merit that ashing becomes easy.

Although the sixth embodiment of the present invention has been described above, the present invention is not limited to these embodiments, and the structure of the sample wafer, the kind of each material film and the formation thereof. The film method can be appropriately changed or selected.

[0080]

As is apparent from the above description, according to the present invention, it is possible to achieve the substrate contact and the on-field wiring contact in the same layer when the SAC structure, which has been impossible in the past, is adopted. Become. Therefore, the present invention greatly contributes to expanding the range of application of SAC, thereby increasing the degree of freedom in device design and, in turn, promoting the miniaturization of devices.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which a SiN etching stop film and an O ₃ -TEOS film are sequentially formed to cover an active region upper electrode and a field upper electrode in a first embodiment of the present invention. It is a figure.

FIG. 2 is a schematic cross-sectional view showing a state where the O ₃ —TEOS film of FIG. 1 is etched back to form sidewalls.

3 is a schematic cross-sectional view showing a state in which a p-TEOS film is formed on the entire surface of the base body of FIG.

FIG. 4 is a schematic cross-sectional view showing a state in which the p-TEOS film of FIG. 3 is planarized by CMP and the SiN etching stop film is exposed in the field region.

5 is a schematic cross-sectional view showing a state where an exposed portion of the SiN etching stop film of FIG. 4 is selectively removed.

6 is a schematic cross-sectional view showing a state in which a p-TEOS film is deposited on the entire surface of the base body of FIG. 5 and resist patterning is further performed.

FIG. 7 is a schematic cross-sectional view showing a state in which the interlayer insulating film and the offset SiOx film on the surface of the field electrode in FIG. 6 are selectively removed to complete only the via hole.

FIG. 8 is a schematic cross-sectional view showing a state in which an exposed portion of the SiN etching stopper film of FIG. 7 is selectively removed to complete a contact hole.

9 is a schematic cross-sectional view showing a state in which the contact hole and the via hole in FIG. 8 are filled with a tungsten plug to form an upper layer wiring.

FIG. 10 shows a second embodiment of the present invention in which an SiN etching stop film and an O ₃ -BPSG film are sequentially formed so as to cover the active region upper electrode and the field upper electrode, and the surface of the substrate is resist-coated. It is a typical sectional view showing the state where it was made flat with a film.

FIG. 11 is a schematic cross-sectional view showing a state in which the resist film of FIG. 10 is etched back to expose the O ₃ -BPSG film on the field region side.

FIG. 12 is a graph of O ₃ using the residual resist film of FIG. 11 as a mask.
-Etch back the BPSG film and apply S on the field area side.
It is a typical sectional view showing the state where the iN etching stop film was exposed.

13 is a schematic cross-sectional view showing a state where the exposed portion of the SiN etching stop film of FIG. 12 is selectively removed.

14 is a schematic cross-sectional view showing a state in which an O ₃ -BPSG film is deposited on the entire surface of the base body in FIG. 13 and resist patterning is further performed.

15 is a schematic cross-sectional view showing a state where contact holes and via holes are completed by etching the exposed portion of the interlayer insulating film and the offset SiOx film and the SiN etching stop film of FIG.

16 is a schematic cross-sectional view showing a state in which the contact hole and the via hole in FIG. 15 are filled with a tungsten plug to form an upper layer wiring.

FIG. 17 is a schematic cross-sectional view showing a state in which an upper electrode of an active region and an upper electrode of a field are covered with a SiN etching stop film and then the entire surface of a substrate is planarized with an SOG film in a third embodiment of the invention. It is a figure.

FIG. 18 is a schematic cross-sectional view showing a state where the SOG film of FIG. 17 is etched back to expose the SiN etching stop film on the field region side.

FIG. 19 is a schematic cross-sectional view showing a state where the exposed portion of the SiN etching stop film of FIG. 18 is selectively removed.

20 is a schematic cross-sectional view showing a state in which a p-TEOS film is formed, a connection hole is formed, and an upper layer wiring is formed on the base body of FIG.

21. In the fourth embodiment of the present invention, after covering the active region upper electrode and the field upper electrode with a SiN etching stop film, a p-TEOS film is formed on the entire surface of the substrate, and the active region is further formed. FIG. 6 is a schematic cross-sectional view showing a state in which a resist pattern having an opening on the side is formed.

FIG. 22 is a schematic cross-sectional view showing a state in which the p-TEOS film and the SiN etching stop film of FIG. 21 are selectively removed on the active region side to complete a contact hole.

23 is a schematic cross-sectional view showing a state in which a resist pattern covering the contact hole of FIG. 22 and having an opening on the field region side is formed.

24 is a schematic cross-sectional view showing a state in which the p-TEOS film, the SiN etching stop film, and the offset SiOx film in FIG. 23 are selectively removed on the field region side to complete a via hole.

25 is a schematic cross-sectional view showing a state in which the contact hole and the via hole in FIG. 24 are filled with a tungsten plug to form an upper layer wiring.

FIG. 26 is a cross-sectional view of a fifth embodiment of the present invention, in which an active region upper electrode and a field upper electrode surrounded by an offset SiN film and SiN sidewalls are covered with p-TE.
FIG. 3 is a schematic cross-sectional view showing a state in which an OS film is formed and a resist pattern is further formed.

27 selectively removes the p-TEOS film of FIG.
FIG. 6 is a schematic cross-sectional view showing a state in which only the contact hole is completed and the via hole is incomplete.

28 is a schematic cross-sectional view showing a state in which a resist pattern covering the contact hole of FIG. 27 and having an opening only on the field region side is formed.

FIG. 29 is a schematic cross-sectional view showing a state in which an exposed portion of the offset SiN film of FIG. 28 is selectively removed to complete a via hole.

30 is a schematic cross-sectional view showing a state in which the contact hole and the via hole in FIG. 29 are filled with a tungsten plug to form an upper wiring.

FIG. 31 is a diagram showing a sixth embodiment of the present invention, in which a tungsten polycide film, an offset oxide film, and
FIG. 3 is a schematic cross-sectional view showing a state in which SiN etching stop films are sequentially stacked and a resist pattern covering the active region side is further formed.

32 is a schematic cross-sectional view showing a state where the exposed portion of the SiN etching stop film of FIG. 31 is selectively removed.

33 is a schematic cross-sectional view showing a state in which the resist pattern of FIG. 32 is removed and a new resist pattern that follows the electrode pattern is formed.

34 is a schematic cross-sectional view showing a state in which an active region upper electrode and a field upper electrode are formed by etching the multilayer film of FIG. 33. FIG.

35 is a schematic cross-sectional view showing a state in which SiN sidewalls are formed on the sidewalls of the active region upper electrode and the field upper electrode in FIG. 34.

36 is a schematic cross-sectional view showing a state in which a p-TEOS film is formed on the entire surface of the base body of FIG. 35 and resist patterning is performed thereon.

37 is a schematic cross-sectional view showing a state in which the p-TEOS film and the offset SiOx film on the field region side of FIG. 36 are selectively removed to complete a contact hole and a via hole at the same time.

38 is a schematic cross-sectional view showing a state in which the contact hole and the via hole in FIG. 37 are filled with a tungsten plug to form an upper wiring.

FIG. 39 is a schematic cross-sectional view showing a state in which a substrate contact and an on-field electrode contact are simultaneously formed by a conventional aligned contact method.

FIG. 40 is a schematic view showing a state in which a SiN etching stop film and an interlayer insulating film are sequentially formed to cover the active region upper electrode and the field upper electrode in the conventional SAC method, and then resist patterning is performed. FIG.

41 is a schematic cross-sectional view showing a state where the interlayer insulating film of FIG. 40 is selectively etched.

42 is a schematic cross-sectional view showing a state in which the exposed portion of the SiN etching stop film of FIG. 41 is selectively removed and only the contact hole is completed and the via hole is unfinished.

43 is a schematic cross-sectional view showing a state where a contact failure has occurred in the via hole as a result of filling the contact hole and the via hole in FIG. 42 with a tungsten plug to form an upper layer wiring.

FIG. 44 is a schematic cross-sectional view showing a state where the active region upper electrode is partially exposed in the contact hole as a result of selectively removing the offset SiOx film exposed in the via hole in FIG. 42.

45 is a schematic cross-sectional view showing a state in which a contact hole and a via hole in FIG. 44 are filled with a tungsten plug to form an upper layer wiring, and as a result, a withstand voltage defect occurs in the contact hole.

[Explanation of symbols]

1 Silicon Substrate 2 Field Oxide Film 4a Active Area Upper Electrode 4f Field Upper Electrode 5a, 5f Offset SiOx Film 6a, 6f SiOx Side Wall 8, 45a SiN Etching Stop Film 10 O ₃ -TEOS Film 11 p-TEOS Film 12 Interlayer Insulating Film 14a, 22a, 28a, 33a, 41a, 51a Contact hole 14f, 22f, 28f, 33f, 41f, 51f Via hole 37a, 37f Offset SiN film 38a, 38f, 48a, 48f SiN sidewall

Claims (15)

[Claims] 1. A wiring forming method for forming a first-layer contact of a semiconductor device by applying a self-aligned contact method, which is a self-aligned substrate contact adjacent to an electrode formed on an active region of a semiconductor substrate. And a wiring contact to an electrode formed on a field region of the semiconductor substrate, which is formed in the same layer as the first layer contact. 2. A wiring forming method for forming a first-layer contact of a semiconductor device by applying a self-aligned contact method, wherein a top surface and a side surface of a first insulating material are formed in an active region and a field region of a semiconductor substrate, respectively. A first step of forming an active region upper electrode and a field upper electrode, which are covered with an offset insulating film made of, and a sidewall, respectively; and a second step of ensuring an etching selection ratio with respect to the first insulating material. A second step of forming an etching stopper film that conformally covers the entire surface of the substrate by using an insulating material; and a third step of selectively removing the etching stopper film from at least the surface of the field upper electrode in the field region.
A fourth step of covering the entire surface of the substrate with an interlayer insulating film made of a first insulating material, and selectively removing the interlayer insulating film through an etching mask so that at least in the active region. A fifth step of simultaneously forming a contact hole in which a part of the bottom surface faces the surface of the semiconductor substrate, a via hole reaching the surface of the field upper electrode in the field region at the same time, and using the etching mask as it is, A sixth step of selectively removing the etching stopper film exposed on the bottom surface. 3. The wiring forming method according to claim 2, wherein the first insulating material is a silicon oxide based material and the second insulating material is a silicon nitride based material. 4. In the fourth step, the entire surface of the substrate is once
After coating with a thick interlayer insulating film made of the first insulating material,
By reducing the film thickness, at least the etching stopper film on the surface of the field electrode can be exposed on the field region, and the exposed portion can secure the etching selection ratio of the etching stopper film to the first insulating material. The wiring forming method according to claim 2, wherein etching is performed under the conditions. 5. The wiring forming method according to claim 4, wherein the film thickness of the interlayer insulating film is reduced by chemical mechanical polishing. 6. The film thickness of the interlayer insulating film is adjusted so that a substrate surface is flattened by a resist film, a first etch back of the resist film, and a first etch back of the interlayer insulating film exposed by the first etch back. 5. The reduction after 2 etchbacks.
The wiring forming method according to the above. 7. The wiring forming method according to claim 4, wherein the interlayer insulating film is made of a first insulating material capable of substantially flattening the surface of the substrate, and the film thickness thereof is reduced by etching back. 8. A wiring forming method for forming a first-layer contact of a semiconductor device by applying a self-aligned contact method, wherein a top surface and a side surface of a first insulating material are formed in an active region and a field region of a semiconductor substrate, respectively. A first step of forming an active region upper electrode and a field upper electrode, which are covered with an offset insulating film made of, and a sidewall, respectively; and a second step of ensuring an etching selection ratio with respect to the first insulating material. A second step of forming an etching stopper film that conformally covers the entire surface of the base using an insulating material; a third step of covering the entire surface of the base with an interlayer insulating film made of the first insulating material; And selectively removing the interlayer insulating film and the etching stop film in the active region through an etching mask that covers the active region. A fourth step of performing sequential selective removal of the interlayer insulating film, the etching stopper film, and the offset insulating film in the field region through another etching mask that covers A wiring forming method having. 9. The wiring forming method according to claim 8, wherein the first insulating material is a silicon oxide based material, and the second insulating material is a silicon nitride based material. 10. A wiring forming method for forming a first-layer contact of a semiconductor device by applying a self-aligned contact method, wherein a top surface and a side surface of a first insulating material are provided in an active region and a field region of a semiconductor substrate, respectively. A first step of forming an active region upper electrode and a field upper electrode, which are covered with an offset insulating film made of, and a sidewall, respectively; and a second step of ensuring an etching selection ratio with respect to the first insulating material. A second step of forming an etching stopper film that conformally covers the entire surface of the base using an insulating material; a third step of covering the entire surface of the base with an interlayer insulating film made of the first insulating material; By selectively removing the film and the etching stop film through the etching mask, at least a part of the bottom surface of the semiconductor substrate is within the active region. A fourth step of simultaneously forming a contact hole reaching the surface, a via hole facing the field upper electrode in the field region, and an offset insulation exposed on the bottom surface of the via hole through another etching mask covering the active region. A fifth step of sequentially and selectively removing the film. 11. The wiring forming method according to claim 10, wherein the first insulating material is a silicon oxide based material, and the second insulating material is a silicon nitride based material. 12. A wiring forming method for forming a first-layer contact of a semiconductor device by applying a self-aligned contact method, comprising: a second insulating material formed on an upper surface and a side surface of an active region and a field region of a semiconductor substrate, respectively. A first step of forming an active region upper electrode and a field upper electrode, which are covered with an offset insulating film made of, and a sidewall, respectively; and a first step of ensuring an etching selection ratio with respect to the second insulating material. A second step of covering the entire surface of the substrate with an interlayer insulating film made of an insulating material, and by selectively removing the interlayer insulating film through an etching mask, at least a part of the bottom surface is formed on the active region. A third step of simultaneously forming a contact hole reaching the surface of the semiconductor substrate and a via hole facing the field upper electrode on the field region; A fourth step of selectively removing the offset insulating film exposed on the bottom surface of the via hole through another etching mask covering the active region. 13. The wiring forming method according to claim 12, wherein the first insulating material is a silicon oxide based material, and the second insulating material is a silicon nitride based material. 14. A wiring forming method for forming a first-layer contact of a semiconductor device by applying a self-aligned contact method, comprising: an electrode film, a first electrode on a semiconductor substrate in which an active region and a field region are defined. Forming a multi-layered film in which an offset insulating film made of the above insulating material and an etching stop film made of a second insulating material capable of ensuring an etching selection ratio are stacked in this order. A second step of selectively removing the etching stopper film in the field region, patterning the multilayer film to form an active region upper electrode and a field upper electrode in the active region and the field region, respectively. A third step of forming an electrode, and a fourth step of forming a sidewall made of a second insulating material on sidewall surfaces of the active region upper electrode and the field upper electrode. A fifth step of covering the entire surface of the substrate with an interlayer insulating film made of a first insulating material, and by selectively removing the interlayer insulating film through an etching mask, at least one of the bottom surfaces in the active region is covered. 6. A wiring forming method comprising: a sixth step of simultaneously forming a contact hole whose portion reaches the surface of the semiconductor substrate and a via hole reaching the surface of the field upper electrode in the field region. 15. The wiring forming method according to claim 14, wherein the first insulating material is a silicon oxide based material, and the second insulating material is a silicon nitride based material.