KR20010058563A - Method for forming pattern of semiconductor memory device by using dual damascene - Google Patents
Method for forming pattern of semiconductor memory device by using dual damascene Download PDFInfo
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- KR20010058563A KR20010058563A KR1019990065908A KR19990065908A KR20010058563A KR 20010058563 A KR20010058563 A KR 20010058563A KR 1019990065908 A KR1019990065908 A KR 1019990065908A KR 19990065908 A KR19990065908 A KR 19990065908A KR 20010058563 A KR20010058563 A KR 20010058563A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Abstract
Description
본 발명은 반도체 메모리 소자 제조 분야에 관한 것으로, 쌍상감(dual damascene) 방법을 이용한 반도체 소자의 패턴 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a pattern formation method of a semiconductor device using a dual damascene method.
Cu 등을 이용한 반도체 소자의 금속배선 형성 과정에서는 상감 공정이 이용되고 있는데, 공정의 순서에 따라 트렌치 우선 공정(trench first), 비아 우선(via first) 공정 또는 자기정렬(self align) 쌍상감 공정(dual damascene) 등으로 나누어진다. 개발 초기에는 전술한 세 가지 방법이 모두 거론되었으나, 소자의 집적도 증가에 따른 포토리소그래피 공정의 한계, 오정렬 문제에 따른 비아 폭의 문제 등에 따라 근래에는 비아 우선 쌍상감 공정(via first dual damascene)이 주류를 이루고 있다.A damascene process is used to form metallization of a semiconductor device using Cu or the like. Depending on the order of the process, a trench first process, a via first process, or a self-aligned pairwise process ( dual damascene). In the early stages of development, all three methods mentioned above have been discussed, but via first dual damascene has become the mainstream in recent years due to the limitation of photolithography process due to the increase in device density and the problem of via width due to misalignment problem. To achieve.
첨부 도면 도1a 내지 도1e를 참조하여 비아 우선 쌍상감 공정 방법을 설명한다.Referring to the accompanying drawings, FIGS. 1A-1E, a via-first pair-delay process method will be described.
도1a는 반도체 기판(10) 상부에 형성된 Cu 등의 금속막 패턴(11)을 덮는 금속막 보호용 절연막(12)을 형성하고, 그 상부에 제1 저유전막(13), 제1 식각장벽막(14), 제2 저유전막(15) 및 제2 식각장벽막(16)을 적층하고 제2 식각장벽막(16) 상에 비아 마스크로 이용되는 포토레지스트 패턴(PR1)을 형성한 상태를 보이고 있다. 상기 금속막 보호용 절연막(12)은 SiN으로 형성하고, 상기 제2 식각장벽막(14) 및 제2 식각장벽막(16)은 SiO2, SiC, SiN 등으로 형성한다.FIG. 1A shows a metal film protective insulating film 12 covering a metal film pattern 11 such as Cu formed on an upper portion of a semiconductor substrate 10, and a first low dielectric film 13 and a first etch barrier film (top) formed thereon. 14), the second low dielectric film 15 and the second etch barrier film 16 are stacked and the photoresist pattern PR1 used as a via mask is formed on the second etch barrier film 16. . The metal film protective insulating layer 12 is formed of SiN, and the second etching barrier film 14 and the second etching barrier film 16 are formed of SiO 2 , SiC, SiN, or the like.
도1b는 비아 마스크인 포토레지스트(PR1)로 덮이지 않은 제2 식각장벽막(16), 제2 저유전막(15), 제1 식각장벽막(14) 및 제1 저유전막(13)을 식각하여 그 바닥에 금속막 보호용 절연막(12)을 노출시키는 비아를 형성한 상태를 보이고 있다.FIG. 1B shows the etching of the second etching barrier film 16, the second low dielectric film 15, the first etching barrier film 14, and the first low dielectric film 13 not covered with the photoresist PR1, which is a via mask. As shown in the figure, a via is formed in the bottom thereof to expose the metal film protective insulating film 12.
도1c는 비아 마스크로 이용된 포토레지스트 패턴(PR1)을 제거하고 제2 식각장벽막(16) 상에 트렌치 마스크로 이용될 포토레지스트 패턴(PR2)을 형성하고, 식각방지를 위해 비아 내부에 제1 식각장벽막(14) 높이까지 포토레지스트(PR3)를 채운 상태를 보이고 있다.FIG. 1C illustrates that the photoresist pattern PR1 used as the via mask is removed, and the photoresist pattern PR2 to be used as the trench mask is formed on the second etching barrier layer 16. 1 shows a state where the photoresist PR3 is filled up to the height of the etching barrier film 14.
도1d는 제2 식각장벽막(16), 제2 저유전막(15)을 선택적으로 식각하여 제1 식각장벽막(14) 상부면의 일부를 노출시키는 트렌치를 형성한 상태를 보이고 있다. 이와 같이 비아를 먼저 형성시키는 방법을 통상적으로 비아 우선 쌍상감 공정이라고 칭하고 있다.FIG. 1D shows a state in which a trench is formed to selectively expose a portion of the upper surface of the first etching barrier layer 14 by selectively etching the second etching barrier layer 16 and the second low dielectric layer 15. As described above, the method of forming the via first is generally referred to as a via-first twinning process.
도1e는 트렌치 마스크로 이용된 포토레지스트 패턴(PR2) 및 비아 내부의 포토레지스트(PR3)를 제거하고 보호용 절연막(12) 제거를 위한 식각 공정을 실시하여 금속막 패턴(11)을 노출시킨 상태를 보이고 있다. 전술한 종래 기술은 보호용 절연막(12) 제거과정에서 식각장벽막(16, 14)의 손실이 발생하고 노출된 저유전막(13, 15)이 손상되는 문제가 발생한다.FIG. 1E illustrates a state in which the metal film pattern 11 is exposed by removing the photoresist pattern PR2 and the photoresist PR3 inside the via and using an etching process to remove the protective insulating layer 12. It is showing. In the above-described prior art, the loss of the etch barrier films 16 and 14 occurs in the process of removing the protective insulating film 12 and the exposed low dielectric films 13 and 15 are damaged.
한편, 종래 상기 금속막 패턴(11)은 성능을 향상시키기 위하여 Al에 비하여 비저항이 작은 Cu로 형성하며, 배선간의 캐패시턴스를 감소시키고자 층간절연막으로 저유전막을 사용하고 있다.On the other hand, the metal film pattern 11 is conventionally formed of Cu having a lower specific resistance than Al in order to improve performance, and a low dielectric film is used as the interlayer insulating film to reduce the capacitance between wirings.
이와 같은 저유전 절연막의 도입에 따라 쌍상감 공정에서 여러가지 문제점이 대두되고 있으나, 가장 근원적인 문제는 모든 저유전막이 가지는 내산화성의 문제이다. 즉, 포토리소그래피 및 식각 공정을 진행하여 쌍상감 구조를 형성할 때 포토레지스트의 형성, 식각공정 후 산소 플라즈마를 이용한 포토레지스트 제거, 트렌치형성 후의 세정 공정 등이 수반되는데, 이와 같은 과정에서 산소에 의해 저유전막이 손상되는 문제점이 있다.With the introduction of such a low dielectric insulating film, various problems have arisen in the dual phase damaging process, but the most fundamental problem is the oxidation resistance problem of all low dielectric films. That is, photolithography and etching processes are performed to form a pair-like structure, followed by formation of photoresist, removal of photoresist using oxygen plasma after etching process, and cleaning process after trench formation. There is a problem that the low-k dielectric is damaged.
상기와 같은 문제점을 해결하기 위한 본 발명은 비아 및 트렌치로 이루어지는 쌍상감 구조 형성 과정에서 저유전막이 손상되는 것을 효과적으로 방지하고, 포토레지스트 형성 및 제거 과정에서 저유전막이 산소에 노출되는 것을 효과적으로 방지할 수 있는 쌍상감법을 이용한 반도체 소자의 패턴 형성 방법을 제공하는데 그 목적이 있다.The present invention to solve the above problems effectively prevent damage to the low-k dielectric in the process of forming a pair-symmetric structure consisting of vias and trenches, and effectively prevent the low-k dielectric exposed to oxygen during the photoresist formation and removal process SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a pattern of a semiconductor device using a dual image reduction method.
도 1a 내지 도 1e는 종래의 쌍상감 방법을 보이는 공정 단면도,1a to 1e is a cross-sectional view showing a conventional method of twinning;
도 2a 내지 도 2f는 본 발명의 실시예에 따른 쌍상감법을 이용한 비트라인 패턴 형성 공정 단면도.2A to 2F are cross-sectional views of a bit line pattern forming process using a pair image reduction method according to an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for main parts of the drawings *
20: 실리콘 기판 21: 금속막 패턴20: silicon substrate 21: metal film pattern
22: 보호용 절연막 23, 25: 저유전막22: protective insulating film 23, 25: low dielectric film
24, 26: 식각장벽막24, 26: etching barrier
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 형성된 금속막을 보호하는 보호절연막을 형성하는 제1 단계; 상기 보호절연막 상에 제1 절연막을 형성하는 제2 단계; 상기 제1 절연막 상에, 상기 제1 절연막 보다 유전율이 큰 제2 절연막을 형성하는 제3 단계; 상기 제2 절연막 상에, 상기 제2 절연막 보다 유전율이 작은 제3 절연막을 형성하는 제4 단계; 상기 제2 절연막 상에, 상기 제3 절연막 보다 유전율이 큰 제4 절연막을 형성하는 제5 단계; 상기 제4 절연막, 상기 제3 절연막, 상기 제2 절연막 및 상기 제1 절연막을 선택적으로 식각하여 그 바닥에 상기 보호절연막을 노출시키는 제1 개구부를 형성하는 제6 단계; 상기 제6 단계가 완료된 전체 구조 상에 산화막을 형성하는 제7 단계; 상기 제4 절연막 및 상기제3 절연막을 선택적으로 식각하여 상기 제1 개구부와 연결되며 상기 제1 개구부 보다 폭이 큰 제2 개구부를 형성하는 제8 단계; 상기 제1 개구부 하부에 노출된 상기 보호절연막을 선택적으로 식각하여 상기 금속막을 노출시키는 제9 단계; 및 상기 제1 개구부 및 상기 제2 개구부 내에 전도막을 채워 상기 금속막과 연결시키는 제10 단계를 포함하는 반도체 소자 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a protective insulating film to protect the metal film formed on the semiconductor substrate; Forming a first insulating film on the protective insulating film; Forming a second insulating film on the first insulating film, the second insulating film having a higher dielectric constant than the first insulating film; Forming a third insulating film on the second insulating film, the third insulating film having a lower dielectric constant than the second insulating film; Forming a fourth insulating film on the second insulating film, the fourth insulating film having a higher dielectric constant than the third insulating film; A sixth step of selectively etching the fourth insulating film, the third insulating film, the second insulating film and the first insulating film to form a first opening exposing the protective insulating film on a bottom thereof; A seventh step of forming an oxide film on the entire structure in which the sixth step is completed; An eighth step of selectively etching the fourth insulating film and the third insulating film to form a second opening connected to the first opening and having a width greater than that of the first opening; A ninth step of selectively etching the passivation insulating layer exposed under the first opening to expose the metal layer; And a tenth step of filling a conductive film in the first opening and the second opening and connecting the conductive film to the metal film.
본 발명은 반도체 기판 상에 적층된 절연막을 식각하여 반도체 기판을 노출시키는 비아홀을 형성하고, 전체 구조 상에 얇은 두께의 산화막을 형성하고 이후 트렌치 형성을 위한 공정을 진행함으로써 트렌치 형성 과정에 필요한 포토레지스트 형성 및 제거과정에서 저유전막이 손상되거나 산소에 노출되는 것을 방지하는데 특징이 있다.The present invention forms a via hole for exposing a semiconductor substrate by etching an insulating layer stacked on the semiconductor substrate, forming a thin oxide film on the entire structure, and then performing a process for forming a trench. It is characterized by preventing the low-k dielectric from being damaged or exposed to oxygen during formation and removal.
이하, 첨부된 도면 도 2a 내지 도 2f를 참조하여 본 발명의 실시예에 따른 반도체 메모리 소자의 비트라인 형성 방법을 설명한다.Hereinafter, a method of forming a bit line of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 2A through 2F.
먼저 도2a에 도시한 바와 같이 반도체 기판(20) 상부에 형성된 금속막 패턴(21)을 덮는 250 Å 내지 1000 Å 두께의 금속막 보호용 절연막(22)을 형성하고, 그 상부에 제1 저유전막(23), 제1 식각장벽막(24), 제2 저유전막(25) 및 제2 식각장벽막(26)을 적층하고 제2 식각장벽막(26) 상에 비아 마스크로 이용되는 포토레지스트 패턴(PR1)을 형성한다.First, as shown in FIG. 2A, an insulating film 22 for protecting a metal film having a thickness of 250 kHz to 1000 는 is formed to cover the metal film pattern 21 formed on the semiconductor substrate 20. The first low dielectric film ( 23), a photoresist pattern stacked on the first etch barrier film 24, the second low dielectric film 25, and the second etch barrier film 26 and used as a via mask on the second etch barrier film 26 ( PR1).
상기 금속막 보호용 절연막(22)은 SiH4, NH3, N2등의 반응 기체를 이용하여형성한 SiN막 또는 SiON으로 이루어지거나, 트리메칠실란(trimethyl silane) 또는 테트라메칠실란(tetramethyl silane) 중 어느 하나와, H2,Ar, N2의 혼합가스를 이용하여 형성한 SiC로 이루어진다. 이러한 금속막 보호용 절연막(22) 형성을 위해서는 플라즈마 화학기상증착법(plasma enhanced chemical vapor deposition, PECVD)이 이용된다.The metal film protective insulating layer 22 may be formed of a SiN film or SiON formed using a reaction gas such as SiH 4 , NH 3 , N 2 , or the like. It made of one and, H 2, the SiC formed using a mixed gas of Ar, N 2. Plasma enhanced chemical vapor deposition (PECVD) is used to form the metal layer protective insulating layer 22.
상기 제1 저유전막(23) 및 제2 저유전막(25)은 방향(aromatic)계 탄소화합물인 스핀온 폴리머(spin on polymer) 계통의 절연막 또는 탄소가 도핑된 SiO2막으로 이루어진다.The first low dielectric layer 23 and the second low dielectric layer 25 may be formed of an insulating film of a spin on polymer based on an aromatic carbon compound or a SiO 2 film doped with carbon.
상기 제1 식각장벽막(24) 및 제2 식각장벽막(26)은 플라즈마로 형성된 SiO2, SiN, SiC 등으로 이루어지며 그 두께는 500 Å 내지 3000 Å이 되도록 한다.The first etching barrier layer 24 and the second etching barrier layer 26 may be made of SiO 2 , SiN, SiC, or the like, which are formed of plasma, and have a thickness of 500 μm to 3000 μm.
다음으로 도2b에 도시한 바와 같이 비아 마스크인 포토레지스트(PR1)로 덮이지 않은 제2 식각장벽막(26), 제2 저유전막(25), 제1 식각장벽막(24) 및 제1 저유전막(23)을 식각하여 그 바닥에 금속막 보호용 절연막(22)을 노출시키는 비아를 형성한다.Next, as shown in FIG. 2B, the second etching barrier film 26, the second low dielectric film 25, the first etching barrier film 24, and the first low film not covered with the photoresist PR1 as a via mask are next. The dielectric layer 23 is etched to form vias exposing the metal layer protective insulating layer 22 at the bottom thereof.
이어서 도2c에 도시한 바와 같이 비아 마스크로 이용된 포토레지스트 패턴(PR1)을 제거하고 전체 구조 상에 얇은 산화막(27)을 형성한다.Subsequently, as shown in FIG. 2C, the photoresist pattern PR1 used as the via mask is removed and a thin oxide film 27 is formed on the entire structure.
상기 산화막(27)으로는 PECVD 방법 또는 상압화학기상증착법(atmospheric pressure chemical vapor deposition, APCVD)으로 형성된 SiO2막을 적용하거나 PECVD법으로 형성되며 유전율이 3.5 내지 3.8인 SiOF막을 적용할 수 있다.As the oxide layer 27, a SiO 2 film formed by a PECVD method or an atmospheric pressure chemical vapor deposition (APCVD) may be applied, or a SiOF film formed by PECVD and having a dielectric constant of 3.5 to 3.8 may be used.
보다 구체적으로 설명하면, PECVD법으로 SiO2막을 형성할 경우에는 SiH4, N2O, O2의 혼합가스, TEOS와 O2의 혼합가스 또는 TEOS와 N2O의 혼합가스를 이용하여 형성한다. 이때, 증착막의 층덮힘 특성을 양호하게 하기 위하여 바이어스 전압을 인가할 수 있다.In more detail, when the SiO 2 film is formed by PECVD, SiH 4 , N 2 O, O 2 mixed gas, TEOS and O 2 mixed gas or TEOS and N 2 O mixed gas is formed. . At this time, a bias voltage may be applied to improve the layer covering characteristic of the deposited film.
APCVD법으로 SiO2막을 형성할 경우에는 TEOS, O3, N2O, O2의 혼합가스를 사용하여 200 torr 내지 760 torr의 압력에서 350 ℃ 내지 450 ℃ 온도조건으로 형성한다.When the SiO 2 film is formed by the APCVD method, a mixed gas of TEOS, O 3 , N 2 O, and O 2 is formed under a temperature condition of 350 ° C. to 450 ° C. at a pressure of 200 torr to 760 torr.
PECVD법으로 SiOF막을 형성할 경우는 SiH4, N2O, C2F6, CF4의 혼합가스, TEOS, O2, C2F6, CF4의 혼합가스 또는 TEFS와 O2의 혼합가스를 이용하여 형성한다. 이때, 증착막의 층덮힘 특성을 양호하게 하기 위하여 바이어스 전압을 인가할 수 있다.In case of forming SiOF film by PECVD, SiH 4 , N 2 O, C 2 F 6 , CF 4 mixed gas, TEOS, O 2 , C 2 F 6 , CF 4 mixed gas or TEFS and O 2 mixed gas To form. At this time, a bias voltage may be applied to improve the layer covering characteristic of the deposited film.
다음으로 도2d에 도시한 바와 같이 제2 식각장벽막(24) 상부의 산화막(27) 상에 트렌치 마스크로 이용될 포토레지스트 패턴(PR2)을 형성한다. 이때, 식각방지를 위해 비아 내부에 제1 식각장벽막(24) 정도 높이까지 포토레지스트(PR3)가 채워지게 된다.Next, as shown in FIG. 2D, a photoresist pattern PR2 to be used as a trench mask is formed on the oxide layer 27 on the second etching barrier layer 24. In this case, the photoresist PR3 is filled to the height of the first etching barrier layer 24 in the via to prevent the etching.
이어서 도2e에 도시한 바와 같이 산화막(27), 제2 식각장벽막(26), 제2 저유전막(25)을 선택적으로 식각하여 제1 식각장벽막(24)의 상부면 일부를 노출시키는 트렌치를 형성하고, 트렌치 마스크로 이용된 포토레지스트 패턴(PR2) 및 비아 내부의 포토레지스트(PR3)를 제거한다. 이러한 식각과정에서 포토레지스트(PR3)로 덮여있던 산화막(27)은 제거되지 않고 제1 식각장벽막(24) 및 제1 저유전막(23) 측벽에 스페이서(27A) 형태로 잔류한다.Next, as shown in FIG. 2E, a trench for selectively etching the oxide film 27, the second etching barrier film 26, and the second low dielectric film 25 to expose a portion of the upper surface of the first etching barrier film 24. Is formed, and the photoresist pattern PR2 and the photoresist PR3 inside the via are removed. In this etching process, the oxide layer 27 covered with the photoresist PR3 is not removed and remains on the sidewalls of the first etching barrier layer 24 and the first low dielectric layer 23 in the form of a spacer 27A.
다음으로 도2f에 도시한 바와 같이 보호용 절연막(22) 제거를 위한 식각 공정을 실시하여 금속막 패턴(21)을 노출시킨다.Next, as illustrated in FIG. 2F, an etching process for removing the protective insulating film 22 is performed to expose the metal film pattern 21.
이후 비아 및 트렌치 내부에 전도막을 채워 금속막 패턴(21)과 연결시킨다.Thereafter, a conductive film is filled in the via and the trench to be connected to the metal layer pattern 21.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 저유전막을 이용한 쌍상감 구조 형성에 있어서 포토레지스트 패턴 형성 및 제거, 세정 등의 공정에 저유전막이 산소에 노출되는 것을 억제할 수 있다 또한, 금속막 상의 보호절연막을 제거하는 과정에서 식각장벽막 및 저유전막 측벽에 잔류하는 산화막은 저유전막이 손상되는 것을 방지할 수 있다.The present invention as described above can suppress the exposure of the low dielectric film to oxygen in the process of forming, removing, and cleaning the photoresist pattern in forming the dual phase structure using the low dielectric film. Also, the protective insulating film on the metal film is removed. The oxide film remaining on the etch barrier film and the low dielectric film sidewalls may prevent the low dielectric film from being damaged.
Claims (6)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100412195B1 (en) * | 2001-12-29 | 2003-12-24 | 주식회사 하이닉스반도체 | Method of forming a dual damascene pattern in a semiconductor device |
| KR100436770B1 (en) * | 2002-07-18 | 2004-06-23 | 주식회사 하이닉스반도체 | Method of forming a metal line in semiconductor device |
| KR100470197B1 (en) * | 2002-09-10 | 2005-02-05 | 동부아남반도체 주식회사 | Damascene method for reducing resistance of metal line |
| KR100824623B1 (en) * | 2006-12-05 | 2008-04-25 | 동부일렉트로닉스 주식회사 | Method for forming semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05211130A (en) * | 1992-01-27 | 1993-08-20 | Nec Corp | Manufacture of semiconductor device |
| JPH08330252A (en) * | 1995-05-29 | 1996-12-13 | Toshiba Corp | Manufacture of semiconductor device |
| KR100226250B1 (en) * | 1996-06-27 | 1999-10-15 | 김영환 | Semiconductor element metal line manufacturing method |
| KR100585069B1 (en) * | 1999-08-16 | 2006-05-30 | 삼성전자주식회사 | Method of Forming Dual Damascene Interconnection |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100412195B1 (en) * | 2001-12-29 | 2003-12-24 | 주식회사 하이닉스반도체 | Method of forming a dual damascene pattern in a semiconductor device |
| KR100436770B1 (en) * | 2002-07-18 | 2004-06-23 | 주식회사 하이닉스반도체 | Method of forming a metal line in semiconductor device |
| KR100470197B1 (en) * | 2002-09-10 | 2005-02-05 | 동부아남반도체 주식회사 | Damascene method for reducing resistance of metal line |
| KR100824623B1 (en) * | 2006-12-05 | 2008-04-25 | 동부일렉트로닉스 주식회사 | Method for forming semiconductor device |
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