KR20010018260A - Method for forming contact between devices - Google Patents
Method for forming contact between devices Download PDFInfo
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- KR20010018260A KR20010018260A KR1019990034133A KR19990034133A KR20010018260A KR 20010018260 A KR20010018260 A KR 20010018260A KR 1019990034133 A KR1019990034133 A KR 1019990034133A KR 19990034133 A KR19990034133 A KR 19990034133A KR 20010018260 A KR20010018260 A KR 20010018260A
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- conductive layer
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 claims description 14
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004541 SiN Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로 소자간의 콘택 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact between devices.
디자인 룰(design rule)이 0.2㎛ 이하로 작아짐에 따라 반도체 장치가 고집적화, 고용량화되고 소자의 크기가 점점 작아지고 있다. 따라서, 콘택홀(contact hole)의 크기가 줄어 콘택홀을 채워 콘택 플러그(contact plug)를 형성하는데 어려움이 있다. 또한, 미세한 폴리머(polymer)로 인한 도전막과 도전막 사이의 접촉 불량이 증대되고 있다. 그리고, 패턴이 밀한 영역과 소한 영역간의 상대적인 식각 차이, 콘택홀의 폭이 넓은 영역과 좁은 영역간의 상대적인 식각 차이로 생기는 로딩 효과(loading effect) 때문에 폭이 작은 콘택홀을 형성할 때 식각 불량이 생긴다. 이러한 이유들로 콘택 플러그 형성 후 상하 도전막 사이의 접촉 면적의 감소로 콘택 저항 증가라는 문제점이 발생한다.As design rules become smaller than 0.2 µm, semiconductor devices are becoming more integrated, higher in capacity, and smaller in size. Therefore, it is difficult to form a contact plug by filling in the contact hole by reducing the size of the contact hole. In addition, poor contact between the conductive film and the conductive film due to a fine polymer is increasing. In addition, an etch defect occurs when a contact hole having a small width is formed due to a loading effect caused by a relative etching difference between a dense and a small area of the pattern and a relative etching difference between a wide area and a narrow area of the contact hole. For these reasons, a problem arises in that contact resistance increases due to a decrease in the contact area between the upper and lower conductive films after the contact plug is formed.
이러한 문제점들을 해결하기 위한 방법으로 첫째, 콘택홀(contact hole) 형성 후 세정 공정을 통해 접촉 상태를 개선하는 방법이 있다. 그러나, 세정(cleaning) 공정시 도전막과 도전막 사이의 접촉을 좋게 하기 위한 목적과는 별개로 절연막의 식각을 유발하여 오히려 콘택 크기를 증가시키게 된다. 그러므로, 정렬 마진(align margin)을 축소시키는 역효과가 날 수 있다.As a method for solving these problems, first, there is a method of improving the contact state through a cleaning process after forming a contact hole. However, apart from the purpose of improving the contact between the conductive film and the conductive film during the cleaning process, the insulating film is etched to increase the contact size. Therefore, the adverse effect of reducing the alignment margin can be adversely affected.
둘째, 디자인 개선에 의한 접촉 면적을 증대시켜 콘택 저항(contact resistance)을 감소키는 방법이 있다. 그러나, 디자인 룰의 한계를 고려하지 않을 수 없고 주변 공정과의 미스 얼라인(miss align) 축소로 적용하는데 제약이 있다.Second, there is a method of reducing contact resistance by increasing the contact area due to design improvement. However, it is inevitable to consider the limitations of the design rule and apply it to reduce the misalignment with the surrounding process.
세째, 콘택 플러그(contact plug) 물질을 도핑된 폴리실리콘(doped poly-Si) 대신 도전성이 좋은 텅스텐(tungsten;W)을 사용하는 방법 등이 제시되고 있다. 그러나, 텅스텐 콘택 플러그 형성시 장벽 금속막(barrier metal layer)을 형성해야 하며 일정 크기 이상이 되어야만 증착이 가능하므로 종횡비(aspect ratio)가 커지는 시점에서는 적용하는데 확대되는 공정이 많이 추가되어 비용을 상승시키는 요소로 작용한다.Third, a method using tungsten (W) having high conductivity instead of doped poly-Si as a contact plug material has been proposed. However, when forming a tungsten contact plug, a barrier metal layer must be formed, and it can be deposited only when it is larger than a predetermined size. Therefore, when the aspect ratio is increased, an additional process that is expanded is added to increase the cost. Acts as an element
도 1은 종래의 버팅 콘택홀의 모습을 보여주는 단면도이다.1 is a cross-sectional view showing a state of a conventional butting contact hole.
도 1을 참조하면, 하부 도전막(110)과 중간 도전막(114)이 있는 버팅 콘택(butting contact)의 경우에 있어서, 버팅 콘택홀이 폭이 아래로 갈수로 좁아져 노출된 중간 도전막(114)과 하부 도전막(110) 각각의 표면적이 작다. 이로인해, 콘택 면적이 좁아지고 콘택 저항이 증가되는 문제가 더 심화된다.Referring to FIG. 1, in the case of a butting contact including the lower conductive layer 110 and the intermediate conductive layer 114, the intermediate conductive layer exposed by narrowing the width of the butting contact hole toward the bottom thereof ( 114 and the lower conductive film 110 each have a small surface area. This further exacerbates the problem of narrowing the contact area and increasing the contact resistance.
본 발명은 상술한 제반 문제를 해결하기 위해 제안된 것으로, 도전막과 콘택 플러그 사이의 유효 콘택 면적을 증가시켜 콘택 저항을 감소시키는 데 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems, and its object is to reduce the contact resistance by increasing the effective contact area between the conductive film and the contact plug.
도 1은 문제점이 있는 종래의 소자간 콘택 형성을 보여주는 단면도이다.1 is a cross-sectional view showing a conventional inter-element contact formation having a problem.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 소자간 콘택 형성 방법을 순차적으로 보여주는 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method for forming a device-to-device contact according to an exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
110, 210 : 하부 도전막 112, 212 : 제 1 절연막110 and 210: lower conductive film 112 and 212: first insulating film
114, 214 : 중간 도전막 116, 216 : 제 2 절연막114 and 214: intermediate conductive film 116 and 216: second insulating film
118, 218 : 버팅 콘택홀118, 218: Butting Contact Hole
상술한 문제를 해결하기 위한 본 발명에 의하면, 소자간 콘택 형성 방법은 제 1 도전막 상에 제 1 절연막과 제 2 도전막을 차례로 증착한다. 상기 제 1 도전막이 노출되도록 사진 공정을 통해 상기 제 2 도전막과 제 1 절연막을 패터닝한다. 상기 제 1 도전막 및 제 2 도전막 상에 제 2 절연막을 증착한다. 상기 제 2 도전막 및 제 1 도전막이 노출되도록 사진 공정을 통해 상기 제 2 절연막을 식각하여 버팅 콘택홀을 형성한다. 노출된 상기 제 1 도전막 및 제 2 도전막의 표면을 등방성 식각한다.According to the present invention for solving the above-described problem, in the inter-element contact forming method, the first insulating film and the second conductive film are sequentially deposited on the first conductive film. The second conductive film and the first insulating film are patterned through a photolithography process so that the first conductive film is exposed. A second insulating film is deposited on the first conductive film and the second conductive film. The second insulating layer is etched through the photolithography process so that the second conductive layer and the first conductive layer are exposed to form a butting contact hole. The exposed surfaces of the first conductive film and the second conductive film are isotropically etched.
(실시예)(Example)
이하 도 2a 내지 도 2d를 참조하여 본 발명의 실시예를 자세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2D.
본 발명의 신규한 소자간 콘택 형성 방법은 버팅 콘택홀이 형성된 후 건식 등방성 식각이 수행되므로 하부 도전막과 중간 도전막이 더 식각되어 노출된 각각의 도전막 표면이 울퉁불퉁한 요철 모양을 형성하므로 접촉면적이 증가되는 효과가 생긴다.In the novel inter-element contact forming method of the present invention, dry isotropic etching is performed after the butting contact hole is formed, so that the lower conductive film and the intermediate conductive film are etched more, so that the exposed surface of each conductive film forms an uneven concave-convex shape. This increases the effect.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 소자간 콘택 방법을 순차적으로 보여주는 단면도이다.2A through 2D are cross-sectional views sequentially illustrating an inter-device contact method according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 하부 도전막(210)이 형성된 반도체 기판 상에 제 1 절연막(212)이 증착된다. 상기 제 1 절연막(212) 상에 중간 도전막(214)이 증착된다. 상기 하부 도전막(210)과 중간 도전막(214)은 폴리실리콘 또는 도전성이 좋은 도핑된 폴리실리콘(doped poly-Si)이 사용될 수 있다. 상기 제 1 절연막(212)은 CVD(Chemical Vapor Deposition), 리플로우(reflow) 및 HDP(High Density Plasma) 방법 중 하나를 사용하여 SiO2, SiN, SiON, BPSG(Boron Phosphorus Silicate Glass), USG(Undoped Silicate Glass), HDP 산화막 및 이것들의 혼합 물질 등으로 형성될 수 있다.Referring to FIG. 2A, a first insulating layer 212 is deposited on a semiconductor substrate on which a lower conductive layer 210 is formed. An intermediate conductive layer 214 is deposited on the first insulating layer 212. The lower conductive layer 210 and the intermediate conductive layer 214 may be made of polysilicon or doped polysilicon having high conductivity. The first insulating layer 212 may be formed of SiO 2 , SiN, SiON, Boron Phosphorus Silicate Glass (BPSG), or USG using one of Chemical Vapor Deposition (CVD), Reflow, and High Density Plasma (HDP) methods. Undoped Silicate Glass), HDP oxide film, and a mixed material thereof.
도 2b를 보는 바와 같이, 상기 중간 도전막(214) 상에 포토레지스트막(도면에 미도시)이 증착된 후 패터닝(patterning)된다. 상기 포토레지스트 패턴 (pattern)을 마스크(mask)로 사용하여 상기 제 1 절연막(212)이 노출되도록 상기 중간 도전막(214)이 식각된다. 상기 중간 도전막(214)을 마스크로 사용하여 상기 하부 도전막(210)이 노출되도록 상기 제 1 절연막(212)이 식각된다. 상기 기판 전면에 제 2 절연막(216)이 증착된다. 상기 제 2 절연막(216)은 SiO2, SiN, SiON, BPSG(Boron Phosphorus Silicate Glass), USG(Undoped Silicate Glass), HDP(High Density Plasma) 산화막 등으로 형성된다.As shown in FIG. 2B, a photoresist film (not shown) is deposited on the intermediate conductive film 214 and then patterned. The intermediate conductive layer 214 is etched to expose the first insulating layer 212 using the photoresist pattern as a mask. The first insulating layer 212 is etched using the intermediate conductive layer 214 as a mask to expose the lower conductive layer 210. The second insulating layer 216 is deposited on the entire surface of the substrate. The second insulating layer 216 is formed of SiO 2 , SiN, SiON, Boron Phosphorus Silicate Glass (BPSG), Undoped Silicate Glass (USG), High Density Plasma (HDP) oxide, or the like.
도 2c를 참조하면, 상기 제 2 절연막(216) 상에 포토레지스트막(도면에 미도시)이 증착된 후 패터닝된다. 상기 포토레지스트 패턴은 상기 중간 도전막(214)과 하부 도전막(210)이 둘다 포함되는 영역 상에 정렬(align)되어야 한다. 상기 포토레지스트 패턴을 마스크로 사용하여 상기 중간 도전막(214)과 하부 도전막(210)이 노출되도록 상기 제 2 절연막(216)이 식각된다. 이로써, 버팅 콘택홀(butting contact hole, 218)이 형성된다.Referring to FIG. 2C, a photoresist film (not shown) is deposited on the second insulating film 216 and then patterned. The photoresist pattern should be aligned on an area including both the intermediate conductive layer 214 and the lower conductive layer 210. The second insulating layer 216 is etched using the photoresist pattern as a mask to expose the intermediate conductive layer 214 and the lower conductive layer 210. As a result, a butting contact hole 218 is formed.
도 2d를 참조하면, 마이크로 웨이브 소오스(micro wave source)를 채용한 설비에서 NF3및 O2기체 분위기에서 상기 버팅 콘택홀(218)에 노출된 상기 중간 도전막(214)과 하부 도전막(210)이 등방성 식각(isotropic etching)된다.2D, the intermediate conductive layer 214 and the lower conductive layer 210 exposed to the butting contact hole 218 in NF 3 and O 2 gas atmospheres in a facility employing a microwave source. ) Is isotropic etched.
상기 중간 도전막(214)과 하부 도전막(210)은 불순물을 포함한 폴리실리콘이기 때문에 내부적으로 밀도의 분포가 불균일한다. 또한, 등방성 식각의 특성이 수직 방향으로의 식각뿐만 아니라, 수평 방향으로의 식각이 진행된다. 그리고, 물리적 식각뿐만 아니라 식각 반응 기체에 의한 화학적 식각 성질도 강하다. 이러한, 성질로 상기 중간 도전막(214)과 하부 도전막(210)은 그 표면이 불균일하게 식각이 진행되고 먼저 식각된 곳의 식각이 더 심화된다. 이로써, 도 2d에 보는 바와 같이 노출된 상기 중간 도전막(214)과 하부 도전막(210) 표면이 울퉁불퉁한 요철 모양을 이루게 된다.Since the intermediate conductive layer 214 and the lower conductive layer 210 are polysilicon containing impurities, density distribution is internally uneven. In addition, not only the etching in the vertical direction but also the etching in the horizontal direction is characteristic of the isotropic etching. In addition, not only physical etching but also the chemical etching property by the etching reaction gas is strong. As a result, the intermediate conductive layer 214 and the lower conductive layer 210 are etched unevenly on the surfaces thereof, and the etching of the first etched portion is further deepened. As a result, as shown in FIG. 2D, the exposed surfaces of the intermediate conductive layer 214 and the lower conductive layer 210 form an uneven surface.
후속 공정으로 상기 버팅 콘택홀이 상부 도전막으로 채워져 버팅 콘택이 형성된다.In a subsequent process, the butting contact hole is filled with an upper conductive layer to form a butting contact.
이상에서, 본 발명에 따른 버팅 콘택의 콘택 면적 증대를 상기한 설명 및 도면에 따라 도시하였지만 이는 예를 들어 설명한 것에 불과하며 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 다양한 변화 및 변경이 가능함은 물론이다.In the above, although the contact area increase of the butting contact according to the present invention has been shown according to the above description and drawings, this is merely described, for example, and various changes and modifications are possible without departing from the technical spirit of the present invention. to be.
본 발명은 버팅 콘택홀을 형성한 후 등방성이 강한 건식 식각을 수행하므로 버팅 콘택홀 내의 도전막을 더 식각하여 표면을 요철이 있도록 거칠게 만들어 콘택 면적을 증가시키는 효과가 있다.According to the present invention, since the dry isotropic etching is performed after the formation of the butting contact hole, the conductive layer in the butting contact hole is further etched to roughen the surface so that the surface has irregularities, thereby increasing the contact area.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6596628B2 (en) * | 2001-04-06 | 2003-07-22 | Seiko Epson Corporation | Electrode pad in semiconductor device and method of producing the same |
| KR100642922B1 (en) * | 2004-03-17 | 2006-11-03 | 주식회사 하이닉스반도체 | Method of forming a contact in a semiconductor device |
| US7709369B2 (en) | 2006-11-03 | 2010-05-04 | Hynix Semiconductor Inc. | Method for forming a roughened contact in a semiconductor device |
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| KR101654144B1 (en) | 2016-04-04 | 2016-09-05 | 고영호 | Stick magnet block |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6596628B2 (en) * | 2001-04-06 | 2003-07-22 | Seiko Epson Corporation | Electrode pad in semiconductor device and method of producing the same |
| KR100642922B1 (en) * | 2004-03-17 | 2006-11-03 | 주식회사 하이닉스반도체 | Method of forming a contact in a semiconductor device |
| US7709369B2 (en) | 2006-11-03 | 2010-05-04 | Hynix Semiconductor Inc. | Method for forming a roughened contact in a semiconductor device |
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