KR20050091954A - Method for fabricating contact of semiconductor devices - Google Patents

Abstract

As semiconductor devices become smaller and smaller in the manufacture of semiconductor devices, there is a difficulty in forming contacts due to a lack of plug contacts and overlay margins when forming bit line contacts. In order to solve this problem, the present invention facilitates contact formation using an insulating layer having a different etching rate, and increases the contact area of the plug contact and the bit line contact with the same overlay margin by increasing the area of the plug contact. Can reduce the poor contact.

Description

Method for forming contact of semiconductor device {METHOD FOR FABRICATING CONTACT OF SEMICONDUCTOR DEVICES}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device. In particular, a plug contact for forming an undercut in a plug contact hole and filling a buried contact is formed using an insulating layer having a different etching rate, thereby contacting the plug contact and the bitline contact with the same overlay margin. The present invention relates to a method of forming a contact for a semiconductor device which increases the area and reduces contact defects with word lines, thereby simplifying the process and improving yield.

1A to 1C are cross-sectional views illustrating a method for forming a contact according to the prior art.

Referring to FIG. 1A, a planarized first insulating layer 20 is formed on a semiconductor substrate 10 having a word line 45, a plug contact 40 is formed in a cell region, and a second insulating layer is formed. .

Referring to FIG. 1B, the bit line contact hole 50 exposing the plug contact 40 in the cell region and the word line 45 in the peripheral circuit region is formed.

Referring to FIG. 1C, the bit line plug contact 60 and the bit line 65 filling the bit line contact hole 50 are formed.

In the method of manufacturing a bit line of a semiconductor device according to the related art, when a bit line contact hole is formed, a misalignment occurs as shown in FIG. 1B, and a nitride film on the word line is etched and perforated, causing a short circuit between the bit line contact and the word line. have. Therefore, as the size of the semiconductor device is reduced, the overlay margin between the bit line contact and the plug contact is insufficient, which exacerbates this problem.

According to the present invention, in order to secure an overlay margin, after forming a word line, an insulating layer having a different etching rate is stacked, an undercut is formed in a plug contact hole, and a plug contact is formed to fill the plug contact hole, thereby securing an overlay margin, and making a plug contact and a bit line. It is an object of the present invention to provide a method for forming a contact of a semiconductor device which increases the contact area of a contact and reduces contact failure with a word line, thereby simplifying the process and improving yield.

The present invention to achieve the above object, the present invention is a step of depositing a planarized first insulating film on the semiconductor substrate having a word line, and the second insulating film, the third insulating film on the first insulating film sequentially Forming a plug contact hole exposing a predetermined region of the semiconductor substrate by etching the third insulating film, the second insulating film, and the first insulating film; and forming the plug contact hole exposed through sidewalls of the contact hole. Forming an undercut under the third insulating film by forming a plug; forming a plug contact filling a plug contact hole including an undercut; forming a flattened fourth insulating film on an entire surface of the plug; Forming a bit line contact hole exposing a contact, a word line and a semiconductor substrate, and a bit line contact filling the bit line contact hole Characterized in that it comprises a step of forming a bit line connected with the bit line contacts.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are diagrams illustrating manufacturing processes of the semiconductor device according to the present invention.

Referring to FIG. 2A, the planarized first insulating layer 100 is deposited on the semiconductor substrate 70 including the word line 75.

Referring to FIG. 2B, the second insulating layer 200 and the third insulating layer 300 are sequentially formed on the first insulating layer 100. In this case, the second insulating film 200 may be formed of an insulating film having a faster etching rate than that of the first insulating film 100 and the third insulating film 300. More preferably, the first insulating film is formed of a BPSG film, the second insulating film is formed of a PSG film or a PE-USG film using a HDP oxide film.

Referring to FIG. 2C, a plug contact that exposes a predetermined region, for example, a source / drain region, of the semiconductor substrate 70 by etching the third insulating layer 300, the second insulating layer 200, and the first insulating layer 100. The hole 400 is formed. In this case, the etching process for forming the plug contact hole 400 may preferably use wet etching.

Referring to FIG. 2D, the second insulating layer 200 exposed through the sidewall of the plug contact hole 400 is etched to form an undercut 500 under the third insulating layer 300, and includes the undercut 500. A plug contact 600 filling the plug contact hole 400 is formed.

Referring to FIG. 2E, a planarized fourth insulating film 700 is formed on the entire surface.

Referring to FIG. 2F, a bit line contact hole 800 is formed in the cell region to expose the plug contact 600 and in the peripheral circuit region to expose the word line 75 and the semiconductor substrate. In this case, the bit line contact hole 800 may be performed on the cell and the peripheral circuit area, respectively, or simultaneously.

Referring to FIG. 2G, a bit line contact 900 filling the bit line with the contact hole 800 and a bit line 950 connected to the bit line contact 800 are formed.

According to the present invention, a plug contact hole, which is a problem when forming a plug contact according to the prior art, is formed in a small or small plug contact hole, thereby increasing plug contact resistance, thereby causing a defect in a semiconductor device or deteriorating stability of the semiconductor device. The reliability of the semiconductor device is improved and the reliability of the semiconductor device is improved by reducing the contact resistance by increasing the contact area between the plug contact and the bit line contact by facilitating the formation of the plug contact using the etching rate difference of the insulating film. It can improve the quality and contribute to the yield. In addition, in the present invention, forming the cell region and the peripheral circuit region which are mainly used in the conventional bit line contact formation can simplify the process by allowing the cell and the peripheral circuit to be formed at the same time. Formation of line contacts and bit lines can prevent shorting between problematic bit line contacts and word lines, and contribute to process simplification and yield improvement by securing more alignment margins with plug contacts.

1A-1C are cross-sectional views illustrating a method for forming a contact according to the prior art.

2A-2G are cross-sectional views illustrating a method for forming a contact according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 70: semiconductor substrate 20, 100: first insulating film

30, 200: second insulating film 300: third insulating film

700: fourth insulating film 40, 600: plug contact

50, 800: bit line contact hole 60, 900: bit line contact

65, 950: bit line 45, 75: word line

400: plug contact hole 500: undercut

Claims (5)

Depositing a planarized first insulating layer on the semiconductor substrate having a word line; Sequentially forming a second insulating film and a third insulating film on the first insulating film; Etching the third insulating layer, the second insulating layer, and the first insulating layer to form a plug contact hole exposing a predetermined region of the semiconductor substrate; Etching the second insulating layer exposed through the sidewall of the plug contact hole to form an undercut under the third insulating layer; Forming a plug contact filling a plug contact hole including an undercut; Forming a planarized fourth insulating film over the entire surface; Forming a bit line contact hole exposing the plug contact, the word line and the semiconductor substrate; And Forming a bit line contact filling the bit line contact hole and a bit line connected to the bit line contact; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The second insulating layer is a semiconductor device manufacturing method, characterized in that the etching speed is faster than the first insulating film and the third insulating film. The method according to any one of claims 1 and 2, The first insulating film is a BPSG film, the second insulating film is a PSG film or a PE-USG film, and the third insulating film is an HDP oxide film. The method of claim 1, The forming of the plug contact hole may include a wet etching process. The method of claim 1, The forming of the bit line contact holes may be performed on the cell and the peripheral circuit area, respectively, or simultaneously.