KR20090112925A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent device failure by preventing a short circuit of a word line and a buried bit line due to an excessive etching. CONSTITUTION: A method for manufacturing a semiconductor device is comprised of the steps: forming a vertical pillar on a semiconductor substrate(200); forming a gate electrode layer pattern(208) on the sidewall of the vertical pillar; forming the buried bit line(212) within the semiconductor substrate under the gate electrode layer; forming the first insulating layers filling up the gap between gate electrode layer patterns; forming an etch stop layer pattern(218a) on the surface of the first insulating layer and the gate electrode pattern; and forming a surround gate by etching the gate electrode layer pattern.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a word line of a memory cell including a vertical transistor.

Recently, in the case of semiconductor devices such as DRAMs, a technique for increasing the degree of integration by forming more transistors in a limited area is required. For this purpose, a vertical transistor technology capable of putting a memory cell element in a small area has been proposed. In the case of a memory device, the vertical transistor provides a surrounding gate structure surrounding the vertical channel.

This surround gate structure selectively isotropically etches the channel region to form at 4F2, making the channel region relatively thinner than the source / drain regions. In the surround gate structure, the front surface of the channel region may be surrounded by the gate electrode to maximize the control power of the gate. In addition, the surround gate structure provides excellent operating current characteristics due to the large current flow area as well as the short channel effect.

The present invention has the following object.

First, it is possible to prevent device defects by preventing the short circuit of the word line and the buried bit line electrically by the excessive etching that is involved in the interlayer insulating film etching process for the word line forming process by using the etch stop layer. .

Second, the selective oxidation process may be used to compensate for the interlayer insulating film lost by the excessive etching that is involved in the interlayer insulating film etching process for the word line forming process.

Method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a vertical filler on the semiconductor substrate; Forming a gate electrode layer pattern on sidewalls of the vertical pillars; Forming a buried bit line in the semiconductor substrate under the gate electrode layer pattern; Forming a first insulating film partially filling the gate electrode layer patterns; Forming an etch stop layer pattern on the gate electrode layer pattern and the surface of the first insulating layer; And forming a surround gate by etching the gate electrode layer pattern.

The method may further include forming a gate insulating layer on a surface of the vertical pillar and the semiconductor substrate after the vertical pillar forming step. The forming of the gate electrode layer pattern may include forming a gate electrode layer on the gate insulating layer. system; And etching the gate electrode layer until the gate insulating layer is exposed.

The buried bit line forming step may include forming a bit line impurity region in the semiconductor substrate between the gate electrode layer patterns; Forming a first nitride film on a surface of the gate electrode layer pattern; And etching the first nitride film and the semiconductor substrate by a photolithography process using a mask defining a bit line, wherein the etch stop layer pattern is formed to have the same thickness as that of the first nitride film. The insulating film may be formed higher than the bottom of the gate electrode layer pattern.

And forming an oxide film on the surface of the first insulating film using a selective oxidation process after the first insulating film forming step, wherein the etch stop layer pattern is selected from among a low pressure nitride film, a plasma nitride film, and a combination thereof. The etching stop layer pattern forming step may include forming an etch stop layer on the gate electrode layer pattern and the first insulating layer; Forming a second insulating layer on the etch stop layer to partially fill the gate electrode layer pattern; And etching the etch stop layer exposed by the second insulating layer.

The second insulating layer is formed to be lower than the upper side of the vertical pillar, the etching stop layer etching process is performed by a wet etching method, and after the surround gate forming step, the vertical portion above the surround gate. Forming a second nitride film on the type pillar side wall; Forming a third insulating film on the second nitride film and the second insulating film; Etching the third insulating film and the second insulating film to expose the second nitride film and the etch stop layer pattern; Removing the exposed second nitride layer and the etch stop layer pattern; Forming a conductive film on the surround gate and the first insulating film; And forming a word line by etching the conductive layer until the surround gate is exposed.

The present invention provides the following effects.

First, by preventing the short circuit of the word line and the buried bit line electrically by the excessive etching involved in the interlayer insulating film etching process for the word line forming process using the etch stop film to prevent device defects. .

Second, the selective oxidation process provides an effect of compensating for the interlayer insulating film lost by the excessive etching that is involved in the interlayer insulating film etching process for the word line forming process.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device.

Referring to FIG. 1A, a hard mask layer pattern 102 defining an active region is formed on the semiconductor substrate 100. Next, the semiconductor substrate 100 is etched using the hard mask layer pattern 102 as an etch mask to form a vertical pillar 104.

Next, a gate insulating layer 106 and a gate electrode layer (not shown) are formed on the hard mask layer pattern 102 and the vertical pillars 104. Here, the gate insulating film 106 is formed of an oxide film. Next, the gate electrode layer is etched entirely until the gate insulating layer 106 is exposed to form the gate electrode layer pattern 108 on the sidewalls of the vertical pillars 104. Next, an impurity is implanted into the semiconductor substrate 100 between the gate electrode layer patterns 108 to form the bit line impurity region 110.

Referring to FIG. 1B, a first nitride film 112 is formed on the gate insulating layer 106, the gate electrode layer pattern 108, and the semiconductor substrate 100. Next, a first oxide film (not shown) is formed on the first nitride film 112, and a photosensitive film pattern 114 defining a bit line is formed on the first oxide film. Next, the first oxide film, the first nitride film 112 and the semiconductor substrate 100 are etched using the photoresist pattern 114 as an etch mask to form a separate buried bit line 110a. Next, the photoresist pattern 114 is removed.

Referring to FIG. 1C, a second oxide film 116 is formed on the first nitride film 112 and the semiconductor substrate 100. Next, the second oxide film 116 is selectively etched so that the second oxide film 116 is lower than the upper side of the vertical filler 104. Here, the etching depth of the second oxide film 116 is adjusted according to the size of the surround gate 108a to be formed in a subsequent process. Next, the exposed first nitride film 112 and the gate electrode layer pattern 108 are etched to form the first nitride film pattern 112a and the surround gate 108a. In this case, the upper side of the vertical pillar 104 is defined as a source / drain region, and the lower side of the vertical pillar 104 in contact with the surround gate 108a is defined as a channel region.

Referring to FIG. 1D, a second nitride film (not shown) is formed on the gate insulating film 106 and the second oxide film 116. Next, the second nitride film is etched entirely until the gate insulating layer 106 is exposed to form the second nitride film pattern 118 on the sidewall of the vertical pillar 104. Next, a third oxide film 120 is formed on the second nitride film pattern 118 and the second oxide film 116 to fill the gap between the second nitride film pattern 118.

Referring to FIG. 1E, the third oxide film 120 and the second oxide film 116 are selectively etched so that the second oxide film 116 remains higher than the bottom of the surround gate 108a. At this time, the etching depth of the third oxide film 120 and the second oxide film 116 is adjusted according to the size of the word line to be formed in a subsequent process. Next, the exposed second nitride film pattern 118 and the first nitride film pattern 112a are removed.

Referring to FIG. 1F, a conductive film (not shown) is formed on the second oxide film 116, the first nitride film pattern 112a, the surround gate 108a, and the gate insulating film 106. Next, the conductive layer is selectively etched until the surround gate 108a is exposed to form the word line 122.

However, when the process is performed as described above, as shown in FIG. 1G, the gate is formed by the transient etching that is involved in the etching process of the second oxide film 120 and the first oxide film 116 to form the word line 122. When deeply etched to the lower portion of the insulating layer 106, a phenomenon A in which the word line 122 and the buried bit line 110a are electrically shorted may be caused.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, a hard mask layer pattern 202 defining an active region is formed on the semiconductor substrate 200. Next, the semiconductor substrate 200 is etched using the hard mask layer pattern 202 as an etch mask to form a vertical pillar 204.

Next, a gate insulating layer 206 and a gate electrode layer (not shown) are formed on the hard mask layer pattern 202 and the vertical pillar 204. Here, the gate insulating film 206 is preferably formed of an oxide film. Next, the gate electrode layer is etched entirely until the gate insulating layer 206 is exposed to form a gate electrode layer pattern 208 on the sidewall of the vertical pillar 204. Next, an impurity is implanted into the semiconductor substrate 200 between the gate electrode layer patterns 208 to form a bit line impurity region (not shown).

Next, a first nitride film 210 is formed on the gate insulating film 206, the gate electrode layer pattern 208, and the semiconductor substrate 200. Next, a first oxide film (not shown) is formed on the first nitride film 210. Next, the buried bit line 212 is formed by etching the first oxide layer, the first nitride layer 210, and the semiconductor substrate 200 by a photolithography process using a mask defining a bit line.

Subsequently, a second oxide film 214 is formed on the first nitride film 210 and the semiconductor substrate 200, and the second oxide film 214 is planarized and etched until the first nitride film 210 is exposed. Next, the second oxide layer 214 is etched by a photolithography process using a mask defining a word line to partially fill the gaps between the gate electrode layer patterns 208. Here, the etching depth of the second oxide film 214 is adjusted according to the size of the word line to be formed in a subsequent process, but it is preferable to etch the second oxide film 214 so that the second oxide film 214 remains higher than the bottom of the gate electrode layer pattern 208. . In addition, the etching process of the second oxide film 214 may be performed by a dry etching method. Next, the exposed first nitride film 210 is removed.

Referring to FIG. 2B, a third oxidation film 216 is formed on the surfaces of the first nitride film 210, the second oxide film 214, and the gate insulating film 206 by performing a selective oxidation process. In this case, the selective oxidation process may be performed to selectively oxidize only the oxide film and the nitride film to compensate for the loss caused by the excessive etching in the etching process of the second oxide film 214. Next, an etch stop film 218 is formed on the surfaces of the third oxide film 216 and the gate electrode layer pattern 208. The etch stop layer 218 may be formed of any one selected from a low pressure CVD nitride, a plasma enhanced CVD nitride, and a combination thereof. The etch stop layer 218 may be formed to have the same thickness as that of the first nitride layer 210.

Referring to FIG. 2C, the fourth oxide layer 220 is formed on the etch stop layer 218, and the fourth oxide layer 220 is planarized until the etch stop layer 218 is exposed. Next, the fourth oxide film 220 is etched to expose the etch stop layer 218 so that the fourth oxide film 220 is lower than the upper side of the vertical pillar 204. The etching process of the fourth oxide film 220 may be performed by a self alignment contact (SAC) process using a difference in etching selectivity between the fourth oxide film 220 and the etch stop layer 218.

Next, the etch stop layer 218 and the gate electrode layer pattern 208 are etched to form an etch stop layer pattern 218a and a surround gate 208a. Here, the etching stop layer 218 etching process is preferably performed by a wet etching method. In this case, an upper side of the vertical pillar 204 from which the gate electrode layer pattern 208 is removed is defined as a source / drain region, and a lower side of the vertical pillar 204 in contact with the surround gate 208a is defined as a channel region.

Next, a second nitride layer 222 is formed on the gate insulating layer 206, the etch stop layer pattern 218a, the fourth oxide layer 220, and the surround gate 208a. Subsequently, the entire surface of the second nitride layer 222 is etched until the gate insulating layer 206 is exposed. Next, a fifth oxide layer 224 is formed on the gate insulating layer 206, the second nitride layer 222, the fourth oxide layer 220, and the etch stop layer pattern 218a. Next, the fifth oxide film 224 is planarized etched until the second nitride film 222 is exposed.

Referring to FIG. 2D, the fifth oxide layer 224 and the fourth oxide layer 220 are etched to expose the second nitride layer 222 and the etch stop layer pattern 218a. In this case, the loss of the third oxide layer 216 and the second oxide layer 214 may be prevented by the etch stop layer pattern 218a to prevent the buried bit line 212 from being exposed. As a result, the short circuit of the word line and the buried bit line 212 formed in the subsequent process can be prevented.

Referring to FIG. 2E, the exposed second nitride layer 222 and the etch stop layer pattern 218a are removed. Next, a conductive film (not shown) is formed on the third oxide film 216, the surround gate 208a, and the gate insulating film 206. Next, the conductive film is etched until the surround gate 208a is exposed to form a word line 226.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (12)

Forming a vertical filler on the semiconductor substrate; Forming a gate electrode layer pattern on sidewalls of the vertical pillars; Forming a buried bit line in the semiconductor substrate under the gate electrode layer pattern; Forming a first insulating film partially filling the gate electrode layer patterns; Forming an etch stop layer pattern on the gate electrode layer pattern and the surface of the first insulating layer; And Etching the gate electrode layer pattern to form a surround gate Method of manufacturing a semiconductor device comprising a. The method of claim 1, further comprising forming a gate insulating film on a surface of the vertical pillar and the semiconductor substrate after the vertical pillar forming step. The method of claim 2, wherein the forming of the gate electrode layer pattern is performed. Forming a gate electrode layer on the gate insulating layer; And Etching the gate electrode layer until the gate insulating layer is exposed Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the buried bitline forming step is Forming a bit line impurity region in the semiconductor substrate between the gate electrode layer patterns; Forming a first nitride film on a surface of the gate electrode layer pattern; And Etching the first nitride film and the semiconductor substrate by a photolithography process using a mask defining a bit line Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein the etch stop layer pattern is formed to have the same thickness as that of the first nitride layer. The method of claim 1, wherein the first insulating layer is formed higher than a bottom of the gate electrode layer pattern. The method of claim 1, further comprising forming an oxide film on the surface of the first insulating film using a selective oxidation process after the first insulating film forming step. The method of claim 1, wherein the etch stop layer pattern is formed of a low pressure nitride film, a plasma nitride film, or a combination thereof. The method of claim 1, wherein the etching stop layer pattern forming step is Forming an etch stop layer on the gate electrode layer pattern and the first insulating layer; Forming a second insulating layer on the etch stop layer to partially fill the gate electrode layer pattern; And Etching the etch stop layer exposed by the second insulating layer Method of manufacturing a semiconductor device comprising a. 10. The method of claim 9, wherein the second insulating film is formed lower than the upper side of the vertical pillar. The method of claim 9, wherein the etching stop layer etching process is performed by a wet etching method. 10. The method of claim 9, wherein after the surround gate forming step Forming a second nitride film on a sidewall of the vertical pillar above the surround gate; Forming a third insulating film on the second nitride film and the second insulating film; Etching the third insulating film and the second insulating film to expose the second nitride film and the etch stop layer pattern; Removing the exposed second nitride layer and the etch stop layer pattern; Forming a conductive film on the surround gate and the first insulating film; And Etching the conductive layer until the surround gate is exposed to form a word line Method of manufacturing a semiconductor device further comprising.

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