KR101185951B1 - Method for manufacturing the semiconductor device - Google Patents

Method for manufacturing the semiconductor device Download PDF

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Publication number
KR101185951B1
KR101185951B1 KR1020110080609A KR20110080609A KR101185951B1 KR 101185951 B1 KR101185951 B1 KR 101185951B1 KR 1020110080609 A KR1020110080609 A KR 1020110080609A KR 20110080609 A KR20110080609 A KR 20110080609A KR 101185951 B1 KR101185951 B1 KR 101185951B1
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KR
South Korea
Prior art keywords
pattern
forming
semiconductor substrate
etching
conductive material
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KR1020110080609A
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Korean (ko)
Inventor
김도형
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110080609A priority Critical patent/KR101185951B1/en
Application granted granted Critical
Publication of KR101185951B1 publication Critical patent/KR101185951B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

An object of the present invention is to improve the characteristics of a semiconductor device by preventing IDD failure by suppressing an increase in the volume of the device isolation film resulting from the height of the landing plug contact.
A method of manufacturing a semiconductor device according to the present invention includes forming a trench by forming a pad pattern on an upper surface of a semiconductor substrate and then etching the semiconductor substrate using the pad pattern as an etch mask, and filling the active region by filling an insulating layer in the trench. Removing the pad pattern after forming a device isolation layer to be defined, forming a first pattern having a line shape in which the active region is exposed on the semiconductor substrate, and forming an upper portion of the semiconductor substrate between the first patterns Forming a conductive material, etching the first pattern and the conductive material to form a second pattern and the conductive pattern, and etching the semiconductor substrate using the second pattern and the conductive pattern as an etch mask to form a gate region. It characterized by comprising the step of forming.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device for forming a landing plug contact in a buried gate structure.

A semiconductor memory device includes a plurality of unit cells composed of capacitors and transistors, and double capacitors are used for temporarily storing data, and transistors use data of semiconductors whose electrical conductivity varies depending on the environment to transfer data between bit lines and capacitors. It is used to convey. A transistor is composed of three regions: a gate, a source, and a drain. Charge occurs between a source and a drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of semiconductor memory devices increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. As a result, the area of the active region is also reduced, making it difficult to pattern the active region of 30 nm or less.

In addition, as the line width of the gate is gradually reduced, the aspect ratio of the gate increases, thereby causing the gate to be leaked, and the overlay accuracy between the recess and the gate decreases. As a result, SAC margins are decreasing and SAC fail is increased. If the landing plug contact is made small in order to prevent the SAC fail, Rext is increased to cause a tWR fail. In addition to this problem, the direct short margin between the storage electrode contact and the bit line contact is also reduced in the 6F2 structure, which is a problem inevitably occurring in the layout. In order to solve this problem, a process of completely separating the storage electrode contact and the bit line contact by forming a self-aligned landing plug contact and damascene bit line has been proposed, but the height of the landing plug contact produced during the insulating film annealing process of the device isolation layer is proposed. There is a problem that an IDD fail occurs due to an increase in the volume of the insulating film.

An object of the present invention is to improve the characteristics of a semiconductor device by preventing IDD failure by suppressing an increase in the volume of the device isolation film resulting from the height of the landing plug contact.

A method of manufacturing a semiconductor device according to the present invention includes forming a trench by forming a pad pattern on an upper surface of a semiconductor substrate and then etching the semiconductor substrate using the pad pattern as an etch mask, and filling the active region by filling an insulating layer in the trench. Removing the pad pattern after forming a device isolation layer to be defined, forming a first pattern having a line shape in which the active region is exposed on the semiconductor substrate, and forming an upper portion of the semiconductor substrate between the first patterns Forming a conductive material, etching the first pattern and the conductive material to form a second pattern and the conductive pattern, and etching the semiconductor substrate using the second pattern and the conductive pattern as an etch mask to form a gate region. It characterized by comprising the step of forming.

Furthermore, after removing the pad pattern, the method may further include performing an annealing process on the device isolation layer.

The forming of the second pattern and the conductive pattern may include forming a line pattern intersecting the first pattern on the first pattern and the conductive material, and using the line pattern as an etch mask. And etching the conductive material.

Further, in the forming of the second pattern and the conductive pattern, the conductive pattern may be a landing plug contact, and after forming the gate region, further including filling a conductive material in the gate region to form a gate. Characterized in that.

The manufacturing method of the semiconductor device of the present invention provides the following effects.

First, it is not necessary to form a structure for forming the landing plug contact during the device isolation film forming process, and thus, an etching process for device isolation is easy, thereby providing an effect of securing the height of the landing plug contact.

Secondly, in forming an isolation trench, the volume of the insulating layer is suppressed from increasing in the annealing process of the insulating layer, thereby providing an effect of preventing IDD failing.

Third, since the landing plug contact can be formed using a buried gate hard mask, the problem of preventing the problem of reducing the height of the landing plug contact while removing the pad layer is conventionally provided.

1 to 7 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Hereinafter, an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention. 1 (b) to 7 (b) show a plan view. 1 (ii) to 7 (ii) are cross-sectional views showing cut planes taken along the line Y ′ of FIGS. 1 (i) to 7 (i), respectively. ) Are cross-sectional views showing cut planes taken along the line X-X 'in FIGS.

First, referring to FIG. 1, a pad nitride layer 110 and a hard mask layer (not shown) are formed on the semiconductor substrate 100. The pad nitride layer 110 is formed to a thickness of 800 to 1200Å, and serves as an etch stop layer when the device isolation layer is subsequently formed. The hard mask layer (not shown) may be formed of any one selected from an oxide film, a silicon oxynitride film, a polysilicon layer, a carbon layer, and a combination thereof.

The hard mask layer is patterned by a photolithography process using an exposure mask defining an active region to form a hard mask pattern (not shown) on the active region of the semiconductor substrate 100. The pad nitride layer 110 is etched using the hard mask pattern (not shown) as an etch mask, and then the hard mask pattern (not shown) is removed. Thereafter, the semiconductor substrate 100 is etched using the etched pad nitride layer 110 as an etch mask to form a device isolation trench.

Next, an insulating film is buried in the entire upper portion of the semiconductor substrate 100 including the device isolation trenches, and then the annealing process is performed. The planarization etching process is performed until the pad nitride layer 110 is exposed to form the device isolation layer 105. Here, the insulating film is formed of a material having excellent gap fill characteristics. For example, it may be formed of an SOD film. In this case, the omission of the polysilicon layer for forming the landing plug contact may be easily etched during the device isolation trench forming process, and a problem caused by an increase in the volume of the device isolation layer 105 may be prevented, for example, an IDD fail.

Referring to FIG. 2, the pad nitride layer 110 is removed to expose the active region 103 of the semiconductor substrate 100. In this case, a portion of the upper portion of the isolation layer 105 may also be removed to become the same height as the active region 103. An annealing process is performed on the exposed device isolation layer 105. When the annealing process is performed, the upper side of the insulating layer becomes harder and the densification becomes less toward the lower side. When the pad nitride layer 110 is removed, the upper part of the isolation layer 105 is removed, and thus the middle part of the insulating layer is exposed, so it is preferable to proceed with the annealing process again. Do. The annealing process is preferably performed for 50 to 70 minutes at a temperature of 800 ~ 1000 ℃ in N 2 gas atmosphere.

Referring to FIG. 3, a first hard mask layer (not shown) for forming a buried gate is formed on the semiconductor substrate 100 including the active region 103 and the device isolation layer 105. The first hard mask layer (not shown) is formed to a thickness of 800 ~ 1200Å, it may be formed of a nitride film. In addition, any one selected from a carbon layer, a silicon oxynitride film, and a combination thereof may be further formed on the first hard mask layer (not shown). In this case, since the height of the landing plug contact may be determined by the thickness of the first hard mask layer (not shown), it is easy to adjust the height of the landing plug contact to increase the overlap margin during subsequent bit line etching.

Next, a first hard mask layer (not shown) is etched by a photolithography process using a landing plug contact mask to form a first hard mask pattern 115. In this case, the first hard mask pattern 115 may be formed in a line shape (see FIG. 3B) in which the upper portion of the active region 103 is exposed.

Referring to FIG. 4, the conductive material 120 for the landing plug contact is formed on the entire surface including the first hard mask pattern 115. In this case, the landing plug contact conductive material 120 may be formed of a polysilicon layer. Subsequently, the planarization process is performed until the first hard mask pattern 115 is exposed to fill the landing plug contact conductive material 120 between the first hard mask patterns 115.

Referring to FIG. 5, after forming a hard mask layer over the entire surface including the landing plug contact conductive material 120 and the first hard mask pattern 115, photo etching is performed using an exposure mask defining a buried gate. As a result, the second hard mask pattern 125 is formed. The hard mask layer may use any one selected from a carbon layer, a silicon oxynitride film, and a combination thereof. For example, in the case of forming a stacked structure of the carbon layer and the silicon oxynitride film, the carbon layer is formed to a thickness of 2200 ~ 2700Å, the silicon oxynitride film is formed to a thickness of 200 ~ 400Å.

Referring to FIG. 6, the first hard mask pattern 115 and the landing plug contact conductive material 120 are etched using the second hard mask pattern 125 as an etch mask, and the active region 103 of the semiconductor substrate 100 is etched. ) Is further etched to form the buried gate region 130. In this case, as the buried gate region 130 is formed, the conductive material 120 for the landing plug contact becomes the respective landing plug contact 120a. The landing plug contact 120a is a basic structure for forming a damascene bit line, and when the landing plug contact 120a is not formed, the depth of the metal plug and cell junction regions of the bit line contact is deep, which may cause storage electrode degradation. Can be. Therefore, in this case, as the landing plug contact 120a is formed, the advantages of the existing storage electrode contact and the bit line structure can be maintained.

Referring to FIG. 7, an oxide film (not shown) is formed on the buried gate region 130. The oxide film is preferably formed to mitigate damage to the substrate surface generated during the buried gate region 130 etching process. Thereafter, a buried gate 135 is formed by filling a conductive material in the bottom of the buried gate region 130. The conductive material may be formed of tungsten.

As described above, a process of forming a landing plug contact in the form of a line after the annealing process of the device isolation layer insulating film is performed to prevent an increase in the volume of the device isolation insulating layer and to increase the contact area between the storage electrode contact and the active region. It can be secured.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

100 semiconductor substrate 103 active region
105: device isolation layer 110: pad nitride film
115: first hard mask pattern 120: conductive material for the landing plug contact
120a: landing plug contact 1 125: second hard mask pattern
130: buried gate region 135: buried gate

Claims (5)

Forming a trench on the semiconductor substrate and then etching the semiconductor substrate using the pad pattern as an etch mask to form a trench;
Filling an insulating layer in the trench to form an isolation layer defining an active region, and then removing the pad pattern;
Forming a first pattern having a line shape on the semiconductor substrate to expose the active region;
Forming a conductive material on the semiconductor substrate between the first patterns;
Etching the first pattern and the conductive material to form a second pattern and a conductive pattern; And
Etching the semiconductor substrate using the second pattern and the conductive pattern as an etch mask to form a gate region
And forming a second insulating film on the semiconductor substrate. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
After removing the pad pattern,
A method of manufacturing a semiconductor device, characterized in that it further comprises the step of performing an annealing process on the device isolation film. Claim 3 has been abandoned due to the setting registration fee. The method according to claim 1,
Forming the second pattern and the conductive pattern is
Forming a line pattern intersecting the first pattern on the first pattern and the conductive material; And
Etching the first pattern and the conductive material using the line pattern as an etching mask
Method of manufacturing a semiconductor device further comprising. Claim 4 has been abandoned due to the setting registration fee. The method according to claim 1,
In the forming of the second pattern and the conductive pattern,
The conductive pattern is a manufacturing method of a semiconductor device, characterized in that the landing plug contact. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 1,
After forming the gate region,
Embedding a conductive material in the gate region to form a gate
Method of manufacturing a semiconductor device further comprising.
KR1020110080609A 2011-08-12 2011-08-12 Method for manufacturing the semiconductor device KR101185951B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9916979B2 (en) 2016-04-25 2018-03-13 Samsung Electronics Co., Ltd. Methods for manufacturing a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9916979B2 (en) 2016-04-25 2018-03-13 Samsung Electronics Co., Ltd. Methods for manufacturing a semiconductor device
US10283360B2 (en) 2016-04-25 2019-05-07 Samsung Electronics Co., Ltd. Semiconductor device

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