KR20030058296A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR20030058296A KR20030058296A KR1020010088711A KR20010088711A KR20030058296A KR 20030058296 A KR20030058296 A KR 20030058296A KR 1020010088711 A KR1020010088711 A KR 1020010088711A KR 20010088711 A KR20010088711 A KR 20010088711A KR 20030058296 A KR20030058296 A KR 20030058296A
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- contact
- plug
- bit line
- forming
- insulating layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 특히 셀 크기가 매우 작은 고집적 반도체소자의 콘택 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact of a semiconductor device, and more particularly to a method for forming a contact of a highly integrated semiconductor device having a very small cell size.
종래기술에 의한 반도체소자의 콘택 형성방법을 일례로서 비트라인콘택 및 스토리지노드 콘택 형성방법을 도1 및 도2를 참조하여 다음에 설명한다. 도1은 종래기술에 따른 평면도이고, 도 2는 도 1의 A-A'선에 따른 공정 단면도이다.A method for forming a contact of a semiconductor device according to the prior art will be described below with reference to FIGS. 1 and 2 as an example of a bit line contact and a storage node contact. Figure 1 is a plan view according to the prior art, Figure 2 is a cross-sectional view along the line AA 'of FIG.
도 1에 도시된 바와 같이, 활성영역(ACT)을 노출시키는 제1마스크(MK1)을 이용하여 활성영역을 노출시키는 비트라인콘택(BLC)을 형성하고, 제2마스크(MK2)를 이용하여 스토리지노드콘택(SNC)을 형성한다.As illustrated in FIG. 1, the bit line contact BLC exposing the active region is formed using the first mask MK1 exposing the active region ACT, and the storage is formed using the second mask MK2. The node contact SNC is formed.
도 2a에 도시된 바와 같이, 반도체기판(11)에 소자간 격리를 위한 필드산화막(12)을 형성한 후, 반도체기판(11)의 활성영역상에 게이트산화막(13), 게이트전극(14), 캡절연막(15)을 형성한 후, 캡절연막(15), 게이트전극(14) 및 게이트산화막(13)을 동시에 패터닝하여 다수의 게이트패턴을 형성한다.As shown in FIG. 2A, after the field oxide film 12 is formed on the semiconductor substrate 11 for isolation between devices, the gate oxide film 13 and the gate electrode 14 are formed on the active region of the semiconductor substrate 11. After the cap insulation layer 15 is formed, a plurality of gate patterns are formed by simultaneously patterning the cap insulation layer 15, the gate electrode 14, and the gate oxide layer 13.
다음으로, 게이트패턴의 양측벽에 접하는 스페이서(16)을 형성한 후, 전면에 제1절연막(17)을 형성한 후, 제1절연막(17)을 식각하여 게이트패턴 사이의 반도체기판(11)의 활성영역을 노출시키는 제1콘택홀(도시 생략)을 형성한다.Next, after forming spacers 16 in contact with both sidewalls of the gate pattern, the first insulating layer 17 is formed on the entire surface, and the first insulating layer 17 is etched to form the semiconductor substrate 11 between the gate patterns. A first contact hole (not shown) is formed to expose the active region of the film.
다음으로, 제1콘택홀을 통해 반도체기판(11)의 활성영역에 연결되는 플러그(18a, 18b)를 형성한다. 이때, 플러그(18a,18b) 중 하나는 비트라인콘택플러그(18a)이고, 다른 하나는 스토리지노드콘택플러그(18b)이다.Next, plugs 18a and 18b connected to the active region of the semiconductor substrate 11 are formed through the first contact hole. At this time, one of the plugs 18a and 18b is a bit line contact plug 18a and the other is a storage node contact plug 18b.
도 2b에 나타낸 바와 같이, 전면에 제2절연막(19)을 증착한 후, 사진식각공정을 통해 제2절연막(19)을 선택적으로 식각하여 제2콘택홀(도시 생략)을 형성한 다음, 제2콘택홀을 통해 비트라인콘택플러그(18a)에 접속되는 비트라인(20)을 형성한다.As shown in FIG. 2B, after the second insulating layer 19 is deposited on the entire surface, the second insulating layer 19 is selectively etched through a photolithography process to form a second contact hole (not shown). The bit line 20 connected to the bit line contact plug 18a is formed through two contact holes.
도 2c에 도시된 바와 같이, 비트라인(20)을 포함한 전면에 제3절연막(21)을 형성하고 평탄화한 후, 제3절연막(21)과 제2절연막(19)을 사진식각공정을 통해 선택적으로 식각하여 스토리지노드콘택플러그(18b)의 표면을 노출시키는 제3콘택홀(22)을 형성한다. 이때, 제3콘택홀(22)은 통상적으로 스토리지노드콘택홀이라 한다.As shown in FIG. 2C, after the third insulating film 21 is formed and planarized on the entire surface including the bit line 20, the third insulating film 21 and the second insulating film 19 are selectively selected through a photolithography process. Etching to form a third contact hole 22 exposing the surface of the storage node contact plug 18b. In this case, the third contact hole 22 is commonly referred to as a storage node contact hole.
이후의 공정은 스토리지노드콘택플러그(18b)에 접속되는 스토리지노드를 형성하고 유전막과 플레이트노드를 형성하여 커패시터를 형성하는 것이다.The subsequent process is to form a storage node connected to the storage node contact plug 18b, and to form a dielectric film and a plate node to form a capacitor.
상기한 바와 같은 종래의 콘택 형성기술은 도 1을 참조하면, 노광기술만을 이용하여 콘택홀을 형성하므로 인접한 콘택홀 사이의 공간(x)이 좁은 부분으로 인해 노광기술에 한계가 있다. 따라서 콘택홀의 크기를 크게 하는 데에는 무리가 있다. 이에 따라 콘택 상부에 형성되는 구조물의 콘택에 대한 정렬마진(align margin)이 부족하게 되어 하지층과의 단락을 유발하므로 생산 적용이 문제시되고 있다. 또한, 이중 콘택을 사용할 경우에는 접촉면적이 작아지면서 계면가 저항이 커지는 문제가 발생한다.As described above, referring to FIG. 1, since the conventional contact forming technique forms a contact hole using only the exposure technique, the exposure technique is limited due to the narrow portion of the space x between adjacent contact holes. Therefore, it is unreasonable to increase the size of the contact hole. Accordingly, there is a lack of alignment margin (contact margin) for the contact of the structure formed on the upper contact causing a short circuit with the underlying layer is a production application problem. In addition, when the double contact is used, a problem arises in that the contact area becomes smaller and the interface becomes larger in resistance.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 차세대 반도체 제조기술에서 셀 크기의 축소에 따른 노광기술의 한계로 인한 인접 콘택홀간의 분리 공간을 노광 한계 이상으로 최소한으로 분리할 수 있도록 공정 마진을 확보하고, 특히 인로 인한 상기 콘택홀 상부에 형성되어지는 제2의 콘택에 대한 하지층과의 정렬마진을 최대로 확보함과 동시에 접촉면적을 넓히는데 적합한 반도체소자의 콘택 형성방법을 제공하는데 목적이 있다.The present invention is to solve the above problems, to secure a process margin to separate the separation space between adjacent contact holes to the minimum beyond the exposure limit in the next generation semiconductor manufacturing technology due to the limitation of the exposure technology due to the reduction of the cell size In particular, it is an object of the present invention to provide a method for forming a contact for a semiconductor device suitable for increasing the contact area and at the same time ensuring the maximum alignment margin with the underlying layer for the second contact formed on the contact hole due to phosphorus. have.
도1은 종래기술에 따른 반도체소자의 평면도,1 is a plan view of a semiconductor device according to the prior art,
도 2a 내지 도 2c는 도 1의 A-A'선에 따른 종래 반도체소자의 콘택 형성방법을 나타낸 공정순서 단면도,2A through 2C are cross-sectional views illustrating a process forming method of a conventional semiconductor device according to the line AA ′ of FIG. 1;
도 3은 본 발명의 실시예에 따른 콘택마스크를 도시한 평면도,3 is a plan view showing a contact mask according to an embodiment of the present invention;
도 4a 내지 도 4e는 본 발명에 의한 반도체소자의 콘택 형성방법을 나타낸 공정순서 단면도.4A to 4E are cross-sectional views of a process sequence showing a contact forming method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
31 : 반도체기판 32 : 필드산화막31 semiconductor substrate 32 field oxide film
33 : 게이트산화막 34 : 게이트전극33: gate oxide film 34: gate electrode
35 : 캡절연막 36 : 스페이서35 cap insulation film 36 spacer
37 : 제1절연막 38a : 비트라인콘택플러그37: first insulating film 38a: bit line contact plug
38b : 스토리지노드콘택플러그 39 : 폴리실리콘38b: storage node contact plug 39: polysilicon
40a : 비트라인콘택패드 40b : 스토리지노드콘택패드40a: Bitline contact pad 40b: Storage node contact pad
상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 게이트전극 및 게이트 캡절연막을 형성하는 단계와, 상기 게이트전극 측면에 측벽절연막 형성하는 단계, 기판 전면에 절연막을 증착하는 단계, 사진식각공정을 통해 상기 절연막을 식각하여 기판 소정부분을 노출시키는 제1콘택홀을 형성하는 단계, 상기 제1콘택홀 내부에 도전물질을 증착하여 콘택플러그를 형성하는 단계, 습식식각을 통해 상기 남아 있는 절연막을 일정부분 식각하고 게이트 캡절연막을 에치백하여 상기 콘택플러그 상부의 개구부를 가능한 한 최대로 확대시키는 단계, 상기 콘택플러그 상부의 개구부내에 도전물질을 증착하여 제1콘택플러그보다 면적이 큰 콘택 패드를 형성하는 단계, 기판 전면에 층간절연막을 형성하고 평탄화시키는 단계 및 사진식각공정을 통해 상기 층간절연막을 선택적으로 식각하여 상기 콘택패드 상부에 콘택패드 표면을 노출시키는 제2콘택홀을 형성하는 단계를 포함하여 구성된 것을 특징으로한다.According to an aspect of the present invention, a gate electrode and a gate cap insulating film are formed on a semiconductor substrate, a sidewall insulating film is formed on a side of the gate electrode, an insulating film is deposited on the entire surface of the substrate, and a photolithography process is performed. Forming a first contact hole through which the insulating layer is etched to expose a predetermined portion of the substrate; depositing a conductive material in the first contact hole to form a contact plug; and wetting the remaining insulating layer by wet etching. Partially etching and etching back the gate cap insulating layer to maximize the opening of the upper portion of the contact plug as much as possible, and depositing a conductive material in the opening of the upper portion of the contact plug to form a contact pad having a larger area than the first contact plug. Forming, planarizing and forming an interlayer insulating film over the entire surface of the substrate; That by selectively etching the insulating film is configured by forming a second contact hole for exposing the contact pads on the upper surface of the contact pad is characterized.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도 3은 본 발명의 실시예에 따른 반도체소자의 평면도로서, 콘택마스크를 도시하고 있다.3 is a plan view of a semiconductor device according to an embodiment of the present invention and shows a contact mask.
도 3을 참조하면, 넓어진 비트라인콘택패드마스크(MK12)의 면적만큼 비트라인콘택플러그마스크(MK11)와 비트라인콘택(BLC)의 정렬마진이 확보되며, 또한, 확대된 스토리지노드콘택패드마스크(MK22)의 면적만큼 스토리지노드콘택플러그마스크 (MK21)와 스토리지노드콘택(SNC)의 정렬마진이 확보된다.Referring to FIG. 3, the alignment margin of the bit line contact plug mask MK11 and the bit line contact BLC is secured by the area of the wider bit line contact pad mask MK12, and the enlarged storage node contact pad mask ( Alignment margin between the storage node contact plug mask MK21 and the storage node contact SNC is secured by the area of MK22.
도4a 내지 도 4e에 본 발명의 일실시예에 의한 반도체소자의 비트라인 콘택 및 스토리지노드 콘택 형성방법을 공정순서에 따라 단면도로 나타내었다. 도4는 도3e에 따른 평면도이다.4A through 4E are cross-sectional views illustrating a method of forming a bit line contact and a storage node contact of a semiconductor device according to an embodiment of the present invention. 4 is a plan view according to FIG. 3E.
먼저, 도4a에 나타낸 바와 같이 반도체기판(31)에 소자간 격리를 위한 필드산화막(32)을 형성한 후, 반도체기판(31)의 활성영역상에 게이트산화막(33), 게이트전극(34), 캡절연막(35)을 형성한 후, 캡절연막(35), 게이트전극(34) 및 게이트산화막(33)을 동시에 패터닝하여 다수의 게이트패턴을 형성한다.First, as shown in FIG. 4A, a field oxide film 32 is formed on the semiconductor substrate 31 for isolation between devices, and then the gate oxide film 33 and the gate electrode 34 are formed on the active region of the semiconductor substrate 31. After the cap insulation layer 35 is formed, a plurality of gate patterns are formed by simultaneously patterning the cap insulation layer 35, the gate electrode 34, and the gate oxide layer 33.
다음으로, 게이트패턴의 양측벽에 접하는 스페이서(36)을 형성한 후, 전면에 제1절연막(37)을 형성한 후, 제1절연막(37)을 식각하여 게이트패턴 사이의 반도체기판(31)의 활성영역을 노출시키는 제1콘택홀(도시 생략)을 형성한다.Next, after forming spacers 36 in contact with both side walls of the gate pattern, the first insulating layer 37 is formed on the entire surface, and the first insulating layer 37 is etched to form the semiconductor substrate 31 between the gate patterns. A first contact hole (not shown) is formed to expose the active region of the film.
다음으로, 제1콘택홀을 포함한 전면에 폴리실리콘을 증착한 후, 폴리실리콘을 에치백하되 캡절연막(35) 하부까지 과도에치백시켜 반도체기판(31)의 활성영역에 연결되는 플러그(38a, 38b)를 형성한다. 이때, 플러그(38a,38b) 중 하나는 비트라인콘택플러그(38a)이고, 다른 하나는 스토리지노드콘택플러그(38b)이다.Next, after the polysilicon is deposited on the entire surface including the first contact hole, the polysilicon is etched back but excessively etched back to the lower portion of the cap insulation layer 35 to connect the plug 38a to the active region of the semiconductor substrate 31. 38b). At this time, one of the plugs 38a and 38b is a bit line contact plug 38a and the other is a storage node contact plug 38b.
다음에 도4b에 나타낸 바와 같이, 인접한 비트라인콘택플러그(38a)와 스토리지노드콘택플러그(38b)간의 공간이 최소가 되도록 습식식각을 통해 상기 제1절연막(37)을 식각하고 캡절연막(35)을 에치백하여 상기 비트라인콘택플러그(38a) 및 스토리지노드콘택플러그(38b)의 상부 개구부를 최대로 확대시킨다.Next, as shown in FIG. 4B, the first insulating layer 37 is etched through wet etching to minimize the space between the adjacent bit line contact plugs 38a and the storage node contact plugs 38b. The upper openings of the bit line contact plug 38a and the storage node contact plug 38b are maximally enlarged by etching back.
도 4c에 나타낸 바와 같이, 상기와 같이 확대된 콘택 상부 개구부가 충분히 매립될 수 있는 두께로 전면에 폴리실리콘(39)을 증착한 후, CMP공정을 이용하여 상기 폴리실리콘(39)을 각각의 콘택별로 분리하여, 도4d에 나타낸 바와 같이, 비트라인콘택플러그(38a)와 스토리지노드콘택플러그(38b) 상부에 비트라인콘택플러그(38a)와 스토리지노드콘택플러그(38b)보다 면적이 확대된 비트라인콘택패드(40a) 및 스토리지노드콘택패드(40b)를 각각 형성한다.As shown in FIG. 4C, after the polysilicon 39 is deposited on the front surface to a thickness such that the enlarged contact upper opening may be sufficiently buried, the polysilicon 39 is contacted with each other using a CMP process. As shown in FIG. 4D, the bit line having a larger area than the bit line contact plug 38a and the storage node contact plug 38b is disposed on the bit line contact plug 38a and the storage node contact plug 38b. The contact pads 40a and the storage node contact pads 40b are formed, respectively.
다음에 도4e에 나타낸 바와 같이 기판 전면에 제2절연막(41)을 형성하고 평탄화한 후, 사진식각공정을 통해 소정패턴으로 패터닝하여 상기 비트라인 콘택패드(40a)를 노출시키는 제2콘택홀을 형성한 다음, 이 제2콘택홀이 매립되도록 도전물질을 증착하고, 그위에 비트라인 형성용 도전층을 증착한 후, 소정의 비트라인 패턴으로 패터닝하여 상기 비트라인콘택패드(40a)와 연결되는 비트라인(42)을 형성한다.Next, as shown in FIG. 4E, the second insulating layer 41 is formed on the entire surface of the substrate and planarized, and then patterned into a predetermined pattern through a photolithography process to expose the second contact hole 40a. After the formation, the conductive material is deposited to fill the second contact hole, and the conductive layer for forming a bit line is deposited thereon, and then patterned into a predetermined bit line pattern to be connected to the bit line contact pad 40a. The bit line 42 is formed.
이때, 비트라인콘택플러그(38a) 상부에 면적이 큰 비트라인콘택패드(40a)가 형성되어 있기 때문에 비트라인(42) 형성시 정렬마진이 증가하며, 비트라인(42) 형성을 위한 식각공정시 충분히 과도식각할 수 있으므로 콘택간 접촉면적을 증가시킬 수 있다. 이어서 기판 전면에 제3절연막(43)을 형성하고 평탄화시킨다.At this time, since the bit line contact pad 40a having a large area is formed on the bit line contact plug 38a, the alignment margin increases when the bit line 42 is formed, and during the etching process for forming the bit line 42. It can be sufficiently overetched to increase the contact area between contacts. Subsequently, a third insulating layer 43 is formed on the entire surface of the substrate and planarized.
다음에 사진식각공정을 통해 상기 제3절연막(43)과 제2절연막(41)을 선택적으로 식각하여 상기 스토리지노드콘택패드(40b) 표면을 노출시키는 스토리지노드 콘택홀(44)을 형성한다. 이후 이 스토리지노드 콘택홀(44)내에 커패시터를 형성하는 공정을 진행한다. 상기 스토리지노드콘택홀(44)의 경우에도 스토리지노드콘택플러그(38b) 상부에 면적이 큰 스토리지노드콘택패드(40b)가 형성되어 있기 때문에 스토리지노드 콘택홀(44) 형성시 정렬마진이 증가하며, 스토리지노드 콘택홀 형성을 위한 식각공정시 충분히 과도식각할 수 있으므로 스토리지노드콘택패드(40b)와 스토리지노드간 접촉면적을 증가시킬 수 있다.Next, the third insulating layer 43 and the second insulating layer 41 are selectively etched through a photolithography process to form a storage node contact hole 44 exposing the surface of the storage node contact pad 40b. Thereafter, a process of forming a capacitor in the storage node contact hole 44 is performed. In the case of the storage node contact hole 44, since the storage node contact pad 40b having a large area is formed on the storage node contact plug 38b, the alignment margin increases when the storage node contact hole 44 is formed. In the etching process for forming the storage node contact hole, the substrate may be sufficiently over-etched to increase the contact area between the storage node contact pad 40b and the storage node.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 제1의 콘택을 형성한 후 제2의 콘택 형성시 최대의 정렬마진을 확보할 수 있도록 제1의 콘택홀을 형성한 다음에 습식식각 및 에치백을 이용하여 층간절연막을 식각하여 하지층의 플러그 상부 개구부의 면적을 확대시키고 패드를 형성함으로써 노광 한계를 극복할 수 있다. 또한, 콘택간 오정렬에 의한 콘택저항의 증가를 억제할 수 있으며, 랜딩 플러그 에치백공정시 과도식각에 의한 마진도 증가되며, 콘택간 콘택저항도 낮출 수 있다.According to the present invention, after forming the first contact, the first contact hole is formed to secure the maximum alignment margin when the second contact is formed, and then the interlayer insulating layer is etched by using wet etching and etch back. Exposure limits can be overcome by enlarging the area of the plug upper opening of the layer and forming the pad. In addition, an increase in contact resistance due to misalignment between contacts can be suppressed, a margin due to excessive etching during a landing plug etch back process can be increased, and contact resistance can be lowered.
Claims (10)
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| KR1020010088711A KR20030058296A (en) | 2001-12-31 | 2001-12-31 | Method for forming contact of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8580669B2 (en) | 2010-01-08 | 2013-11-12 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8580669B2 (en) | 2010-01-08 | 2013-11-12 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| US9082755B2 (en) | 2010-01-08 | 2015-07-14 | SK Hynix Inc. | Semiconductor device having multi-layered bit line contact |
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