KR100527573B1 - Method for forming a contact hole - Google Patents
Method for forming a contact hole Download PDFInfo
- Publication number
- KR100527573B1 KR100527573B1 KR10-2000-0083844A KR20000083844A KR100527573B1 KR 100527573 B1 KR100527573 B1 KR 100527573B1 KR 20000083844 A KR20000083844 A KR 20000083844A KR 100527573 B1 KR100527573 B1 KR 100527573B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- forming
- film
- layer
- photoresist
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 33
- 229920000642 polymer Polymers 0.000 claims abstract description 17
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 15
- 239000010410 layer Substances 0.000 abstract description 52
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000004804 winding Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 콘택홀 형성 방법에 관한 것으로, 특히 콘택홀 형성을 위한 감광막 패턴(Pattern) 표면에 식각 보호막으로 폴리머(Polymer)층을 형성한 후 반사방지막과 층간 절연막을 선택 식각하여 콘택홀을 형성하므로, 콘택홀 형성 공정시 콘택 탑 CD 와이더닝(Contact Top CD Widening)의 발생을 방지하여 후속 공정에서 형성될 비트 라인이 상기 콘택홀을 커버(Cover)하므로 쇼트(Short) 방지 및 소자의 수율 및 신뢰성을 향상시키는 특징이 있다.The present invention relates to a method of forming a contact hole, and in particular, after forming a polymer layer as an etch protective film on the surface of the photoresist pattern for forming the contact hole, the antireflection film and the interlayer insulating film are selectively etched to form contact holes. In the contact hole forming process, contact top CD widening is prevented from occurring so that the bit line to be formed in a subsequent process covers the contact hole to prevent short and yield and reliability of the device. There is a feature to improve.
Description
본 발명은 콘택홀 형성 방법에 관한 것으로, 특히 콘택홀 형성을 위한 감광막 패턴(Pattern) 표면에 식각 보호막으로 폴리머(Polymer)층을 형성한 후 콘택홀을 형성하여 쇼트(Short) 방지 및 소자의 수율 및 신뢰성을 향상시키는 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a contact hole, and in particular, after forming a polymer layer as an etch protective layer on a surface of a photoresist pattern for forming a contact hole, forming a contact hole to prevent short and yield of a device. And a contact hole forming method for improving reliability.
종래의 콘택홀 형성 방법은 도 1a에서와 같이, 반도체 기판(11) 상에 다수개의 워드 라인(Word line)(12)들을 형성한다.The conventional contact hole forming method forms a plurality of word lines 12 on the semiconductor substrate 11 as shown in FIG. 1A.
그리고, 상기 워드 라인(12)들을 포함한 전면에 질화막(13)을 형성한 후, 상기 질화막(13)상에 층간 절연막인 제 1 비피에스지(Boron Phosphor Silicate Glass: BPSG)층(14)을 형성한다.After the nitride film 13 is formed on the entire surface including the word lines 12, the first BPSG layer 14, which is an interlayer insulating film, is formed on the nitride film 13. .
도 1b에서와 같이, 상기 제 1 BPSG층(14)상에 제 1 감광막을 도포하고, 상기 제 1 감광막을 비트 라인(Bit line) 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1B, a first photoresist film is coated on the first BPSG layer 14, and the first photoresist film is selectively exposed and developed to be removed only at a portion where a bit line contact is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 BPSG층(14)을 선택 식각한 후, 상기 제 1 감광막을 제거한다.The first BPSG layer 14 is selectively etched using the selectively exposed and developed first photoresist layer, and then the first photoresist layer is removed.
이어, 상기 제 1 BPSG층(14)을 마스크로 상기 질화막(13)을 에치백(Etch-back)하여 제 1 콘택홀(15)을 형성하고 상기 노출된 워드 라인(12) 일측의 반도체 기판(11) 상에 질화막 스페이서(13a)를 형성한다.Subsequently, the nitride layer 13 is etched back using the first BPSG layer 14 as a mask to form a first contact hole 15 and the semiconductor substrate on one side of the exposed word line 12 ( 11) The nitride film spacer 13a is formed on it.
도 1c에서와 같이, 상기 제 1 콘택홀(15)을 포함한 전면에 다결정 실리콘층을 형성한 후, 상기 제 1 BPSG층(14)을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 다결정 실리콘층을 평탄 식각하여 플러그층(16)을 형성한다.As shown in FIG. 1C, after the polycrystalline silicon layer is formed on the entire surface including the first contact hole 15, the polycrystalline silicon layer is flattened by a chemical mechanical polishing method using the first BPSG layer 14 as an etching end point. By etching, the plug layer 16 is formed.
도 1d에서와 같이, 상기 워드 라인(12)들을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 질화막(13), 제 1 BPSG층(14) 및 플러그층(16)을 평탄 식각한다.As shown in FIG. 1D, the nitride film 13, the first BPSG layer 14, and the plug layer 16 are etched flat by the chemical mechanical polishing method with the word lines 12 as an etching end point.
그리고, 전면에 제 2 BPSG층(17), 반사방지막(18) 및 제 2 감광막(19)을 순차적으로 형성하고, 상기 제 2 감광막(19)을 비트 라인 콘택이 형성될 부위에민 남도록 선택적으로 노광 및 현상한다.A second BPSG layer 17, an antireflection film 18, and a second photoresist film 19 are sequentially formed on the front surface, and the second photoresist film 19 is selectively left to remain at a portion where a bit line contact is to be formed. Exposure and development.
도 1e에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(19)을 마스크로 상기 반사방지막(18)을 선택 식각한다.As shown in FIG. 1E, the anti-reflection film 18 is selectively etched using the selectively exposed and developed second photosensitive film 19 as a mask.
이때 상기 반사방지막(18)의 식각 공정시, 상기 제 2 감광막(19)은 반사방지막(18)과의 식각 선택비가 없기 때문에 상기 제 2 감광막(19)도 식각되어 탑 CD 와이더닝(Top CD Widening)이 발생된다.At this time, during the etching process of the anti-reflection film 18, since the second photosensitive film 19 has no etching selectivity with the anti-reflection film 18, the second photosensitive film 19 is also etched to Top CD Widening ) Is generated.
그리고, 상기 제 2 감광막(19)과 반사방지막(18)을 마스크로 상기 제 2 BPSG층(17)을 선택 식각하여 제 2 콘택홀(20)을 형성한 다음, 상기 제 2 감광막(19)과 반사방지막(18)을 제거한다.The second BPSG layer 17 is selectively etched using the second photoresist 19 and the antireflection film 18 as a mask to form a second contact hole 20, and then the second photoresist 19 The antireflection film 18 is removed.
여기서, 상기 제 2 콘택홀(20) 형성 공정시 상기 제 2 감광막(19)과 반사방지막(18)의 프로파일(Profile)에 영향을 받아 상기 제 2 BPSG층(17)에 콘택 탑 CD 와이더닝(Contact Top CD Widening)이 발생된다.Here, in the process of forming the second contact hole 20, a contact top CD winding on the second BPSG layer 17 may be influenced by the profile of the second photoresist 19 and the antireflection film 18. Contact Top CD Widening occurs.
도 2a에서와 같이, 상기 제 2 콘택홀(20)에 콘택 탑 CD 와이더닝이 발생되어 도 2b에서와 같이, 후속 공정에서 형성될 비트 라인(B)이 상기 제 2 콘택홀(20)을 커버(Cover)하지 못한다.As shown in FIG. 2A, a contact top CD widing is generated in the second contact hole 20 so that the bit line B to be formed in a subsequent process as shown in FIG. 2B covers the second contact hole 20. Can't Cover
그러나 종래의 콘택홀 형성 방법은 한 층의 층간 절연막과 반사방지막을 형성한 후 콘택홀 형성을 위한 감광막 패턴을 형성하므로, 콘택홀 형성 공정시 상기 층간 절연막에 콘택 탑 CD 와이더닝이 발생되어 상기 콘택홀의 면적이 증가하기 때문에, 후속 공정에서 형성될 비트라인이 상기 콘택홀을 커버(Cover)하지 못하여 쇼트 발생 및 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다. However, the conventional contact hole forming method forms a photoresist pattern for forming a contact hole after forming a layer interlayer insulating film and an antireflection film, and thus, contact top CD widing occurs in the interlayer insulating film during the contact hole forming process. Since the area of the hole increases, the bit line to be formed in a subsequent process does not cover the contact hole, causing short-circuit and yield and reliability of the device.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 콘택홀 형성을 위한 감광막 패턴 표면에 식각 보호막으로 폴리머층을 형성한 후 반사방지막과 층간 절연막을 선택 식각하여 콘택홀을 형성하므로, 콘택홀 형성 공정시 콘택 탑 CD 와이더닝의 발생을 방지하여 후속 공정에서 형성될 비트라인이 상기 콘택홀을 커버하는 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems, and after forming a polymer layer as an etch protective film on the surface of the photoresist pattern for forming the contact hole, the contact hole is formed by selectively etching the antireflection film and the interlayer insulating film, thereby forming a contact hole. It is an object of the present invention to provide a method for forming a contact hole in which a bit line to be formed in a subsequent process covers the contact hole by preventing occurrence of contact top CD widing.
본 발명의 콘택홀 형성 방법은 플러그층을 갖는 하부 구조물상에 BPSG층, 반사방지막 및 감광막을 순차적으로 형성하는 단계와, 상기 플러그층 상측의 감광막을 현상하는 단계와, 상기 감광막 표면에 폴리머층을 형성하는 단계와, 상기 감광막을 마스크로 반사방지막과 BPSG층을 선택 식각하여 콘택홀을 형성하는 단계와, 상기 폴리머층, 감광막 및 반사방지막을 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.The contact hole forming method of the present invention comprises the steps of sequentially forming a BPSG layer, an anti-reflection film and a photoresist film on the lower structure having a plug layer, developing the photoresist film on the upper side of the plug layer, and a polymer layer on the surface of the photoresist film And forming a contact hole by selectively etching the anti-reflection film and the BPSG layer using the photoresist as a mask, and removing the polymer layer, the photoresist and the anti-reflection film.
상기와 같은 본 발명에 따른 콘택홀 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for forming a contact hole according to the present invention as follows.
도 3a 내지 도 3f는 본 발명의 실시 예에 따른 콘택홀 형성 방법을 나타낸 공정 단면도이고, 도 4a와 도 4b는 본 발명의 실시 예에 따른 콘택홀과 비트 라인을 나타낸 사진도이다.3A to 3F are cross-sectional views illustrating a method of forming a contact hole according to an exemplary embodiment of the present invention, and FIGS. 4A and 4B are photographs illustrating a contact hole and a bit line according to an exemplary embodiment of the present invention.
본 발명의 실시 예에 따른 콘택홀 형성 방법은 도 3a에서와 같이, 반도체 기판(31) 상에 다수개의 워드 라인(32)들을 형성한다.In the method for forming a contact hole according to the embodiment of the present invention, as shown in FIG. 3A, a plurality of word lines 32 are formed on the semiconductor substrate 31.
그리고, 상기 워드 라인(32)들을 포함한 전면에 질화막(33)을 형성한 후, 상기 질화막(33)상에 층간 절연막인 제 1 BPSG층(34)을 형성한다.After the nitride film 33 is formed on the entire surface including the word lines 32, the first BPSG layer 34, which is an interlayer insulating film, is formed on the nitride film 33.
도 3b에서와 같이, 상기 제 1 BPSG층(34)상에 제 1 감광막을 도포하고, 상기 제 1 감광막을 비트 라인 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 3B, a first photoresist film is coated on the first BPSG layer 34, and the first photoresist film is selectively exposed and developed to be removed only at a portion where a bit line contact is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막을 마스크로 상기 제 1 BPSG층(34)을 선택 식각한 후, 상기 제 1 감광막을 제거한다.The first BPSG layer 34 is selectively etched using the selectively exposed and developed first photoresist layer, and then the first photoresist layer is removed.
이어, 상기 제 1 BPSG층(34)을 마스크로 상기 질화막(33)을 에치백(Etch-back)하여 제 1 콘택홀(35)을 형성하고 상기 노출된 워드 라인(32) 일측의 반도체 기판(31) 상에 질화막 스페이서(33a)를 형성한다.Subsequently, the nitride layer 33 is etched back using the first BPSG layer 34 as a mask to form a first contact hole 35 and the semiconductor substrate on one side of the exposed word line 32 ( 31 is formed on the nitride film spacer 33a.
도 3c에서와 같이, 상기 제 1 콘택홀(35)을 포함한 전면에 다결정 실리콘층을 형성한 후, 상기 제 1 BPSG층(34)을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 다결정 실리콘층을 평탄 식각하여 플러그층(36)을 형성한다.As shown in FIG. 3C, after the polycrystalline silicon layer is formed on the entire surface including the first contact hole 35, the polycrystalline silicon layer is flattened by a chemical mechanical polishing method using the first BPSG layer 34 as an etching end point. By etching, the plug layer 36 is formed.
도 3d에서와 같이, 상기 워드 라인(32)들을 식각 종말점으로 화학 기계 연마 방법에 의해 상기 질화막(33), 제 1 BPSG층(34) 및 플러그층(36)을 평탄 식각한다.As shown in FIG. 3D, the nitride film 33, the first BPSG layer 34, and the plug layer 36 are etched flat by the chemical mechanical polishing method with the word lines 32 as the etching endpoints.
그리고, 전면에 제 2 BPSG층(37), 반사방지막(38) 및 제 2 감광막(39)을 순차적으로 형성하고, 상기 제 2 감광막(39)을 비트 라인 콘택이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.A second BPSG layer 37, an antireflection film 38, and a second photoresist film 39 are sequentially formed on the entire surface, and the second photoresist film 39 is selectively exposed so that only the portion where the bit line contact is to be formed remains. And develop.
도 3e에서와 같이, 전면을 20 ∼ 70mT의 압력과 1000 ∼ 2000W의 전원 조건하에 C4F8, CH2F2, CO 또는 Ar 가스를 사용하여 10 ∼ 30초 동안 폴리머 형성 공정을 진행하므로 상기 제 2 감광막(39)의 표면에 폴리머(Polymer)층(40)을 형성한다.As shown in FIG. 3E, the front surface of the polymer is formed using C 4 F 8 , CH 2 F 2 , CO, or Ar gas under a pressure of 20 to 70 mT and a power source of 1000 to 2000 W. A polymer layer 40 is formed on the surface of the second photosensitive film 39.
여기서, 상기 반사방지막(38) 표면에도 상기 폴리머층(40)이 형성되지만 그 두께가 미비하다.Here, the polymer layer 40 is formed on the surface of the anti-reflection film 38 but the thickness thereof is insufficient.
도 3f에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(39)을 마스크로 상기 반사방지막(38)을 30 ∼ 70mT의 압력과 1000 ∼ 2000W의 전원 조건하에 O2, CO 또는 Ar 가스를 사용하여 선택 식각한다.As shown in FIG. 3F, the anti-reflection film 38 is subjected to O 2 , CO, or Ar gas under a pressure of 30 to 70 mT and a power source of 1000 to 2000 W using the selectively exposed and developed second photosensitive film 39 as a mask. Using selective etching.
이때 상기 반사방지막(39)의 식각 공정시, 상기 폴리머층(40)의 보호 역할로 상기 제 2 감광막(39)에 탑 CD 와이더닝이 발생되지 않는다.At this time, during the etching process of the anti-reflection film 39, the top CD widing is not generated in the second photoresist film 39 as a protective role of the polymer layer 40.
그리고, 상기 제 2 감광막(39)과 반사방지막(38)을 마스크로 상기 제 2 BPSG층(37)을 선택 식각하여 제 2 콘택홀(41)을 형성한 다음, 상기 폴리머층(40), 제 2 감광막(39) 및 반사방지막(38)을 제거한다.The second BPSG layer 37 is selectively etched using the second photoresist film 39 and the antireflection film 38 as a mask to form a second contact hole 41, and then the polymer layer 40, 2 Remove the photosensitive film 39 and the anti-reflection film 38.
상기 폴리머층(40)의 보호 역할로 상기 제 2 감광막(39)에 탑 CD 와이더닝이 발생되지 않아 도 4a에서와 같이, 상기 제 2 콘택홀(41)의 면적 증가를 방지하여 도 4b에서와 같이, 후속 공정에서 형성될 비트 라인(B)이 상기 제 2 콘택홀(41)을 커버한다.As a protection role of the polymer layer 40, the top CD winding is not generated in the second photoresist layer 39, so that the area of the second contact hole 41 is prevented from increasing as shown in FIG. 4A. Likewise, the bit line B to be formed in a subsequent process covers the second contact hole 41.
본 발명의 콘택홀 형성 방법은 콘택홀 형성을 위한 감광막 패턴(Pattern) 표면에 식각 보호막으로 폴리머층을 형성한 후 반사방지막과 층간 절연막을 선택 식각하여 콘택홀을 형성하므로, 콘택홀 형성 공정시 콘택 탑 CD 와이더닝의 발생을 방지하여 후속 공정에서 형성될 비트 라인이 상기 콘택홀을 커버하므로 쇼트 방지 및 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the contact hole forming method of the present invention, since the polymer layer is formed on the surface of the photoresist pattern for forming the contact hole, the contact hole is formed by selectively etching the anti-reflection film and the interlayer insulating film. Since the bit line to be formed in a subsequent process by preventing the occurrence of top CD widing covers the contact hole, there is an effect of preventing short and improving the yield and reliability of the device.
도 1a 내지 도 1e는 종래의 콘택홀 형성 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a conventional method for forming a contact hole.
도 2a와 도 2b는 종래의 콘택홀과 비트 라인을 나타낸 사진도2A and 2B are photographic views showing a conventional contact hole and bit line
도 3a 내지 도 3f는 본 발명의 실시 예에 따른 콘택홀 형성 방법을 나타낸 공정 단면도3A to 3F are cross-sectional views illustrating a method of forming a contact hole according to an exemplary embodiment of the present invention.
도 4a와 도 4b는 본 발명의 실시 예에 따른 콘택홀과 비트 라인을 나타낸 사진도4A and 4B are photographic views illustrating contact holes and bit lines according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11, 31 : 반도체 기판 12, 32 : 워드 라인11 and 31: semiconductor substrate 12 and 32: word line
13, 33 : 질화막 13a, 33a : 질화막 스페이서13, 33: nitride film 13a, 33a: nitride film spacer
14, 34 : 제 1 BPSG층 15, 35 : 제 1 콘택홀14, 34: first BPSG layer 15, 35: first contact hole
16, 36 : 플러그층 17, 37 : 제 2 BPSG층16, 36: plug layer 17, 37: second BPSG layer
18, 38 : 반사방지막 19, 39 : 제 2 감광막18, 38: antireflection film 19, 39: second photosensitive film
48 : 폴리머층 20, 41 : 제 2 콘택홀48: polymer layer 20, 41: second contact hole
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0083844A KR100527573B1 (en) | 2000-12-28 | 2000-12-28 | Method for forming a contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0083844A KR100527573B1 (en) | 2000-12-28 | 2000-12-28 | Method for forming a contact hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020054679A KR20020054679A (en) | 2002-07-08 |
| KR100527573B1 true KR100527573B1 (en) | 2005-11-09 |
Family
ID=27687413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0083844A KR100527573B1 (en) | 2000-12-28 | 2000-12-28 | Method for forming a contact hole |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100527573B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100928098B1 (en) * | 2002-12-24 | 2009-11-24 | 동부일렉트로닉스 주식회사 | Metal line formation method using oxide film |
| KR100621562B1 (en) * | 2004-07-30 | 2006-09-14 | 삼성전자주식회사 | Method of dry etching using selective polymer mask formed by CO gas |
-
2000
- 2000-12-28 KR KR10-2000-0083844A patent/KR100527573B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020054679A (en) | 2002-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20000044928A (en) | Method for forming trench of semiconductor device | |
| JP2006005344A (en) | Semiconductor pattern forming method | |
| US20080045033A1 (en) | Stacked structure and patterning method using the same | |
| KR100527573B1 (en) | Method for forming a contact hole | |
| KR100596899B1 (en) | Method for manufacturing semiconductor device | |
| KR100527572B1 (en) | Method for forming contact hole | |
| KR20020056013A (en) | Method for fabricating dual damascene | |
| KR100303997B1 (en) | Metal gate electrode formation method | |
| KR100772699B1 (en) | Method for forming semiconductor device | |
| KR100682167B1 (en) | Method for forming metal line | |
| KR100364810B1 (en) | Method for fabricating of semiconductor device | |
| KR100427718B1 (en) | Method for manufacturing a semiconductor device | |
| KR19990050866A (en) | Plug Formation Method for Semiconductor Devices | |
| KR100604759B1 (en) | Method for manufacturing semiconductor device | |
| KR100504551B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR100403327B1 (en) | Method for manufacturing semiconductor device | |
| KR100456421B1 (en) | Method of manufacturing a semiconductor device | |
| KR100419745B1 (en) | Method for manufacturing semiconductor device | |
| KR100314738B1 (en) | Method for forming gate electrode in semiconductor device | |
| KR100318262B1 (en) | Method for forming alignment key of semiconductor device | |
| KR20030091452A (en) | Method of forming pattern inhibiting pitting effect | |
| KR20020054637A (en) | Method for manufacturing semiconductor device | |
| KR20040031524A (en) | Method for forming floating gate of semiconductor element | |
| KR20030002051A (en) | A forming method of contact hole | |
| KR20040021370A (en) | Method for forming metal line of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |