KR19980020850A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to improve the level difference between devices.

Such a method of manufacturing a semiconductor device of the present invention includes the steps of forming a first insulating film and a second insulating film having a first contact hole on a semiconductor substrate having an impurity region, and forming a gate electrode in the first contact hole. Forming a third insulating film and a fourth insulating film having a first trench on the second insulating film including the gate electrode, forming a second contact hole on the impurity region, and forming the first trench and the second contact hole. Forming a bit line in the second insulating film; forming a fifth insulating film on the fourth insulating film including the bit line; and a sixth insulating film having a second trench; and forming a bit line on the impurity region in which the second contact hole is not formed. Forming a third contact hole and forming a capacitor in the second trench and the third contact hole.

Description

Manufacturing method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device of the present invention, and more particularly, to a method for manufacturing a semiconductor device for improving the level difference between devices.

After forming the device, a planarization insulating film such as BPSG is used to reduce the topologies generated in the device and the step difference between the cell region and the peripheral region.

1A to 1I are cross-sectional views illustrating a conventional method of forming a DRAM.

In the conventional DRAM cell forming method, as shown in FIG. 1A, the gate oxide film 12, the first polycrystalline silicon, and the first oxide film are sequentially formed on the semiconductor substrate 11, and then the first polycrystalline silicon and the first oxide film are formed. Is selectively etched to form a plurality of gates 13 and gate cap oxide films 14.

The impurity ions are implanted into the semiconductor substrate 11 using the gate 13 as a mask to form a plurality of impurity regions 15.

As shown in FIG. 1B, the nitride film 16 is formed on the surface of the gate oxide film 12 including the gate 13 and the gate cap oxide film 14 and then etched back to form the gate 13 and the gate cap oxide film 14. The sidewall of the nitride film 16 is formed in the side surface of the ().

As shown in FIG. 1C, a first high-temperature low-pressure dielectric (HLD) layer 17 and a first boron phosphorous silica (BPSG) layer 18 are sequentially formed on the front surface, and then the first BPSG layer is formed. (18) is annealed, etched back, and then sintered to first planarize.

Subsequently, after the first photoresist film 19 is applied onto the first BPSG layer 18, the first photoresist film 19 is selectively exposed and developed to remove only a portion where a bit line tonetack is to be formed, and then the selective The first BPSG layer 18, the first HLD layer 17, and the gate oxide layer 12 are sequentially etched using the first photosensitive film 19 exposed and developed as a mask, in turn. To form and remove the first photoresist film (19).

As shown in FIG. 1D, a second polycrystalline silicon 20, a tungsten silicide 21, and a second photosensitive film 22 are sequentially formed on the entire surface, and the second photosensitive film 22 is formed using a bit line pattern mask. After selectively exposing and developing using the second photosensitive film 22 as the mask, the second polycrystalline silicon 20 and the tungsten silicide 21 are selectively etched. The bit line is formed to be connected to the impurity region 15 through the contact hole, and the second photoresist layer 22 is removed.

As shown in FIG. 1E, a second HLD layer 23 and a second BPSG layer 24 are sequentially developed on the surface of the first BPSG layer 18 including the bit lines, and then the second BPSG layer 24 is developed. Is second planarized by annealing, etch back and sintering.

As shown in FIG. 1F, a third HLD layer 25 and a third photoresist layer 26 are sequentially formed on the second BPSG layer 24, and then the third photoresist layer 26 is formed by a storage node contact of a capacitor ( After selectively exposing and developing only a portion where a storage node contact is to be formed, the selectively exposed and developed third photoresist layer 26 is used as a mask, and then the selectively exposed and developed third photoresist layer 26 is used. ) As a mask, the third HLD layer 25, the second BPSG layer 24, the second HLD layer 23, the first BPSG layer 18, and the first HLD layer 17. ) And the gate oxide film 12 are selectively etched to form a second contact hole and to remove the third photoresist layer 26.

As shown in FIG. 1G, a fourth HLD layer 27 is formed on the front surface and etched back to form a side wall of the fourth HLD layer 27 on the side of the second contact hole. After the third polycrystalline silicon 28, the second oxide film 29, and the fourth photosensitive film 30 are sequentially formed on the surface of the third HLD layer 25 including the fourth HLD layer 27, The fourth photosensitive film 30 is selectively exposed and developed using a coffee sheet pattern mask.

The second oxide film 29 and the third polycrystalline silicon 28 are selectively etched using the selectively exposed and developed fourth photosensitive film 30 as a mask, and then the fourth photosensitive film 30 is removed. .

As shown in FIG. 1H, the fourth polycrystalline silicon 31 is formed and etched back on the surface of the third HLD layer 25 including the second oxide film 29 to etch back the second oxide film 29 and the third polycrystalline silicon. A sidewall of the fourth polycrystalline silicon 31 is formed on the side surface of the substrate 28, and then the second oxide layer 29 is wet-etched and removed to form a storage node of the capacitor.

As shown in FIG. 1I, the upper electrode of the capacitor is formed by forming and oxidizing a second nitride film 32 on the storage node surface, and then forming a fifth polycrystalline silicon 33 on the oxidized second nitride film 32. To form.

In the conventional DRAM cell manufacturing method, the planarization film is planarized, but due to the step difference, the device is not completely planarized, so that the photoresist film is unevenly applied. There was this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a planarization method of a semiconductor device in which an element is formed inside an insulating film without a step.

1A to 1I are cross-sectional views illustrating a method of forming a conventional DRAM.

2A to 2H are cross-sectional views illustrating a method of forming a DRAM according to the present invention.

Explanation of symbols on the main parts of the drawings

41 semiconductor substrate 43 impurity region

44 gate oxide film 45 first BPSG layer

46: gate 47: gate cap oxide film

48: first HLD layer 49: second BPSG layer

54 second HLD layer 55 third BPSG layer

59: nitride film

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming an insulating film on a semiconductor substrate, patterning the insulating film to remove only a portion where the device is to be formed, and forming a device on a portion exposed by the patterning of the insulating film. Characterized by comprising a step.

Referring to the accompanying drawings, a preferred embodiment of the planarization method of a semiconductor device according to the present invention as described above in detail as follows.

2A to 2H are cross-sectional views illustrating a method of forming a DRAM according to the present invention.

As shown in FIG. 2A, the first photoresist layer 42 is coated on the semiconductor substrate 41, and selectively exposed and developed so that only a portion where the gate electrode is to be formed is left using a gate pattern mask, and then the selective exposure and development Impurity ions are implanted into the semiconductor substrate 41 by using the first photosensitive film 42 as a mask to form the impurity region 43 in the semiconductor substrate 41, and then the first photosensitive film 42 is removed. do.

As shown in FIG. 2B, the gate oxide layer 44 and the first BPSG layer 45 are sequentially formed on the semiconductor substrate 41, and then only the portion where the gate is to be formed is removed from the first BPSG layer 45. Etch selectively.

Subsequently, a first polycrystalline silicon and a first oxide film are sequentially formed on the surface of the first BPSG layer 45 including the exposed gate oxide layer 44, and then etched back to gate the first BPSG layer 45. 46 and a gate cap oxide film 47 are formed.

As shown in FIG. 2C, the first HLD layer 48, the second BPSG layer 49, and the second photoresist film 50 are sequentially formed on the first BPSG layer 45 including the gate cap oxide layer 47. After forming, selectively exposing and developing the second photoresist film 50 to remove only the portion where the bit line is to be formed, and then using the selectively exposed and developed second photoresist film 50 as a mask. The first trenches are formed by selectively etching the BPSG layer 49 to have a predetermined depth, and the second photoresist layer 50 is removed.

As shown in FIG. 2D, a third photoresist film 51 is applied onto the second BPSG layer 49 having the first trench, and selectively exposed to remove only the impurity region 43 between the gates 46. After the development, the second BPSG layer 49, the first HLD layer 48, and the first BPSG layer 45 are sequentially formed using the selectively exposed and developed third photoresist film 51 as a mask. After the first contact hole is formed by selectively etching the gate oxide layer 44, the third photoresist layer 51 is removed.

As shown in FIG. 2E, a second polycrystalline silicon 52 is formed on the surface of the second BPSG layer 49 including the exposed semiconductor substrate 41, the first BPSG layer 45, and the first HLD layer 48. ) And tungsten silicide 53 are sequentially formed and then etched back to form a bit line in the second BPSG layer 49 to be connected to the impurity region 43 through a first contact hole.

As shown in FIG. 2F, a second HLD layer 54, a third BPSG layer 55, and a fourth photoresist film 56 are sequentially formed on the second BPSG layer 49 including the bit line. After selectively exposing and developing the fourth photoresist layer 56 to remove only a portion where a capacitor is to be formed, the third BPSG layer 55 using the selectively exposed and developed fourth photoresist layer 56 as a mask. Is selectively etched to have a predetermined depth to form a second trench, and the fourth photoresist layer 56 is removed.

As shown in FIG. 2G, the fifth photoresist layer 57 is coated on the third BPSG layer 55 having the second trench, and is selectively removed to remove only a predetermined region of the impurity region 43 in which the bit line is not formed. And the third BPSG layer 55, the second HLD layer 54, and the second BPSG layer in order using the selectively exposed and developed fifth photosensitive film 57 as a mask. 49, the first HLD layer 48, the first BPSG layer 45 and the gate oxide film 44 are selectively etched to form a second contact hole, and then the fifth photoresist film 57 is removed. .

As shown in FIG. 2H, a third polycrystalline silicon 58 and a nitride film 59 are sequentially formed on the entire surface, and the nitride film 59 is oxidized, and then the third polycrystalline silicon 58 and the nitride film 59 are formed. Etch back). The fourth polycrystalline silicon 60 is formed on the third BPSG layer 55 including the nitride film 59.

The present invention is applied not only to the DRAM but also to all the stepped devices.

The method of manufacturing a semiconductor device of the present invention forms a device including a gate, a bit line, and a capacitor in an insulating film, thereby solving the problem caused by the step difference of the device, and thus, greatly improving the yield of the device.

Claims (1)

Forming a first insulating film and a second insulating film having a first contact hole on a semiconductor substrate having an impurity region; Forming a gate electrode in the first contact hole; Forming a third insulating film and a fourth insulating film having a first trench on the second insulating film including the gate electrode; Forming a second contact hole on the impurity region and forming a bit line in the first trench and the second contact hole; Forming a fifth insulating film and a sixth insulating film having a second trench on the fourth insulating film including the bit line; And forming a third contact hole on the impurity region in which the second contact hole is not formed, and forming a capacitor in the second trench and the third contact hole.