KR20020017448A - Method for forming self aligned contact pad of semiconductor device using selective epitaxial growth method - Google Patents

Abstract

PURPOSE: A method for forming a self-aligned contact pad is provided to prevent a void inside a polysilicon layer pad, by forming an insulation layer after a nitride layer for a gate spacer and an etch stop layer are sequentially formed in a cell region and by forming the polysilicon layer pad. CONSTITUTION: The nitride layer is formed on the exposed surface of a semiconductor substrate(500) having cell and core regions and on the gate stack(510). The nitride layer in the core region is etched back to form the gate spacer(520) on a side surface of the gate stack in the core region. The first etch stop layer(530) covering the nitride layer in the cell region, the gate spacer in the core region and the gate stack is formed. The first insulation layer(540) covering the first etch stop layer is formed. The first insulation layer is planarized to expose the first etch stop layers on the gate stack. The first insulation layer remaining between the first etch stop layers in the cell region is removed. The gate spacer is formed on the side surface of the gate stack. The polysilicon layer(511) is formed between the gate spacers. An epitaxial layer(567) is formed on the polysilicon layer. The second etch stop layer(570) and the second insulation layer(590) are formed. Contact holes exposing the epitaxial layer in the cell region and the substrate in the core region are formed. A conductive layer is filled in the contact holes to form a contact pad.

Description

Method for forming self aligned contact pad of semiconductor device using selective epitaxial growth method

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a self-aligned contact pad of a semiconductor device using a selective epitaxial growth method.

Increasing integration of semiconductor devices has resulted in very narrow misalign margins in the photolithography process. Accordingly, in recent years, a self aligned contact (SAC) process is used to secure a margin of misalignment. However, as the degree of integration of semiconductor devices becomes higher, various problems are increasingly serious even when a self-aligned contact process is performed. This will be described in more detail with reference to the drawings.

1A to 1C are cross-sectional views illustrating a problem in which voids are formed by a conventional self-aligned contact pad forming method.

Referring first to FIG. 1A, a gate stack 110 is formed on a semiconductor substrate 100 through a gate insulating layer 101. The gate stack 110 is formed by sequentially stacking the polysilicon layer 111, the tungsten silicide 112, and the silicon nitride layer 113. The gate spacer 120 is formed on the side of the gate stack 110. Next, an insulating film, for example, an oxide film 130, is formed to completely cover the gate stack 110, and a mask film pattern 140 made of a polysilicon film is formed thereon.

Next, referring to FIG. 1B, the exposed portion of the oxide layer 130 is etched using the mask layer pattern 140 as an etch mask to expose the surface of the semiconductor substrate 100 between the gate spacers 120. Next, the mask layer pattern 140 is removed by cleaning, and at this time, the side portion A of the oxide layer 130 is recessed to the portion indicated by the dotted line in the drawing due to the difference in the etching rate between the oxide layer and the polysilicon layer.

Next, referring to FIG. 1C, after the cleaning is finished, the polysilicon layer 150 for forming the lower contact pad is filled in the contact, in which case the polysilicon due to the recess portion A of the oxide layer 130. The void 155 is generated in the film 150.

2 is a cross-sectional view illustrating a problem in which contact resistance is reduced by a conventional self-aligned contact pad forming method. For simplicity, it will be assumed that the void is not generated.

Referring to FIG. 2, as described with reference to FIGS. 1A through 1C, after the polysilicon film 150 is formed, an upper contact pad, for example, a BC (buried contact) pad 160 for a capacitor and a DC for a bit line (Direct Contact) The pads 170 are formed in contact with the polysilicon film 150, respectively. However, at this time, misalignment occurs due to an increase in the degree of integration of the device, and the misalignment causes the BC pad 160 to be separated from the original position 160 '(indicated by a dotted line in the drawing). In this case, the area of the surface S on which the BC pad 160 is in contact with the polysilicon film 150 is reduced, and as a result, the contact resistance between the polysilicon film 150 and the BC pad 160 increases, thereby increasing the electrical properties of the device. Characteristics deteriorate.

3A and 3B are cross-sectional views illustrating a problem in which a short between a contact pad and a gate stack is generated in a cell region by a conventional self-aligned contact pad forming method.

Referring first to FIG. 3A, as described with reference to FIGS. 1A to 1C, after performing a self-aligned contact process on the cell region and forming the polysilicon layer 150, an insulating film, for example, is formed in the cell region and the core region. An oxide film 180 is formed. In this case, an etch stop layer 210 is already formed on the gate stack 110 and the gate spacer 120 in the core region. Subsequently, a mask layer pattern, for example, a photoresist layer pattern 190, is formed in the cell region and the core region.

Next, referring to FIG. 3B, after forming the photoresist layer pattern 190, a contact hole for forming an upper contact pad such as a DC contact pad 200 is formed. In other words, the photoresist layer pattern 190 is used as an etching mask to simultaneously etch the cell region and the core region. In this case, since the maximum thickness d ₂ of the oxide layer 180 to be etched in the core region is greater than the maximum thickness d ₁ of the oxide layer 180 to be etched in the cell region, the oxide layer 180 in the core region is While fully etched, the silicon nitride film 113 and the gate spacer 120 that are not to be etched in the cell region are also etched. As a result, the tungsten silicide 112 of the gate stack 110 is exposed by the etching of the silicon nitride film 113 and the gate spacer 120. In this state, when the DC contact pad 200 is formed, a DC contact pad 200 is formed. A problem arises in which the contact pad 200 and the gate stack 110 are shorted (indicated by B in the figure).

As such, a self-aligned contact process using a selective epitaxial growth method has been proposed to solve the problems in the self-aligned contact process due to the high integration of semiconductor devices. The self-aligned contact process using this selective epitaxial growth method is a process of growing an epitaxial layer on the surface of a semiconductor substrate between gate spacers after forming a gate stack and a gate spacer. However, this process has a problem that it is not possible to grow the epitaxial layer by a sufficient height, which will be described in more detail with reference to the drawings.

4 is a layout diagram illustrating a problem of a self-aligned contact process using a selective epitaxial growth method.

Referring to FIG. 4, the active regions 400 are separated from each other. However, in the process of growing the epitaxial layer 410 on the surface of the semiconductor substrate between the gate spacers, due to the isotropic growth characteristic of the epitaxial layer 410, it grows not only on the upper surface but also on the side of the Ira, and worse, C in the drawing. As shown, a problem arises in that the adjacent active region 400 is shorted with each other due to the lateral growth of the epitaxial layer 410.

The technical problem to be achieved by the present invention is to prevent the generation of voids in the process of forming a self-aligned contact pad, increased contact resistance due to misalignment, a shot between the contact pad and the gate stack, and a shot between adjacent active regions. To provide a self-aligned contact pad forming method using a selective epitaxial growth method that can be.

1A to 1C are cross-sectional views illustrating a problem in which voids are formed by a conventional self-aligned contact pad forming method.

2 is a cross-sectional view illustrating a problem in which contact resistance is reduced by a conventional self-aligned contact pad forming method.

3A and 3B are cross-sectional views illustrating a problem in which a short between a contact pad and a gate stack is generated in a cell region by a conventional self-aligned contact pad forming method.

4 is a layout diagram illustrating a problem of a self-aligned contact process using a selective epitaxial growth method.

5 to 13 are cross-sectional views illustrating a method of forming a self-aligned contact pad using a selective epitaxial growth method according to the present invention.

In order to achieve the above technical problem, the self-aligned contact pad forming method using the selective epitaxial growth method according to the present invention, in a semiconductor device in which a gate stack is formed on a semiconductor substrate having a cell region and a core region through a gate insulating film A method of forming a self-aligned contact pad of a semiconductor device using a selective epitaxial growth method, comprising: forming a nitride film for a gate spacer on an exposed surface of the semiconductor substrate and the gate stack in the cell region and the core region; Etching back the nitride film for the gate spacer in the core region to form a gate spacer on the gate stack side of the core region: a first etching covering the gate spacer nitride film in the cell region and the gate spacer and gate stack in the core region Forming a blocking layer: forming a first insulating layer covering both of the cell etching layer and the core etching area; Planarizing an entire surface of the first insulating layer to expose the first etch stop layers on the gate stack in the cell region and the core region; Removing a first insulating layer remaining between the first etch stop layer in the cell region by using a first mask layer pattern; Removing the first mask layer pattern, and etching back the first etch stop layer and the nitride layer for the gate spacer of the cell region to form a gate spacer on a side of the gate stack; Forming a polysilicon film between the gate spacers of the cell region; Forming an epitaxial layer on the polysilicon film; Forming a second etch stop layer on the exposed surface of the epitaxial layer of the cell region and the exposed surface of the gate stack of the cell region; Forming a second etch stop layer of the cell region and a second insulating layer covering the first etch stop layer and the first etch stop layer of the core region; Performing an etching process using a predetermined second mask layer pattern, forming contact holes exposing the epitaxial layer in the cell region and forming contact holes exposing the semiconductor substrate in the core region; And forming a contact pad by removing the second mask layer pattern and filling a conductive layer in the contact hole of the cell region and the contact hole of the core region.

The first etch stop layer and the second etch stop layer may be formed of a material having an etch selectivity with respect to the first and second insulating layers, wherein the first and second insulating layers are oxide films, and the first and second The etch stop layer may be a silicon nitride layer.

The planarizing of the first insulating layer is preferably performed by using a front chemical mechanical polishing method. The first mask layer pattern may be a polysilicon layer pattern.

The forming of the second etch stop layer may include forming a second etch stop layer on the epitaxial layer of the cell region and the exposed surface of the gate stack and on the first etch stop layer on the first insulating layer and the gate stack of the core region. step; Forming a photoresist layer pattern covering the second etch stop layer of the cell region and exposing the second etch stop layer of the core region; Removing the second etch stop layer of the core region using the photoresist pattern as an etch mask; And removing the photoresist film pattern.

The forming of the contact hole in the cell region and the core region may include forming a photoresist layer pattern on a second insulating layer of the cell region and the core region; The second insulating layer of the cell region is etched using the photoresist layer pattern as an etch mask, and the second insulating layer and the first insulating layer of the core region are etched at the same time, so that the second etch stop layer of the cell region and the core region are etched. Exposing the first etch stop layer; And removing a second etch stop layer of the exposed cell region and a first etch stop layer of the core region to form a contact hole exposing the epitaxial layer in a cell region and exposing the semiconductor substrate in a core region. It is preferable to include the step of forming a hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

5 to 13 are cross-sectional views illustrating a method of forming a self-aligned contact pad using a selective epitaxial growth method according to the present invention.

First, referring to FIG. 5, gate stacks 510 are formed on a semiconductor substrate 500 through a gate insulating layer 501 on both a cell region and a core region. The gate stack 510 is formed by sequentially stacking a polysilicon layer 511, a metal silicide 512, and a silicon nitride layer 513. Subsequently, a silicon nitride film 520 ′ for forming a gate spacer is formed to cover the exposed surface of the semiconductor substrate 500 and the gate stack 510 between the gate stacks 510.

Next, referring to FIG. 6, the gate spacer 520 is formed on the side of the gate stack 510 in the core region by etching back the silicon nitride film 520 ′ for forming the gate spacer in the core region. Next, the first etch stop layer 530 is formed in both the cell region and the core region. The first etch stop layer 530 is formed of a silicon nitride film. In the cell region, a first etch stop layer 530 is formed on the silicon nitride layer 520 ′ for forming the gate spacer. In the core region, the silicon nitride layer 513 of the gate stack 510 is exposed on the exposed surface of the semiconductor substrate 500. The first etch stop layer 530 is formed on the gate spacer 520. Subsequently, the first insulating layer 540 is formed on the first etch stop layer 530 in both the cell region and the core region.

Next, referring to FIG. 7, both the cell region and the core region are removed using the planarization process until the first etch stop layer 530 on the gate stack 510 is exposed. The planarization process is performed using a full CMP (Chemical Mechanical Polishing) method. When the planarization process is completed, the first insulating layer 540 remains between the first etch stop layer 530 on the side of the gate stack 510 in the cell region, and the first etch stop layer covering the gate spacer 520 also in the core region. Remain only between 530. Next, a mask film 550 made of a polysilicon film is formed on both surfaces of the cell region and the core region. The mask layer is patterned only in the cell region to form a mask layer pattern 555 exposing the corner portion of the first etch stop layer 530 and the oxide layer 540.

8, the first insulating layer 540 of FIG. 7 is removed using the mask layer pattern 555 of FIG. 7 as an etching mask. In this case, since the mask layer pattern 555 of FIG. 7 is formed after the entire surface planarization process, a portion to be recessed does not occur when the first insulating layer 540 of FIG. 7 is removed. Even if formed, no void is produced. Subsequently, only the mask layer pattern 555 of the cell region is removed while leaving the mask layer 550 of the core region. The gate spacer 520 is also formed in the cell region by sequentially etching back the first etch stop layer 530 and the gate nitride silicon nitride layer 530 ′ in the cell region. After the gate spacer 520 is formed, a polysilicon film 560 is formed in the cell region.

Next, referring to FIG. 9, the polysilicon film 560 in the cell region and the mask film 550 in the core region are etched back to form a polysilicon film pad 565 between the gate spacer 520 in the cell region. In the core region, the mask layer 550 is removed to expose the first etch stop layer 530 and the first insulating layer 540 on the gate stack 510. Next, the epitaxial layer 567 is formed on the polysilicon film pad 565 in the cell region by using the selective epitaxial growth method. A lower contact pad is then formed in the cell region by the epitaxial layer 567 and the polysilicon film pad 565. This lower contact pad has a larger surface area by the upper epitaxial layer 567. Therefore, even if a misalignment occurs during the formation of the upper contact pad, which is a subsequent process, the decrease in the contact area between the upper contact pad and the epitaxial layer 567 may be reduced, thereby suppressing an increase in contact resistance.

Next, referring to FIG. 10, a second etch stop layer 570 is formed over the cell region and the core region. The second etch stop layer 570 is formed of a silicon nitride film. Next, a photoresist film pattern 580 is formed, which completely covers the cell area and completely exposes the core area.

Next, referring to FIG. 11, the second etch stop layer 570 of the core region is removed using the photoresist film pattern 580 of FIG. 10 as an etching mask. The photoresist film pattern 580 in the cell region is removed. Next, a second insulating film 590 is formed over the cell region and the core region. The second insulating film 590 is formed of an oxide film. Next, a mask film pattern 600 is formed on the second insulating film 590. The mask layer pattern 600 is to form upper contact holes such as DC contact holes in the cell region and the core region, respectively. That is, in order to form upper contact holes in the cell region and the core region, respectively, the mask layer pattern 600 has an opening that exposes the second insulating layer 590 on the epitaxial layer 567 in the cell region. The region has an opening that exposes the gate spacer 520 and the second insulating film 590 on a portion of the surface of the semiconductor substrate 500.

Next, referring to FIG. 12, the exposed portion of the second insulating layer 590 is etched in the cell region using the mask layer pattern 600 of FIG. 11, and the exposed portion of the second insulating layer 590 in the core region. After etching, a portion of the first insulating layer 540 is sequentially etched. At this time, the thickness of the insulating film to be etched in the cell region and the thickness of the insulating film to be etched in the core region are different. That is, the thickness of the insulating film to be etched in the core region is greater than the thickness of the insulating film to be etched in the cell region. Therefore, while the second insulating layer 590 and the first insulating layer 540 are sequentially etched in the core region, the etching continues in the cell region even after the second insulating layer 590 is etched. However, no further etching is performed by the second etch stop layer 567 in the cell region. Thus, the silicon nitride layer 513 and the gate spacer of the gate stack 510 are etched to expose the metal silicide 512. The phenomenon does not occur. As described above, after the upper contact holes 611 and 612 are formed in the cell region and the core region, the mask layer pattern 600 is removed.

Next, referring to FIG. 13, the second etch stop layer 570 exposed between the second insulating layers 590 in the cell region and the first etch stop layer 530 exposed in the core region are removed. The upper contact pads 620 are formed by filling conductive films in upper contact holes of the cell region and the core region, respectively.

As described above, the self-aligned contact pad forming method of the semiconductor device using the selective epitaxial growth method according to the present invention has the following advantages.

First, since the nitride film for the gate spacer and the etch stop layer are sequentially formed on the gate stack of the cell region, an insulating film is formed, and then a polysilicon film pad is formed after the entire surface planarization process, void generation in the polysilicon film pad is prevented. You can prevent it.

Second, a polysilicon film pad is formed between the gate spacers of the cell region, and an epitaxial layer is formed thereon, so that a contact pad and the epitaxial layer formed even if misalignment occurs in forming the contact pad in a subsequent process. The increase in contact resistance can be suppressed by minimizing the decrease in the contact area of.

Third, since an etch stop layer is formed only in the cell region, contact holes for forming contact pads are formed. The problem of this being exposed is avoided.

Claims (7)

A method for forming a self-aligned contact pad of a semiconductor device using a selective epitaxial growth method in a semiconductor device in which a gate stack is formed on a semiconductor substrate having a cell region and a core region with a gate insulating film. Forming a nitride film for a gate spacer on the exposed surface of the semiconductor substrate and the gate stack in the cell region and the core region; Etching back the nitride film for the gate spacer in the core region to form a gate spacer on a gate stack side of the core region; Forming a nitride layer for the gate spacer of the cell region and a first etch stop layer covering the gate spacer and the gate stack of the core region: Forming a first insulating layer covering both the cell etch and the core etch stop layer; Planarizing an entire surface of the first insulating layer to expose the first etch stop layers on the gate stack in the cell region and the core region; Removing a first insulating layer remaining between the first etch stop layer in the cell region by using a first mask layer pattern; Removing the first mask layer pattern, and etching back the first etch stop layer and the nitride layer for the gate spacer of the cell region to form a gate spacer on a side of the gate stack; Forming a polysilicon film between the gate spacers of the cell region; Forming an epitaxial layer on the polysilicon film; Forming a second etch stop layer on the exposed surface of the epitaxial layer of the cell region and the exposed surface of the gate stack of the cell region; Forming a second etch stop layer of the cell region and a second insulating layer covering the first etch stop layer and the first etch stop layer of the core region; Performing an etching process using a predetermined second mask layer pattern, forming contact holes exposing the epitaxial layer in the cell region and forming contact holes exposing the semiconductor substrate in the core region; And Removing the second mask layer pattern, and filling a contact layer in the contact hole in the cell region and the contact hole in the core region to form a contact pad, the semiconductor device using the selective epitaxial growth method Method of forming a self aligned contact pad. The method of claim 1, The first etch stop layer and the second etch stop layer are formed of a material having an etch selectivity with respect to the first and second insulating layers, the self aligned contact pads of the semiconductor device using the selective epitaxial growth method. Way. The method of claim 2, The first and second insulating films are oxide films, and the first and second etch stop films are silicon nitride films. The method of forming self-aligned contact pads of a semiconductor device using a selective epitaxial growth method. The method of claim 1, And planarizing the first insulating layer is performed by using a front surface chemical mechanical polishing method. The method of claim 1, The first mask layer pattern is a polysilicon layer pattern, characterized in that the self-aligned contact pad forming method of a semiconductor device using a selective epitaxial growth method. The method of claim 1, wherein the forming of the second etch stop layer comprises: Forming a second etch stop layer on the epitaxial layer of the cell region and on the exposed surface of the gate stack and on the first etch stop layer on the first insulating layer and the gate stack of the core region; Forming a photoresist layer pattern covering the second etch stop layer of the cell region and exposing the second etch stop layer of the core region; Removing the second etch stop layer of the core region using the photoresist pattern as an etch mask; And Removing the photoresist layer pattern; and forming a self-aligned contact pad in a semiconductor device using a selective epitaxial growth method. The method of claim 1, wherein forming a contact hole in the cell region and the core region comprises: Forming a photoresist film pattern on the second insulating film of the cell region and the core region; The second insulating layer of the cell region is etched using the photoresist layer pattern as an etch mask, and the second insulating layer and the first insulating layer of the core region are etched at the same time, so that the second etch stop layer of the cell region and the core region are etched. Exposing the first etch stop layer; And Removing the second etch stop layer of the exposed cell region and the first etch stop layer of the core region to form a contact hole exposing the epitaxial layer in the cell region and exposing the semiconductor substrate in the core region Method for forming a self-aligned contact pad of the semiconductor device using a selective epitaxial growth method comprising the step of forming a.