JP2002093897A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, where in forming an element separation region by an STI method, the exposure of a semiconductor substrate at a trench top part is surely prevented, for simplifying the manufacturing process and coping with a finer element. SOLUTION: There are provided a process (a) where a first protective film and a second protective film are sequentially deposited on a semiconductor substrate, a process (b) where an opening is formed in a region, corresponding to an element separation region of the first and second protective films, a process (c) where a groove is formed on the semiconductor substrate using the acquired second protective film as a mask, a process (d) where a third insulating film and a fourth insulating film are sequentially laminated on the semiconductor substrate comprising the groove, a process (e) where the fourth insulating film is polished until at least a surface of the third insulating film is exposed, and a process (f) where the semiconductor substrate surface is exposed, for forming the element separation region on the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a trench isolation (ST).
I; Shallow Trench Isolation).

[0002]

2. Description of the Related Art In recent years, as semiconductor devices such as LSIs have become more highly integrated, devices have been miniaturized, that is, design rules have been miniaturized. In the miniaturization of devices, with the miniaturization of gate electrodes and metal wirings and the miniaturization of element isolation regions, reduction of these distances is required. Of these, like the gate electrode and the metal wiring, those that are processed by the lithography technique and the anisotropic etching technique greatly depend on the lithography technique.

On the other hand, in miniaturization of the element isolation region, the method of forming the element isolation region itself has a great influence on the miniaturization in addition to the lithography technique. Therefore, as an element isolation method instead of the LOCOS method, trench element isolation (hereinafter referred to as "ST
I ") is proposed and adopted. The STI method is
Since it is a method of forming a trench in a silicon substrate by anisotropic etching and filling this with a silicon oxide film,
The dimensional conversion difference of the element isolation region caused by the element isolation forming step is small, which is an advantageous method for miniaturization.

However, in the STI method, as shown in FIGS. 2A and 2B, the silicon oxide film 22 buried in the trench 21 is etched in a subsequent semiconductor device manufacturing process. The semiconductor substrate 20 at the upper end A of the trench 21 is exposed. As a result, when a transistor or the like is subsequently formed using this semiconductor substrate 20, an electric field concentrates on the gate insulating film in the exposed portion of the semiconductor substrate 20, and a hump occurs due to the gate voltage-drain current characteristics of the transistor. There is a problem that the threshold voltage is lowered. Therefore, an STI method that solves this problem is proposed in Japanese Patent Application Laid-Open No. H11-195701.

[0005] First, as shown in FIG. 3A, a first silicon oxide film 32 and a first silicon nitride film 33 are formed on a silicon substrate 31. Subsequently, a resist pattern 34 having an opening in a predetermined region by photolithography technology
To form Next, as shown in FIG. 3B, the first silicon nitride film 33 and the first silicon oxide film 32 are etched using the resist pattern 34 as a mask,
Further, using the obtained first silicon nitride film 33 as a mask, the silicon substrate 31 is etched to form a first groove 35. A second silicon nitride film 36a is formed on the entire surface of the silicon substrate 31 including the first groove 35.

Next, as shown in FIG. 3C, the second silicon nitride film 36a is etched back to form a side wall silicon nitride film 36 on the side wall of the first groove 35. The sidewall silicon nitride film 36 can prevent the silicon substrate 31 at the upper end of the trench 35 from being exposed. Subsequently, as shown in FIG. 3D, the silicon substrate 31 is etched using the first silicon nitride film 33 and the side wall silicon nitride film 36 as a mask, so that the second groove 35 is formed in the first groove 35. Is formed. A second silicon oxide film 38 is formed on the entire surface of the silicon substrate 31 including the first groove 35 and the second groove 37. Next, as shown in FIG.
The second silicon oxide film 38 is removed from the first silicon nitride film 3 by CMP (Chemical Mechanical Polishing).
3 Polishing is removed until the surface is exposed. afterwards,
As shown in FIG. 3F, the first silicon nitride film 33 and the first silicon oxide film 32 are removed by wet etching to form a trench isolation region.

[0007]

However, the improved STI method as described above has the following problems. First, the side wall silicon nitride film 36 is also exposed to the etching while the second trench 37 is being etched, so that the thickness of the side wall silicon nitride film 36 is reduced, and the silicon substrate 31 at the upper end of the trench 35 is exposed. Therefore, a decrease in the threshold voltage of a transistor obtained later using the silicon substrate 31 is unavoidable. The etching for forming the groove is performed twice, and the etching for the first silicon nitride film is performed twice.
Each time, the second silicon nitride film 36a for forming the side wall silicon nitride film 36 needs to be etched back once, which increases the number of steps. Further, since a sidewall is formed of a silicon nitride film in the first groove 35 and the second groove 37 is formed, it becomes difficult to open the groove as the element is miniaturized.

The present invention has been made in view of the above problems, and simplifies the manufacturing process while securely preventing exposure of a semiconductor substrate at the upper end of a trench when forming an element isolation region by the STI method. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can cope with miniaturization of semiconductor devices.

[0009]

According to the present invention, (a)
A step of sequentially depositing a first protective film and a second protective film on a semiconductor substrate; (b) a step of forming an opening in a region corresponding to an element isolation region of the first and second protective films; and (c). Forming a groove in the semiconductor substrate using the second protective film in which the opening is formed as a mask, and (d) sequentially stacking a third insulating film and a fourth insulating film on the semiconductor substrate including the groove. And (f) polishing the fourth insulating film until at least the surface of the third insulating film is exposed; and (f) exposing the semiconductor substrate surface.
A method for manufacturing a semiconductor device in which an element isolation region is formed in a semiconductor substrate is provided.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of manufacturing a semiconductor device according to the present invention is a method of forming an element isolation region by embedding an insulating film in a groove formed in a semiconductor substrate by the STI method. According to the method for manufacturing a semiconductor device of the present invention, first,
In the step (a), the first protective film and the second protective film are formed on the semiconductor substrate.
A protective film is sequentially deposited. The semiconductor substrate is not particularly limited as long as it is generally used for a semiconductor device, and examples thereof include elemental semiconductors such as silicon and germanium, and compound semiconductors such as GaAs, InGaAs, and ZnSe. Among them, a silicon substrate is preferable.

The first and second protective films are not particularly limited as long as they have a material, a film thickness and the like usually used in a semiconductor device. For example, a silicon oxide film (thermal oxide film, low-temperature Oxide film: LTO film, etc., high-temperature oxide film: HTO film, TEOS film, plasma TEOS film, etc.),
Silicon nitride film, SOG film, NSG film, PSG film, BS
Insulating films such as G films and BPSG films; metal films, refractory metal films,
A single-layer film or a stacked film of a conductive film such as polysilicon, silicide, or polycide may be used. The protective film is formed, for example, by a thermal oxidation method, a low pressure CVD method, a normal pressure CVD method, or a plasma CVD method.
It can be formed by various methods such as a vacuum method, a vacuum evaporation method, and an EB method. In particular, it is more preferable that the second protective film is composed of an insulating film or a conductive film, and the first protective film is composed of an insulating film. When the protective film is composed of two layers, the second
It is preferable that the protective film is made of a material having a lower removal rate than the first protective film. Here, a low removal rate means that the etching or polishing rate is low by wet etching, dry etching, CMP, or the like under appropriate conditions. Specifically, it is preferable that the first protective film and the second protective film are a silicon oxide film and a silicon nitride film, respectively. The thickness of the protective film is not particularly limited, and can be determined in consideration of the height of the protrusion of the insulating film embedded in the groove from the surface of the semiconductor substrate, as described later. For example, when the first protective film / second protective film is a silicon oxide film / silicon nitride film, 10-30
nm / 100 to 300 nm.

In the step (b), an opening is formed in a region of the first and second protective films corresponding to the element isolation region. The opening can be formed by forming a resist pattern by a known method and a photolithography process, and performing etching using the resist pattern as a mask. The size, position, and the like of the opening can be appropriately adjusted depending on the layout, performance, and the like of the semiconductor device to be obtained.

In the step (c), a groove is formed in the semiconductor substrate using the second protective film in which the opening is formed as a mask. The groove can be formed by various methods such as dry etching or wet etching.
Anisotropic dry etching such as IE is preferable. The depth of the groove may be such that it can function as an element isolation region by embedding an insulating film in the groove as described later.
It can be adjusted as appropriate depending on the voltage applied to the semiconductor device to be obtained, performance, and the like. For example, 100-500n
m.

In the step (d), a third insulating film and a fourth insulating film are sequentially laminated on the semiconductor substrate including the groove. The third and fourth insulating films are preferably formed over the entire surface of the semiconductor substrate. However, the third and fourth insulating films may be formed at least in the region where the groove is formed, and need not necessarily be formed over the entire surface of the semiconductor substrate. The third and fourth insulating films are not particularly limited as long as they are normally used in a semiconductor device. For example, a silicon oxide film (thermal oxide film, low-temperature oxide film: LTO film, etc., high-temperature oxide film: HTO film, TEOS film,
Plasma TEOS film, etc.), silicon nitride film, SOG film,
A single-layer film or a laminated film of an insulating film such as an NSG film, a PSG film, a BSG film, or a BPSG film is given. These insulating films are formed, for example, by a thermal oxidation method, a low pressure CVD method, a normal pressure CV method.
It can be formed by various methods such as a D method, a plasma CVD method, a vacuum evaporation method, and an EB method. In particular, when the above-described protective film has a two-layer structure, the third insulating film preferably has a polishing rate lower than the polishing rate of the first protective film. The third insulating film is
The second protective film is preferably formed of the same material as the second protective film, and more preferably a silicon nitride film. Since the fourth insulating film is a film that is substantially buried in the groove and mainly forms an element isolation region, it is preferably an insulating film having a low dielectric constant, specifically, a silicon oxide film. . The thicknesses of the third and fourth insulating films are not particularly limited, and are about 10 to 50 nm and 500 to 10 nm, respectively.
About 100 nm.

In the step (e), the fourth insulating film is polished at least until the surface of the third insulating film is exposed. As a polishing method, for example, a CMP method or the like can be mentioned. Thereby, the surface of the third insulating film and the surface of the fourth insulating film embedded in the groove can be flattened. Also,
The polishing is preferably performed until the entire third insulating film is polished and the surface of the protective film is exposed. Thereby, the surface of the protective film and the surfaces of the third insulating film and the fourth insulating film embedded in the groove can be flattened. In the case where the protective film has a two-layer structure, it is preferable to perform the process until a part of the upper layer (second protective film) of the protective film is polished. Here, the part is polished can be appropriately adjusted depending on the type of the insulating film constituting the protective film,
Polishing is performed until the protective film remains about 50 to 200 nm. Thus, the surface of the second protective film and the surfaces of the third insulating film and the fourth insulating film embedded in the trench can be flattened.

In the step (f), the surface of the semiconductor substrate is exposed. Here, exposing the surface of the semiconductor substrate means removing all the protective film, the third insulating film, and the like existing on the semiconductor substrate where no groove is formed. The removal of the insulating film and the like can be performed by wet etching or dry etching. Above all, wet etching using an appropriate etchant is preferable in consideration of the thickness and type of the insulating film and the like, and the etching selectivity with other insulating films and the semiconductor substrate. Note that it is preferable that the protective film and the third insulating film be removed by a single treatment or a plurality of treatments, such as two or more treatments, depending on the kind and number of the films such as a protective film and a third insulating film. At this time, it is preferable that a portion of the third insulating film formed in the groove, which protrudes from the surface of the semiconductor substrate, is also removed at the same time, and the surface of the semiconductor substrate and the surface of the third insulating film are almost flattened. . In addition, it is preferable that a portion of the fourth insulating film formed in the groove, which protrudes from the surface of the semiconductor substrate, is also removed at the same time, so that a difference in height between the surface of the semiconductor substrate and the surface of the fourth insulating film is reduced. Preferably, both surfaces are substantially flattened.

In the method of manufacturing a semiconductor device according to the present invention, the semiconductor device can be completed by appropriately forming a transistor, an interlayer insulating film, a contact hole, a wiring and the like. Hereinafter, embodiments of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, a first silicon oxide film 2 having a thickness of about 15 nm is formed on a surface of a silicon substrate 1 by a thermal oxidation method, and a 200 nm film thickness is formed thereon by a low pressure CVD method.
A first silicon nitride film 3 of about m is deposited on the entire surface.

Subsequently, as shown in FIG. 1B, a resist pattern (not shown) having an opening in a region where an element isolation region is to be formed is formed by a normal photolithography process, and this resist pattern is formed. Using the mask as a mask, the first silicon nitride film 3 and the first silicon oxide film 2 are opened by anisotropic etching so that the silicon substrate 1 in the region where the element isolation region is to be formed is exposed.
Further, as shown in FIG. 1C, using the obtained first silicon nitride film 3 as an etching mask, the silicon substrate 1 is etched by about 300 nm by anisotropic etching to form a trench 4. Next, as shown in FIG. 1D, the entire surface of the obtained silicon substrate 1 is subjected to low pressure CVD.
A second silicon nitride film 5 having a thickness of about 30 nm by a method and a second silicon oxide film 6 having a thickness of about 700 nm by a low pressure CVD method (for example, a plasma TEOS film, an NSG film, etc.)
To form As a result, the inside of the trench 4 is buried with the second silicon nitride film 5 and the second silicon oxide film 6.

Next, as shown in FIG. 1E, the second silicon oxide film 6 and the second silicon nitride film 5 are polished by CMP using the first silicon nitride film 3 as a CMP polishing stopper film. In the CMP polishing, the polishing of the first silicon nitride film 3 is stopped halfway within a range in which the protrusion height of the silicon oxide film 6 in FIG. It is possible to prevent the surface from being polished by CMP. Also,
Since the first silicon nitride film 3 serving as a CMP polishing stopper film and the second silicon nitride film 5 formed inside the trench 4 are of the same film type, the first silicon nitride film 3 can be polished at the same polishing rate during the CMP polishing. No local level difference occurs between the nitride film 3 and the second silicon nitride film 5 (the portion in contact with). By this step, the second silicon nitride film 5 and the second silicon oxide film 6 are buried in the trench 4.

Subsequently, as shown in FIG. 1F, a part of the first silicon nitride film 3 and a part of the second silicon nitride film 5 are removed by wet etching with phosphoric acid, and the first silicon oxide film 2 is further removed. It is removed by wet etching with hydrofluoric acid to expose the silicon substrate surface 1a. At this time, the surface of the second silicon oxide film 6 is
There is a height difference of about 100 nm. The second silicon nitride film 5 can be further etched by lengthening the wet etching time with phosphoric acid, and the height (step) of the second silicon nitride film 5 protruding from the surface of the silicon substrate 1 is reduced. be able to. Also, during the step of removing the first silicon oxide film 2 with hydrofluoric acid, the second silicon oxide film 6 embedded in the trench 4 is etched to the same extent. In this step, the first silicon nitride film 3 and part of the second silicon nitride film 5 are simultaneously removed by phosphoric acid, so that the second silicon nitride film 5 corresponding to the thickness of the first silicon oxide film 2 is It is formed to protrude from the surface. In other words, the height of the second silicon nitride film 5 protruding from the surface of the silicon semiconductor substrate 1 is determined by the thickness of the first silicon oxide film 2. Since the step may cause a short circuit of a gate electrode or a wiring formed in a later step, it is preferable that the step is small. Thereafter, a MOS transistor is formed on the exposed silicon substrate surface 1a, an interlayer insulating film is formed thereon, and a contact hole, a metal wiring and the like are formed to complete a semiconductor device.

As described above, in this embodiment, the second
With the silicon nitride film 5, the silicon substrate 1 at the upper end of the trench can be completely covered without being exposed. In addition, in this method, since there is no step of etching the second silicon nitride film 5 after removing the first silicon nitride film 3 and the second silicon nitride film 5 with phosphoric acid, the silicon at the upper end of the trench is surely formed. The substrate 1 is not exposed. Further, in the above method, the second silicon nitride film 5 for preventing the silicon substrate 1 at the upper end of the trench from being exposed.
Is polished at the same time by the CMP polishing when the second silicon oxide film 6 is buried in the trench 4, and a step of forming a trench inside the trench is unnecessary, so that the number of manufacturing steps is reduced as compared with the conventional method. can do. further,
Since no sidewall is formed in the etching mask for forming the trench, the trench etching can be performed with the opening width of the etching mask for the element isolation region. Therefore, even if the miniaturization is advanced, it is possible to prevent the opening failure of the etching. .

[0022]

According to the method of manufacturing a semiconductor device of the present invention, when forming an element isolation region in a semiconductor substrate by the STI method, the inner wall of the trench can be covered with the third insulating film. Since the film is not etched, the semiconductor substrate at the upper end of the trench is surely etched to the third position.
When a transistor or the like is formed using this semiconductor substrate in a later step, electric field concentration of the gate insulating film due to partial exposure of the semiconductor substrate, gate voltage of the transistor-drain current Humps can be prevented from occurring in the characteristics, and a decrease in the threshold voltage of the transistor can be suppressed.

Further, since the third insulating film is formed simultaneously by the step of embedding the fourth insulating film in the groove, the number of steps can be simplified as compared with the conventional method, and the manufacturing cost can be reduced. It becomes possible to plan. Further, since no sidewall is formed in the trench for forming the trench, the trench can be formed with an opening width for the element isolation region, and even if the element is miniaturized, an opening defect for forming the trench is prevented. Thus, stable electrical characteristics of the transistor can be obtained, and a highly reliable semiconductor device can be manufactured.

In particular, the protective film has a two-layer structure of a second protective film / first protective film, and the second protective film and the third insulating film are formed of the first protective film.
When the polishing rate is lower than the polishing rate of the protective film, when the second protective film and the third insulating film are the same type of insulating film, the first protective film is a silicon oxide film, and the second protective film and the second When the third insulating film is a silicon nitride film, the second protective film and the third insulating film can be used as an etching stopper, thereby easily preventing the etching of the first protective film and hence the etching of the surface of the semiconductor substrate. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a schematic process sectional view of a main part for describing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIGS. 2A and 2B are a schematic plan view and a cross-sectional view of a main part for describing a problem in a conventional method of manufacturing a semiconductor device.

FIG. 3 is a schematic process sectional view of a main part for describing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate (semiconductor substrate) 1a silicon substrate surface (semiconductor substrate surface) 2 first silicon oxide film (first protection film) 3 first silicon nitride film (second protection film) 4 trench (groove) 5 second silicon nitride Film (third insulating film) 6 Second silicon oxide film (fourth insulating film)

Claims (4)

[Claims] (A) forming a first protective film and a second protective film on a semiconductor substrate;
A step of sequentially depositing a protective film; (b) a step of forming an opening in a region corresponding to an element isolation region of the first and second protective films; and (c) a step of forming an opening in the second protective film. Forming a groove in the semiconductor substrate using as a mask; (d) sequentially stacking a third insulating film and a fourth insulating film on the semiconductor substrate including the groove; (e) at least the third insulating film A semiconductor comprising: a step of polishing the fourth insulating film until a surface of the film is exposed; and (f) a step of exposing the surface of the semiconductor substrate to form an element isolation region in the semiconductor substrate. Device manufacturing method. 2. The method according to claim 1, wherein the second protective film and the third insulating film have a polishing rate lower than the polishing rate of the first protective film. 3. The method according to claim 1, wherein the second protective film and the third insulating film are the same type of insulating film. 4. The method according to claim 1, wherein the first protective film is a silicon oxide film, and the second protective film and the third insulating film are silicon nitride films.