KR100339422B1 - Method for Manufacturing Semiconductor Device - Google Patents
Method for Manufacturing Semiconductor Device Download PDFInfo
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- KR100339422B1 KR100339422B1 KR1020000012263A KR20000012263A KR100339422B1 KR 100339422 B1 KR100339422 B1 KR 100339422B1 KR 1020000012263 A KR1020000012263 A KR 1020000012263A KR 20000012263 A KR20000012263 A KR 20000012263A KR 100339422 B1 KR100339422 B1 KR 100339422B1
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- Prior art keywords
- forming
- substrate
- insulating film
- gate electrode
- photoresist
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 26
- 239000010410 layer Substances 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
본 발명은 실리사이드 형성 이후에 필드를 형성함으로서 필드의 손실을 줄여 정션 리키지를 개선하기 위한 반도체 소자의 제조 방법에 관한 것으로, 게이트 전극 및 소오스/드레인 영역이 형성된 기판상에 살리사이드 공정을 진행하는 단계와, 상기 게이트 전극 사이의 기판에 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 전면에 제 1 절연막, 제 2 절연막을 차례로 형성하고 상기 게이트 전극과 단차가 없도록 평탄화하여 그루브형상의 격리 영역을 형성하는 단계와, 상기 게이트 전극상에 전도성 물질을 형성하는 단계와, 상기 기판 전면에 제 3 절연막을 형성하고, 소오스/드레인 영역이 일정 부분 노출되도록 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 플러그를 형성하고, 상기 플러그상에 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for fabricating a semiconductor device for improving junction junctions by reducing field loss by forming a field after silicide formation, and performing a salicide process on a substrate on which a gate electrode and a source / drain region are formed. And forming a trench in the substrate between the gate electrodes, sequentially forming a first insulating film and a second insulating film on the front surface including the trench, and planarizing the gate electrode to form a groove-shaped isolation region. Forming a conductive material on the gate electrode, forming a third insulating film on the entire surface of the substrate, forming a contact hole to expose a portion of the source / drain region, and a plug inside the contact hole. Forming a metal wire on the plug; The features.
Description
본 발명은 반도체 소자에 관한 것으로, 특히 실리사이드 형성 이후에 필드를형성함으로서 필드의 손실을 줄여 정션 리키지를 개선하기 위한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for reducing junction loss by improving a field by forming a field after silicide formation.
이하, 첨부한 도면을 참고하여 종래의 기술에 따른 반도체 소자의 제조 방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.
도 1a 내지 1f는 종래의 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 1a에 도시한 바와 같이, 기판(101)상에 절연막(102), 질화막(103)을 차례로 형성하고 상기 질화막(103)상에 제 1 포토레지스트(104)를 도포한 후 노광 및 현상 공정을 거쳐 상기 제 1 포토레지스트(104)를 패터닝한다.As shown in FIG. 1A, an insulating film 102 and a nitride film 103 are sequentially formed on the substrate 101, and the first photoresist 104 is coated on the nitride film 103. Afterwards, the first photoresist 104 is patterned.
도 1b에 도시한 바와 같이, 상기 패터닝된 제 1 포토레지스트(104)를 마스크로 질화막(103), 절연막(102)을 기판(101) 표면이 일정 부분 노출되도록 선택적으로 제거하여 질화막 패턴(103a), 절연막 패턴(102a)을 형성하고, 상기 제 1 포토레지스트(104)를 제거한다.As shown in FIG. 1B, the nitrided film 103 and the insulating film 102 are selectively removed to expose a portion of the surface of the substrate 101 by using the patterned first photoresist 104 as a mask. The insulating film pattern 102a is formed, and the first photoresist 104 is removed.
이어, 상기 질화막 패턴(103a)을 마스크로 기판(101)을 일정깊이까지 제거하여 그루브 형상의 트랜치(105)를 형성한다,Subsequently, the trench 101 having a groove shape is formed by removing the substrate 101 to a predetermined depth using the nitride film pattern 103a as a mask.
도 1c에 도시한 바와 같이, 상기 트랜치(105)를 포함한 전면에 절연물질인 HDP(High Density Plasma)를 도포한 후 에치백 공정 또는 CMP 공정을 거쳐 평탄화하여 PGI(Profiled Groove Isolation)(105a)를 형성한다.As shown in FIG. 1C, a high density plasma (HDP), which is an insulating material, is applied to the entire surface including the trench 105 and then planarized through an etch back process or a CMP process to form a profiled groove isolation (PGI) 105a. Form.
이어, 상기 PGI(105a)가 형성된 기판(101)상에 게이트 절연막(106), 폴리실리콘막(107)을 차례로 형성한 후 제 2 포토레지스트(도식되지 않음)를 도포하여 노광 및 현상 공정을 거쳐 패터닝하고, 상기 패터닝된 제 2 포토레지스트를 마스크로 폴리실리콘막(107), 게이트 절연막(106)을 선택적으로 제거하여 게이트 전극(108)을 형성한 후, 상기 제 2 포토레지스트를 제거한다.Subsequently, the gate insulating film 106 and the polysilicon film 107 are sequentially formed on the substrate 101 on which the PGI 105a is formed, and then a second photoresist (not illustrated) is applied to the exposure and development processes. After patterning, the polysilicon layer 107 and the gate insulating layer 106 are selectively removed using the patterned second photoresist as a mask to form a gate electrode 108, and then the second photoresist is removed.
도 1d에 도시한 바와 같이, 상기 게이트 전극(108)을 포함한 전면에 절연물질을 형성한 후 에치백 공정을 통해 게이트 전극(108) 양측면에 측벽(109)을 형성하고, 게이트 전극(108) 양측의 기판(101)내에 이온 주입 공정을 통하여 소오스/드레인 영역(110)을 형성한다.As shown in FIG. 1D, after forming an insulating material on the entire surface including the gate electrode 108, sidewalls 109 are formed on both sides of the gate electrode 108 through an etch back process, and both sides of the gate electrode 108 are formed. The source / drain regions 110 are formed in the substrate 101 by an ion implantation process.
도 1e에 도시한 바와 같이, 상기 기판(101)의 전면에 고융점 금속 물질(Ti)을 도포한 후 열처리를 하여 실리사이드(111)를 형성하고, 다시 전면에 층간절연막(112)을 형성한다.As illustrated in FIG. 1E, a high melting point metal material Ti is coated on the entire surface of the substrate 101 and then heat treated to form a silicide 111, and then an interlayer insulating layer 112 is formed on the entire surface of the substrate 101.
이어, 상기 층간절연막(112)상에 제 3 포토레지스트(도식되지 않음)를 도포한 후 노광 및 현상 공정을 통해 상기 제 3 포토레지스트를 패터닝하고, 상기 패터닝된 제 3 포토레지스트를 마스크로 소오스/드레인 영역(110)상의 실리사이드(111)가 일정 부분 노출되도록 상기 층간절연막(112)을 선택적으로 제거하여 콘택홀(113)을 정의한다.Subsequently, after applying a third photoresist (not illustrated) on the interlayer insulating layer 112, the third photoresist is patterned through an exposure and development process, and the source / patterned third photoresist is used as a mask. The contact hole 113 is defined by selectively removing the interlayer insulating layer 112 so that the silicide 111 on the drain region 110 is partially exposed.
도 1f에 도시한 바와 같이, 상기 콘택홀(113)을 포함한 전면에 전도성 물질을 형성한 후 CMP 공정을 통하여 평탄화시켜 콘택 플러그(113a)를 형성하고, 다시 전면에 금속막을 형성한 후 제 4 포토레지스트(도식되지 않음)를 도포하고 노광 및 현상 공정을 거쳐 상기 제 4 포토레지스트를 패터닝한다.As shown in FIG. 1F, a conductive material is formed on the entire surface including the contact hole 113, and then planarized through a CMP process to form a contact plug 113a, and a metal film is formed on the entire surface. A resist (not shown) is applied and the fourth photoresist is patterned through an exposure and development process.
이어, 상기 패터닝된 제 4 포토레지스트를 마스크로 상기 금속막을 선택적으로 제거하여 콘택 플러그(113a)상에 금속 배선(114)을 형성하고, 상기 패터닝된 제 4 포토레지스트를 제거한다.Next, the metal layer is selectively removed using the patterned fourth photoresist as a mask to form a metal interconnect 114 on the contact plug 113a, and the patterned fourth photoresist is removed.
그러나 상기와 같은 종래의 반도체 소자의 제조 방법에 있어서 다음과 같은 문제점이 있다.However, in the conventional method of manufacturing a semiconductor device as described above has the following problems.
상기 제조 공정 중에서 PGI 형성 후에 다른 나머지 공정들이 진행되기 때문에 필드 로스(Field Loss)가 매 공정마다 발생하게 되어 정션 리키지가 증가하게 되는 문제점이 있다.Since other processes are performed after the formation of PGI in the manufacturing process, field loss occurs in every process, thereby increasing the junction solution.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 실리사이드를 형성한 이후에 필드를 형성함으로서 필드의 손실을 최소한으로 줄여 정션 리키지를 개선하는데 그 목적이 있다.The present invention has been made to solve the above problems is to form a field after forming the silicide to minimize the loss of the field to improve the junction solution.
도 1a 내지 1f는 종래의 기술에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2a 내지 2f는 본 발명에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
201 : 기판 202 : 게이트 절연막201: substrate 202: gate insulating film
203 : 폴리실리콘막 204 : 게이트 전극203: polysilicon film 204: gate electrode
205 : 측벽 206 : 소오스/드레인 영역205 sidewalls 206 source / drain regions
207 : 실리사이드 208 : 질화막207: silicide 208: nitride film
209 : 제 1 절연막 210 : 제 1 금속막209: first insulating film 210: first metal film
211 : 제 2 절연막 212 : 콘택홀211: second insulating film 212: contact hole
212a : 콘택 플러그 213 : 금속배선212a: contact plug 213: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조 방법은 게이트 전극 및 소오스/드레인 영역이 형성된 기판상에 살리사이드 공정을 진행하는 단계와, 상기 게이트 전극 사이의 기판에 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 전면에 제 1 절연막, 제 2 절연막을 차례로 형성하고 상기 게이트 전극과 단차가 없도록 평탄화하여 그루브형상의 격리 영역을 형성하는 단계와, 상기 게이트 전극상에 전도성 물질을 형성하는 단계와, 상기 기판 전면에 제 3 절연막을 형성하고, 소오스/드레인 영역이 일정 부분 노출되도록 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 플러그를 형성하고, 상기 플러그상에 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to perform a salicide process on a substrate on which a gate electrode and a source / drain region are formed, and forming a trench in the substrate between the gate electrodes. Forming a groove-shaped isolation region by sequentially forming a first insulating film and a second insulating film on the entire surface including the trench and planarizing the gate electrode so that there is no step difference; and forming a conductive material on the gate electrode. Forming a third insulating film on the entire surface of the substrate, forming a contact hole to expose a portion of the source / drain region, forming a plug inside the contact hole, and forming a metal wiring on the plug. Characterized in that comprises a step.
이하, 첨부된 도면을 참고하여 반도체 소자의 제조 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device will be described in detail with reference to the accompanying drawings.
도 2a 내지 2f는 본 발명에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 기판(201)상에 게이트 절연막(202), 폴리실리콘막(203)을 차례로 형성하고, 상기 폴리실리콘막(203)상에 제 1 포토레지스트(도식되지 않음)를 도포한 후 노광 및 현상 공정을 거쳐 상기 제 1 포토레지스트를 패터닝한다.As shown in FIG. 2A, a gate insulating film 202 and a polysilicon film 203 are sequentially formed on the substrate 201, and a first photoresist (not illustrated) is formed on the polysilicon film 203. After coating, the first photoresist is patterned through an exposure and development process.
상기 패터닝된 제 1 포토레지스트를 마스크로 폴리실리콘막(203)과 상기 게이트 절연막(202)을 기판(201) 표면이 일정 부분 노출되도록 선택적으로 제거하여 게이트 전극(204)을 형성한다.The gate electrode 204 is formed by selectively removing the polysilicon layer 203 and the gate insulating layer 202 so that the surface of the substrate 201 is partially exposed using the patterned first photoresist as a mask.
도 2b에 도시한 바와 같이, 상기 게이트 전극(204)을 포함한 전면에 절연막을 형성한 후 에치백 공정을 통해 게이트 전극(204)의 양측면에 측벽(205)을 형성하고, 게이트 전극(204) 양측의 기판(201)내에 이온 주입 공정을 통하여 소오스/드레인 영역(206)을 형성한다.As shown in FIG. 2B, after forming an insulating film on the entire surface including the gate electrode 204, sidewalls 205 are formed on both sides of the gate electrode 204 through an etch back process, and both sides of the gate electrode 204 are formed. The source / drain regions 206 are formed in the substrate 201 through an ion implantation process.
이어, 기판(201) 전면에 살리사이드(Self Align Silicide) 공정을 통하여 게이트 전극(204)과 소오스/드레인 영역(206)에 실리사이드(207)를 형성한다.Subsequently, the silicide 207 is formed in the gate electrode 204 and the source / drain regions 206 through a salicide process on the entire surface of the substrate 201.
상기 살리사이드 공정은 기판에 고융점 금속 물질을 도포하여 열처리 과정을 거쳐 실리사이드를 형성하는 공정으로 고융점 금속 물질이 실리콘과 반응하는 성질을 이용한 것이다.The salicide process is a process of forming a silicide by applying a high melting point metal material to a substrate and performing a heat treatment process to utilize the property of the high melting point metal material to react with silicon.
즉, 폴리실리콘으로 이루어진 게이트 전극(204)과 실리콘인 기판(201)의 소오스/드레인 영역(206)의 표면에서만 고융점 금속 물질이 반응하여 실리사이드(207)를 형성하게 된다.That is, the high melting point metal material reacts only on the surface of the gate electrode 204 made of polysilicon and the source / drain region 206 of the silicon substrate 201 to form the silicide 207.
도 2c에 도시한 바와 같이, 전면에 제 3 포토레지스트(도식되지 않음)를 도포한 후 노광 및 현상 공정을 통하여 상기 제 3 포토레지스트를 패터닝한다.As shown in FIG. 2C, after applying a third photoresist (not shown) to the entire surface, the third photoresist is patterned through an exposure and development process.
상기 패터닝된 제 3 포토레지스트를 마스크로 기판(201)을 일정깊이까지 제거하여 그루브(groove) 형상의 트랜치를 형성한다.The patterned third photoresist is removed using a mask to remove the substrate 201 to a predetermined depth to form a groove-shaped trench.
이어, 상기 패터닝된 제 3 포토레지스트를 제거하고, 상기 트랜치를 포함한 전면에 질화막(208)과 층간 절연막인 제 1 절연막(209)을 차례로 형성한 후 상기 게이트 전극(204)상의 실리사이드(207)를 앤드 포인트로 CMP 공정을 실시하여 평탄화시킨다.Subsequently, the patterned third photoresist is removed, a nitride film 208 and a first insulating film 209 which are interlayer insulating films are sequentially formed on the entire surface including the trench, and then the silicide 207 on the gate electrode 204 is formed. The end point is planarized by performing a CMP process.
도 2d에 도시한 바와 같이, 필드 폴리를 연결해 주기 위한 전도성 물질인 제 1 금속막(210)을 게이트 전극(204)의 실리사이드(207)상에만 형성한다.As shown in FIG. 2D, the first metal film 210, which is a conductive material for connecting the field poly, is formed only on the silicide 207 of the gate electrode 204.
도 2e에 도시한 바와 같이, 상기 제 1 금속막(210)을 포함한 전면에 층간 절연막인 제 2 절연막(211)을 형성하고, 상기 제 2 절연막(211)상에 제 4 포토레지스트(도식되지 않음)를 도포하여 노광 및 현상 공정을 통해 상기 제 4 포토레지스트를 패터닝한다.As shown in FIG. 2E, a second insulating film 211, which is an interlayer insulating film, is formed on the entire surface including the first metal film 210, and a fourth photoresist (not illustrated) is formed on the second insulating film 211. ) And pattern the fourth photoresist through an exposure and development process.
상기 패터닝된 제 4 포토레지스트를 마스크로 상기 제 2 절연막(211), 제 1 절연막(209), 질화막(208)을 상기 소오스/드레인 영역(206)이 일정부분 노출되도록선택적으로 제거하여 콘택홀(212)을 정의한다.By using the patterned fourth photoresist as a mask, the second insulating layer 211, the first insulating layer 209, and the nitride layer 208 are selectively removed so that the source / drain region 206 is partially exposed to the contact hole. 212).
도 2g에 도시한 바와 같이, 상기 콘택홀(212)을 포함한 전면에 전도성 물질을 형성한 후, CMP 공정을 통하여 콘택 플러그(212a)를 형성한다.As shown in FIG. 2G, after the conductive material is formed on the entire surface including the contact hole 212, the contact plug 212a is formed through the CMP process.
이어, 전면에 제 2 금속막을 형성하고, 상기 제 2 금속막상에 제 5 포토레지스트(도식되지 않음)를 도포한 후 노광 및 현상 공정을 통해 상기 제 5 포토레지스트를 패터닝한다.Subsequently, a second metal film is formed on the entire surface, and a fifth photoresist (not illustrated) is applied on the second metal film, and then the fifth photoresist is patterned through an exposure and development process.
상기 패터닝된 제 5 포토레지스트를 마스크로 제 2 금속막을 선택적으로 제거하여 콘택 플러그(212a)상에 기판(201)과 전기적으로 연결되는 금속 배선(213)을 형성한다.The second metal layer is selectively removed using the patterned fifth photoresist as a mask to form a metal wire 213 electrically connected to the substrate 201 on the contact plug 212a.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조 방법에 있어서 다음과 같은 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention has the following effects.
첫째, 실리사이드 형성 이후에 PGI 형성 단계를 진행함으로서 필드가 실리사이드 형성 이후에 형성되어 필드 로스가 없어지므로 정션 리키지를 개선하는 효과가 있다.First, since the PGI formation step is performed after silicide formation, a field is formed after silicide formation, thereby eliminating field loss, thereby improving junction liquidity.
둘째, PGI CMP공정에서 버퍼로 사용되는 질화막이 보더 레스 콘택(Border Less Contact)을 위한 물질로도 동시에 사용될 수 있는 효과가 있다.Second, the nitride film used as a buffer in the PGI CMP process can be used simultaneously as a material for borderless contact.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03203322A (en) * | 1989-12-29 | 1991-09-05 | Sony Corp | Manufacture of semiconductor device |
| JPH07263540A (en) * | 1994-03-24 | 1995-10-13 | Matsushita Electron Corp | Dielectric separation substrate and semiconductor device using that substrate, and manufacture thereof |
| JPH07312353A (en) * | 1994-05-17 | 1995-11-28 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| KR980012244A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03203322A (en) * | 1989-12-29 | 1991-09-05 | Sony Corp | Manufacture of semiconductor device |
| JPH07263540A (en) * | 1994-03-24 | 1995-10-13 | Matsushita Electron Corp | Dielectric separation substrate and semiconductor device using that substrate, and manufacture thereof |
| JPH07312353A (en) * | 1994-05-17 | 1995-11-28 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| KR980012244A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | Method for manufacturing semiconductor device |
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