KR100273325B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR100273325B1 KR100273325B1 KR1019980052207A KR19980052207A KR100273325B1 KR 100273325 B1 KR100273325 B1 KR 100273325B1 KR 1019980052207 A KR1019980052207 A KR 1019980052207A KR 19980052207 A KR19980052207 A KR 19980052207A KR 100273325 B1 KR100273325 B1 KR 100273325B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- layer
- drain
- insulating layer
- polysilicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 80
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010937 tungsten Substances 0.000 abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 5
- 101000831940 Homo sapiens Stathmin Proteins 0.000 description 4
- 102100024237 Stathmin Human genes 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 종래에는 내부접속층과 콘택의 단락을 방지하기 위해 층간절연막을 통해 절연해야 함으로써, 사진식각공정, 배리어 금속층과 텅스텐 증착공정 및 텅스텐 평탄화공정이 추가로 요구되어 공정이 복잡한 문제점이 있었고, 내부접속층의 오정렬로 인해 소스/드레인과 게이트의 단선이 발생될 수 있는 문제점이 있었다. 따라서, 본 발명은 일반적인 트랜지스터가 형성되는 제1액티브영역과 내부접속층이 형성될 트랜지스터가 형성되는 제2액티브영역의 반도체기판 상부에 제1절연막을 증착한 후, 사진식각공정을 통해 게이트가 형성될 영역을 식각하는 공정과; 상기 제1절연막의 식각된 영역에 게이트절연막과 제1폴리실리콘이 적층된 게이트를 형성한 후, 제1절연막을 절반정도 식각하는 공정과; 상기 제2액티브영역의 게이트 일측 반도체기판 상부에 형성된 제1절연막을 식각한 후, 그 구조물의 상부전면에 제2폴리실리콘을 증착하는 공정과; 상기 제2폴리실리콘 및 제1절연막을 선택적으로 식각하여 제2액티브영역의 게이트 일측면에 제1측벽을 형성함과 동시에 그 게이트의 타측면 및 제1액티브영역의 게이트 양측면에 제2측벽을 형성하는 공정과; 상기 게이트 및 제1,제2측벽을 마스크로 하여 반도체기판 내에 저농도의 불순물이온을 경사지게 주입한 후, 고농도의 불순물이온을 주입하여 엘디디영역 및 소스/드레인을 형성하는 공정과; 상기 엘디디영역 및 소스/드레인이 형성된 구조물의 상부전면에 살리사이드공정을 적용하여 소스/드레인, 제1,제2측벽 및 게이트 상에 실리사이드층을 형성하는 공정과; 상기 실리사이드층이 형성된 구조물의 상부전면에 층간절연막을 증착하여 평탄화한 후, 사진식각공정을 통해 제1,제2액티브영역의 게이트 타측면 반도체기판 내에 형성된 소스/드레인이 노출되도록 층간절연막을 식각하는 공정과; 상기 층간절연막이 식각된 구조물의 상부전면에 도전성물질을 증착한 후, 평탄화하여 콘택을 형성하는 공정으로 이루어지는 반도체소자의 제조방법을 제공함으로써, 1번의 층간절연막 증착을 통해 게이트의 제1측벽으로 형성되는 내부접속층과 콘택의 단락을 방지함과 아울러 내부접속층을 게이트의 제1측벽으로 형성함에 따라 내부접속층의 오정렬에 대한 우려를 해결할 수 있게 되므로, 종래 2번의 배리어 금속층과 텅스텐 증착공정 및 텅스텐 평탄화공정을 1번으로 줄일 수 있어 제조비용의 절감 및 생산성 향상에 기여할 수 있고, 제1,2액티브영역의 게이트측면에 질화막과 폴리실리콘이 적층된 제2측벽을 형성하여 게이트 상부에 형성되는 실리사이드층의 면적을 넓게 할 수 있어 게이트저항을 감소시킬 수 있는 효과가 있다.The present invention relates to a method for manufacturing a semiconductor device, and in the related art, the insulating layer must be insulated through an interlayer insulating film to prevent a short circuit between the internal connection layer and the contact. There was a problem that the process is complicated, and there is a problem that the disconnection of the source / drain and the gate may occur due to the misalignment of the internal connection layer. Accordingly, in the present invention, a gate is formed through a photolithography process after depositing a first insulating layer on the semiconductor substrate of a first active region in which a general transistor is formed and a second active region in which a transistor in which an internal connection layer is to be formed. Etching the region to be; Forming a gate in which the gate insulating layer and the first polysilicon are stacked in the etched region of the first insulating layer, and then etching the first insulating layer about halfway; Etching the first insulating layer formed on the semiconductor substrate on one side of the gate of the second active region, and then depositing second polysilicon on the upper surface of the structure; Selectively etching the second polysilicon and the first insulating layer to form a first side wall on one side of the gate of the second active region, and a second side wall on the other side of the gate and both sides of the gate of the first active region Process of doing; Implanting obliquely low concentrations of impurity ions into the semiconductor substrate using the gate and the first and second sidewalls as masks, and then implanting high concentrations of impurity ions to form an LED area and a source / drain; Forming a silicide layer on the source / drain, the first and second sidewalls and the gate by applying a salicide process to the upper surface of the structure where the LED area and the source / drain are formed; Depositing and planarizing an interlayer insulating film on the upper surface of the structure on which the silicide layer is formed, and then etching the interlayer insulating film to expose the source / drain formed in the semiconductor substrate on the other side of the gate of the first and second active regions through a photolithography process. Process; A method of manufacturing a semiconductor device, comprising: depositing a conductive material on an upper surface of a structure in which the interlayer insulating film is etched, and then planarizing and forming a contact, thereby forming the first side wall of the gate through first interlayer insulating film deposition. As a result of preventing the short circuit between the interconnection layer and the contact and the formation of the interconnection layer as the first side wall of the gate, concerns about misalignment of the interconnection layer can be solved. The tungsten flattening process can be reduced to one time, contributing to the reduction of manufacturing cost and the improvement of productivity. A second side wall in which the nitride film and the polysilicon are formed on the gate side of the first and second active regions is formed on the gate. Since the area of the silicide layer can be increased, the gate resistance can be reduced.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 전체적인 공정을 단순화하여 실리사이드(silicide)가 형성되는 일반적인 트랜지스터의 게이트저항을 감소시킴과 동시에 실리사이드 및 소스/드레인과 게이트를 접속시키는 국부적인 내부접속층(local interconnection layer)이 형성되는 트랜지스터의 내부접속층 정렬마진을 확보하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a local internal connection layer which connects the silicide and the source / drain and the gate while reducing the gate resistance of a general transistor in which silicide is formed by simplifying the overall process. The present invention relates to a method for fabricating a semiconductor device suitable for securing an alignment margin of an internal connection layer of a transistor in which a local interconnection layer is formed.
종래 반도체소자의 제조방법을 도1a 내지 도1i에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view shown in FIGS. 1A to 1I as follows.
먼저, 도1a에 도시한 바와같이 일반적인 트랜지스터가 형성되는 제1액티브영역과 내부접속층이 형성될 트랜지스터가 형성되는 제2액티브영역의 반도체기판(1) 상부에 게이트산화막(2)과 폴리실리콘(3)이 적층된 게이트를 각기 형성하고, 그 게이트를 마스크로 하여 반도체기판(1) 내에 저농도 불순물이온을 주입한 후, 상기 게이트의 양측면에 절연물질의 측벽(4)을 형성하고, 그 게이트와 측벽(4)을 마스크로 하여 반도체기판(1) 내에 고농도 불순물이온을 주입하여 엘디디(lightly doped drain:LDD)영역(5) 및 소스/드레인(6)을 형성한다. 이때, 게이트 및 측벽(4)을 마스크로 이용하여 형성된 엘디디영역(5)은 반도체소자의 고집적화에 대한 요구로 소자의 각 영역들을 한계면적까지 줄임에 따라 채널길이 감소에 의해 발생하는 단채널효과(short channel effect)를 완화시키게 된다.First, as shown in FIG. 1A, a gate oxide film 2 and a polysilicon layer are formed on the semiconductor substrate 1 on the first active region in which a general transistor is formed and the second active region in which a transistor in which an internal connection layer is to be formed. Each of the gates 3) is laminated, and low concentration impurity ions are implanted into the semiconductor substrate 1 using the gate as a mask, and then sidewalls 4 of an insulating material are formed on both sides of the gate. High concentration impurity ions are implanted into the semiconductor substrate 1 using the sidewalls 4 as a mask to form the lightly doped drain (LDD) region 5 and the source / drain 6. In this case, the LED area 5 formed by using the gate and sidewalls 4 as a mask has a short channel effect caused by the reduction in the channel length as each area of the device is reduced to the limit area in response to a demand for high integration of the semiconductor device. (short channel effect) is alleviated.
그리고, 도1b에 도시한 바와같이 상기 폴리실리콘(3) 및 소스/드레인(6) 상에 자기정렬되는 실리사이드(self-aligned silicide : SALICIDE)공정을 적용하여 실리사이드층(7)을 형성한다. 이때, 자기정렬되는 실리사이드(즉, 살리사이드)공정이란 상기 게이트 및 소스/드레인(6)이 형성된 반도체기판(1)의 상부전면에 금속층을 증착하고 열처리하게 되면 금속과 실리콘은 반응하여 게이트 및 소스/드레인(6) 상에 실리사이드층(7)으로 형성되지만, 금속과 측벽(4) 또는 금속과 필드산화막(도면 미도시)등은 반응이 이루어지지 않아 금속층으로 잔류하는 성질을 이용하여 실리사이드층(7)을 형성하고, 잔류하는 금속층을 습식식각등을 통해 제거하는 일련의 공정을 지칭한다.1B, a silicide layer 7 is formed by applying a self-aligned silicide (SALICIDE) process on the polysilicon 3 and the source / drain 6. In this case, the self-aligned silicide (ie, salicide) process is a metal layer deposited on the upper surface of the semiconductor substrate 1 on which the gate and the source / drain 6 are formed and heat treated. Although the silicide layer 7 is formed on the drain 6, the metal and the sidewall 4 or the metal and the field oxide film (not shown) are not reacted and remain as a metal layer. 7) refers to a series of processes for forming and removing the remaining metal layer by wet etching.
그리고, 도1c에 도시한 바와같이 상기 실리사이드층(7)이 형성된 구조물의 상부전면에 층간절연막(8)을 증착한 후, 화학기계적 연마(chemical mechanical polishing : CMP)하여 평탄화한다.As shown in FIG. 1C, an interlayer insulating film 8 is deposited on the upper surface of the structure on which the silicide layer 7 is formed, and then planarized by chemical mechanical polishing (CMP).
그리고, 도1d에 도시한 바와같이 상기 층간절연막(8)의 상부전면에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴(PR1)을 형성하고, 그 감광막 패턴(PR1)을 적용하여 층간절연막(8)을 식각한다. 이때, 제2액티브영역은 감광막 패턴(PR1)에 의해 상기 소스/드레인(6)의 일측(즉, 게이트 상부 실리사이드층(7)과 접속될 영역) 실리사이드층(7)은 상기 게이트 상부 실리사이드층(7) 및 측벽(4)과 함께 노출되며, 소스/드레인(6)의 타측(즉, 콘택 형성영역) 실리사이드층(7)은 상기 게이트 상부 실리사이드층(7) 및 측벽(4)과 층간절연막(8)을 통해 이격되어 노출되고, 제1액티브영역은 소스/드레인(6)의 타측(즉, 콘택 형성영역) 실리사이드층(7)만이 상기 게이트 상부 실리사이드층(7) 및 측벽(4)과 층간절연막(8)을 통해 이격되어 노출되며, 이후 감광막 패턴(PR1)을 제거한다.Then, as shown in FIG. 1D, a photoresist film is coated on the upper surface of the interlayer insulation film 8, and then exposed and developed to form a photoresist pattern PR1, and the photoresist pattern PR1 is applied to the interlayer insulation film ( Etch 8). In this case, the second active region is formed on one side of the source / drain 6 (ie, the region to be connected to the gate upper silicide layer 7) by the photoresist pattern PR1. The silicide layer 7 is formed on the gate upper silicide layer ( 7) and the sidewall 4 and the other side (ie, contact formation region) silicide layer 7 of the source / drain 6 are formed on the gate upper silicide layer 7 and the sidewall 4 and the interlayer insulating film ( 8) is spaced apart and exposed, and the first active region is the only side (i.e., contact forming region) silicide layer 7 of the source / drain 6 and between the gate top silicide layer 7 and the sidewalls 4 The photoresist pattern PR1 is removed after being exposed through the insulating layer 8.
그리고, 도1e에 도시한 바와같이 상기 감광막 패턴(PR1)에 의해 층간절연막(8)이 식각된 구조물의 상부전면에 배리어(barrier) 금속층과 텅스텐을 증착한 후, 화학기계적 연마하여 평탄화함으로써, 상기 제2액티브영역에 소스/드레인(6)의 일측과 게이트가 접속되는 내부접속층(9) 및 소스/드레인(6)의 타측상에 콘택(10)을 형성함과 동시에 제1액티브영역 소스/드레인의 타측상에 콘택(10)을 형성한다.As shown in FIG. 1E, a barrier metal layer and tungsten are deposited on the upper surface of the structure in which the interlayer insulating film 8 is etched by the photosensitive film pattern PR1, and then chemically polished and planarized. The first active region source / drain is formed at the same time as the contact 10 is formed on the internal connection layer 9 and the other side of the source / drain 6 where one side of the source / drain 6 and the gate are connected to the second active region. The contact 10 is formed on the other side of the drain.
그리고, 도1f에 도시한 바와같이 상기 층간절연막(8) 사이에 내부접속층(9) 및 콘택(10)이 형성된 구조물의 상부전면에 층간절연막(11)을 증착하고, 그 층간절연막(11)의 상부에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴(PR2)을 형성하고, 그 감광막 패턴(PR2)을 적용하여 층간절연막(11)을 식각한다. 이때, 감광막 패턴(PR2)에 의해 제1,제2액티브영역에 형성된 콘택(10)이 노출되며, 이후 감광막 패턴(PR2)을 제거한다.1F, an interlayer insulating film 11 is deposited on the upper surface of the structure in which the internal connection layer 9 and the contact 10 are formed between the interlayer insulating films 8, and the interlayer insulating film 11 is formed. After the photoresist is coated on the upper portion of the photoresist, the photoresist pattern PR2 is formed by exposure and development, and the interlayer insulating film 11 is etched by applying the photoresist pattern PR2. In this case, the contact 10 formed in the first and second active regions is exposed by the photoresist pattern PR2, and then the photoresist pattern PR2 is removed.
그리고, 도1g에 도시한 바와같이 상기 층간절연막(11) 사이로 콘택(10)이 노출된 구조물의 상부전면에 배리어 금속층과 텅스텐을 증착한 후, 에치-백(etch-back) 또는 화학기계적 연마하여 평탄화함으로써, 상기 제1,제2액티브영역의 콘택(10) 상부에 콘택(12)을 형성한다.As shown in FIG. 1G, a barrier metal layer and tungsten are deposited on the upper surface of the structure in which the contact 10 is exposed between the interlayer insulating layers 11, and then etch-back or chemical mechanical polishing. By planarizing, the contact 12 is formed on the contact 10 of the first and second active regions.
그리고, 도1h에 도시한 바와같이 상기 층간절연막(11) 사이에 콘택(12)이 형성된 구조물의 상부전면에 금속배선(13)을 증착하고, 그 금속배선(13)의 상부에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴(PR3)을 형성하고, 그 감광막 패턴(PR3)을 적용하여 금속배선(13)을 식각한다. 이때, 감광막 패턴(PR3)에 의해 패터닝된 금속배선(13)은 상기 제1,제2액티브영역의 콘택(12) 상부에서 접촉됨과 아울러 제2액티브영역은 층간절연막(11)을 통해 내부접속층(9)과 절연될 수 있으므로, 콘택(10,12)보다 넓은 폭으로 구현된다.As shown in FIG. 1H, a metal wiring 13 is deposited on the upper surface of the structure in which the contact 12 is formed between the interlayer insulating films 11, and a photosensitive film is coated on the metal wiring 13. Subsequently, the photosensitive film pattern PR3 is formed by exposure and development, and the metal wiring 13 is etched by applying the photosensitive film pattern PR3. At this time, the metal wiring 13 patterned by the photoresist pattern PR3 is in contact with the upper portion of the contact 12 of the first and second active regions, and the second active region is formed through the interlayer insulating layer 11. Since it can be insulated from (9), it is implemented in a wider width than the contacts (10, 12).
그리고, 도1i에 도시한 바와같이 상기 감광막 패턴(PR3)을 제거한다.As shown in FIG. 1I, the photoresist pattern PR3 is removed.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 내부접속층과 콘택의 단락을 방지하기 위해 층간절연막을 통해 절연해야 함으로써, 사진식각공정, 배리어 금속층과 텅스텐 증착공정 및 텅스텐 평탄화공정이 추가로 요구되어 공정이 복잡한 문제점이 있었고, 내부접속층의 오정렬(mis-align)로 인해 소스/드레인과 게이트의 단선이 발생될 수 있는 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device as described above requires insulation through an interlayer insulating film to prevent a short circuit between the internal connection layer and the contact, thereby requiring a photolithography process, a barrier metal layer and a tungsten deposition process, and a tungsten planarization process. As a result, the process was complicated and there was a problem in that disconnection of the source / drain and the gate could occur due to misalignment of the internal connection layer.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 전체적인 공정을 단순화하여 실리사이드가 형성되는 일반적인 트랜지스터의 게이트저항을 감소시킴과 동시에 실리사이드 및 소스/드레인과 게이트를 접속시키는 국부적인 내부접속층이 형성되는 트랜지스터의 내부접속층 정렬마진을 확보할 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to simplify the overall process to reduce the gate resistance of a common transistor in which silicide is formed, and at the same time to remove silicide and source / drain and gate. The present invention provides a method of manufacturing a semiconductor device capable of securing an internal connection layer alignment margin of a transistor in which a local internal connection layer to be connected is formed.
도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21:반도체기판 22:질화막21: semiconductor substrate 22: nitride film
23:게이트산화막 24,25:폴리실리콘23: gate oxide film 24, 25: polysilicon
26:엘디디영역 27:소스/드레인26: LED area 27: source / drain
28:실리사이드층 29:층간절연막28: silicide layer 29: interlayer insulating film
30:콘택 31:금속배선30: contact 31: metal wiring
PR21∼PR23:감광막 패턴PR21-PR23: Photosensitive film pattern
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 일반적인 트랜지스터가 형성되는 제1액티브영역과 내부접속층이 형성될 트랜지스터가 형성되는 제2액티브영역의 반도체기판 상부에 제1절연막을 증착한 후, 사진식각공정을 통해 게이트가 형성될 영역을 식각하는 공정과; 상기 제1절연막의 식각된 영역에 게이트절연막과 제1폴리실리콘이 적층된 게이트를 형성한 후, 제1절연막을 절반정도 식각하는 공정과; 상기 제2액티브영역의 게이트 일측 반도체기판 상부에 형성된 제1절연막을 식각한 후, 그 구조물의 상부전면에 제2폴리실리콘을 증착하는 공정과; 상기 제2폴리실리콘 및 제1절연막을 선택적으로 식각하여 제2액티브영역의 게이트 일측면에 제1측벽을 형성함과 동시에 그 게이트의 타측면 및 제1액티브영역의 게이트 양측면에 제2측벽을 형성하는 공정과; 상기 게이트 및 제1,제2측벽을 마스크로 하여 반도체기판 내에 저농도의 불순물이온을 경사지게 주입한 후, 고농도의 불순물이온을 주입하여 엘디디영역 및 소스/드레인을 형성하는 공정과; 상기 엘디디영역 및 소스/드레인이 형성된 구조물의 상부전면에 살리사이드공정을 적용하여 소스/드레인, 제1,제2측벽 및 게이트 상에 실리사이드층을 형성하는 공정과; 상기 실리사이드층이 형성된 구조물의 상부전면에 층간절연막을 증착하여 평탄화한 후, 사진식각공정을 통해 제1,제2액티브영역의 게이트 타측면 반도체기판 내에 형성된 소스/드레인이 노출되도록 층간절연막을 식각하는 공정과; 상기 층간절연막이 식각된 구조물의 상부전면에 도전성물질을 증착한 후, 평탄화하여 콘택을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A preferred embodiment of the method of manufacturing a semiconductor device for achieving the object of the present invention as described above is the upper portion of the semiconductor substrate of the first active region in which a general transistor is formed and the second active region in which a transistor in which an internal connection layer is to be formed is formed. Depositing a first insulating layer on the substrate, and etching the region where the gate is to be formed by a photolithography process; Forming a gate in which the gate insulating layer and the first polysilicon are stacked in the etched region of the first insulating layer, and then etching the first insulating layer about halfway; Etching the first insulating layer formed on the semiconductor substrate on one side of the gate of the second active region, and then depositing second polysilicon on the upper surface of the structure; Selectively etching the second polysilicon and the first insulating layer to form a first side wall on one side of the gate of the second active region, and a second side wall on the other side of the gate and both sides of the gate of the first active region Process of doing; Implanting obliquely low concentrations of impurity ions into the semiconductor substrate using the gate and the first and second sidewalls as masks, and then implanting high concentrations of impurity ions to form an LED area and a source / drain; Forming a silicide layer on the source / drain, the first and second sidewalls and the gate by applying a salicide process to the upper surface of the structure where the LED area and the source / drain are formed; Depositing and planarizing an interlayer insulating film on the upper surface of the structure on which the silicide layer is formed, and then etching the interlayer insulating film to expose the source / drain formed in the semiconductor substrate on the other side of the gate of the first and second active regions through a photolithography process. Process; And depositing a conductive material on the upper surface of the structure in which the interlayer insulating film is etched, and then planarizing to form a contact.
상기한 바와같은 본 발명의 일 실시예에 따른 반도체소자 제조방법의 바람직한 일 실시예를 도2a 내지 도2j의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of manufacturing a semiconductor device according to an embodiment of the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2J.
먼저, 도2a에 도시한 바와같이 일반적인 트랜지스터가 형성되는 제1액티브영역과 내부접속층이 형성될 트랜지스터가 형성되는 제2액티브영역의 반도체기판(21) 상부에 절연막으로 질화막(22)을 증착하고, 그 질화막(22)의 상부에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴(PR21)을 형성하고, 그 감광막 패턴(PR21)을 적용하여 질화막(22)을 식각함으로써, 제1,제2액티브영역에 게이트가 형성될 영역을 정의한다.First, as shown in FIG. 2A, a nitride film 22 is deposited on the semiconductor substrate 21 of the first active region in which a general transistor is formed and the second active region in which a transistor in which an internal connection layer is to be formed is formed. After the photoresist film is applied on the nitride film 22, the photoresist film pattern PR21 is formed by exposing and developing the photoresist film. The nitride film 22 is etched by applying the photoresist pattern PR21 to the first and second electrodes. A region in which a gate is to be formed is defined in the active region.
그리고, 도2b에 도시한 바와같이 상기 감광막 패턴(PR21)을 제거하고, 질화막(22)의 식각으로 노출된 반도체기판(21)을 산화시켜 게이트산화막(23)을 성장시킨 후, 그 구조물의 상부전면에 폴리실리콘(24)을 증착하고, 에치-백 또는 화학기계적 연마를 통해 평탄화하여 게이트를 형성한다.As shown in FIG. 2B, the photoresist pattern PR21 is removed, the semiconductor substrate 21 exposed by the etching of the nitride film 22 is oxidized, the gate oxide film 23 is grown, and the upper portion of the structure is formed. Polysilicon 24 is deposited on the front surface and planarized through etch-back or chemical mechanical polishing to form a gate.
그리고, 도2c에 도시한 바와같이 상기 질화막(22)을 절반정도 식각하고, 그 구조물의 상부전면에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴(PR22)을 형성하고, 그 감광막 패턴(PR22)을 적용하여 질화막(22)을 식각한다. 이때, 감광막 패턴(PR22)은 제2액티브영역의 게이트 일측 반도체기판(21)의 상부에 형성된 질화막(22)을 노출시키게 형성한다.As shown in FIG. 2C, the nitride film 22 is etched about halfway, a photoresist film is applied to the upper surface of the structure, and then exposed and developed to form a photoresist pattern PR22, and the photoresist pattern PR22. Is applied to etch the nitride film 22. In this case, the photoresist pattern PR22 is formed to expose the nitride film 22 formed on the semiconductor substrate 21 on one side of the gate of the second active region.
그리고, 도2d에 도시한 바와같이 상기 감광막 패턴(PR22)을 제거한 후, 그 구조물의 상부에 폴리실리콘(25)을 증착한다.After removing the photoresist pattern PR22 as shown in FIG. 2D, polysilicon 25 is deposited on the structure.
그리고, 도2e에 도시한 바와같이 상기 폴리실리콘(25) 및 질화막(22)을 선택적으로 식각하여 제2액티브영역의 게이트 일측면에 폴리실리콘(25)의 제1측벽을 형성함과 동시에 그 게이트의 타측면 및 제1액티브영역의 게이트 양측면에 질화막(22)과 폴리실리콘(25)이 적층된 제2측벽을 형성한다. 이때, 폴리실리콘(25)의 제1측벽은 상기 폴리실리콘(24)과 이후에 형성되는 엘디디영역(26) 및 소스/드레인(27)을 국부적으로 접속시키는 내부접속층이 된다.As shown in FIG. 2E, the polysilicon 25 and the nitride film 22 are selectively etched to form a first side wall of the polysilicon 25 on one side of the gate of the second active region, and the gate thereof. The second side wall on which the nitride film 22 and the polysilicon 25 are laminated is formed on the other side of the gate and on both sides of the gate of the first active region. At this time, the first side wall of the polysilicon 25 is an internal connection layer for locally connecting the polysilicon 24 to the LED region 26 and the source / drain 27 formed thereafter.
그리고, 도2f에 도시한 바와같이 상기 게이트 및 제1,제2측벽을 마스크로 하여 반도체기판(21) 내에 저농도의 불순물이온을 경사지게 주입한 후, 고농도의 불순물이온을 주입하여 엘디디영역(26) 및 소스/드레인(27)을 형성한다. 이때, 엘디디영역(26)을 형성하는 이유는 이미 전술하였으므로 여기서는 상세한 설명을 생략한다.As shown in FIG. 2F, after impurity implantation of low concentration of impurity ions into the semiconductor substrate 21 using the gate and the first and second side walls as masks, a high concentration of impurity ions are implanted and the LED region 26 is formed. ) And source / drain 27. In this case, since the reason for forming the LED area 26 has already been described above, a detailed description thereof will be omitted.
그리고, 도2g에 도시한 바와같이 상기 엘디디영역(26) 및 소스/드레인(27)이 형성된 구조물의 상부전면에 살리사이드공정을 적용하여 소스/드레인(27), 제1,제2측벽 및 게이트 상에 실리사이드층(28)을 형성한다. 이때, 상기 제2액티브영역의 제1측벽은 폴리실리콘(25)으로 형성되므로, 상부전면에 실리사이드층(28)이 형성되어 폴리실리콘(24)과 엘디디영역(26) 및 소스/드레인(27)을 접속시키지만, 제1,제2액티브영역의 제2측벽은 폴리실리콘(25)과 질화막(22)이 적층되어 형성되므로, 질화막(22)의 상부에는 실리사이드층(28)이 형성되지 않게 되어 폴리실리콘(24)와 엘디디영역(26) 및 소스/드레인(27)을 접속시키지 않게 된다.As shown in FIG. 2G, the salicide process is applied to the upper surface of the structure in which the LED area 26 and the source / drain 27 are formed, and thus the source / drain 27, the first and second sidewalls, and the like. The silicide layer 28 is formed on the gate. In this case, since the first side wall of the second active region is formed of polysilicon 25, a silicide layer 28 is formed on the upper surface of the second active region so that the polysilicon 24, the LED region 26, and the source / drain 27 are formed. ) But the second side walls of the first and second active regions are formed by stacking polysilicon 25 and nitride film 22, so that silicide layer 28 is not formed on top of nitride film 22. The polysilicon 24 and the LED area 26 and the source / drain 27 are not connected.
그리고, 도2h에 도시한 바와같이 상기 실리사이드층(28)이 형성된 구조물의 상부에 층간절연막(29)을 증착하고, 그 층간절연막(29)의 상부에 감광막을 도포한 후, 노광 및 현상하여 감광막 패턴(PR23)을 형성하고, 그 감광막 패턴(PR23)을 적용하여 층간절연막(29)을 식각한다. 이때, 감광막 패턴(PR23)은 상기 제1,제2액티브영역의 게이트 타측면 반도체기판(21) 내에 형성된 실리사이드(28) 상의 층간절연막(29)이 노출되도록 형성한다.2H, an interlayer insulating film 29 is deposited on the structure on which the silicide layer 28 is formed, a photoresist film is applied on the interlayer insulating film 29, and then exposed and developed to expose the photosensitive film. The pattern PR23 is formed, and the photoresist pattern PR23 is applied to etch the interlayer insulating film 29. In this case, the photoresist pattern PR23 is formed so that the interlayer insulating layer 29 on the silicide 28 formed in the gate semiconductor side 21 of the first and second active regions is exposed.
그리고, 도2i에 도시한 바와같이 상기 감광막 패턴(PR23)을 제거한 후, 그 구조물의 상부에 도전성물질로 배리어 금속층과 텅스텐을 증착한 후, 에치-백 또는 화학기계적 연마를 통해 평탄화하여 콘택(30)을 형성한다.As shown in FIG. 2I, after the photoresist pattern PR23 is removed, a barrier metal layer and tungsten are deposited on the structure, and then planarized by etch-back or chemical mechanical polishing. ).
그리고, 도2j에 도시한 바와같이 상기 층간절연막(29) 사이에 콘택(30)이 형성된 구조물의 상부전면에 금속배선(31)을 증착하고, 사진식각공정을 통해 패터닝한다.As shown in FIG. 2J, the metal wiring 31 is deposited on the upper surface of the structure in which the contact 30 is formed between the interlayer insulating layers 29 and patterned through a photolithography process.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 1번의 층간절연막 증착을 통해 게이트의 제1측벽으로 형성되는 내부접속층과 콘택의 단락을 방지함과 아울러 내부접속층을 게이트의 제1측벽으로 형성함에 따라 내부접속층의 오정렬에 대한 우려를 해결할 수 있게 되므로, 종래 2번의 배리어 금속층과 텅스텐 증착공정 및 텅스텐 평탄화공정을 1번으로 줄일 수 있어 제조비용의 절감 및 생산성 향상에 기여할 수 있고, 제1,2액티브영역의 게이트측면에 질화막과 폴리실리콘이 적층된 제2측벽을 형성하여 게이트 상부에 형성되는 실리사이드층의 면적을 넓게 할 수 있어 게이트저항을 감소시킬 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above prevents a short circuit between an interconnection layer and a contact formed as the first sidewall of the gate through the deposition of a first interlayer insulating film, and the internal interconnection layer is formed on the first sidewall of the gate. As a result, the problem of misalignment of the internal connection layer can be solved, and thus, the conventional barrier metal layer, tungsten deposition process, and tungsten planarization process can be reduced to one time, thereby reducing manufacturing cost and improving productivity. By forming a second side wall in which a nitride film and polysilicon are stacked on the gate side of the first and second active regions, the area of the silicide layer formed on the gate can be increased, thereby reducing the gate resistance.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980052207A KR100273325B1 (en) | 1998-12-01 | 1998-12-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980052207A KR100273325B1 (en) | 1998-12-01 | 1998-12-01 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000037582A KR20000037582A (en) | 2000-07-05 |
| KR100273325B1 true KR100273325B1 (en) | 2000-12-15 |
Family
ID=19560718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980052207A KR100273325B1 (en) | 1998-12-01 | 1998-12-01 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100273325B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772826B1 (en) * | 2001-12-27 | 2007-11-01 | 동부일렉트로닉스 주식회사 | Fabrication method of semiconductor device |
| US7598572B2 (en) * | 2006-10-25 | 2009-10-06 | International Business Machines Corporation | Silicided polysilicon spacer for enhanced contact area |
-
1998
- 1998-12-01 KR KR1019980052207A patent/KR100273325B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000037582A (en) | 2000-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5937283A (en) | Method of making a dual gate trench thin film transistor | |
| KR100249159B1 (en) | Method for manufacturing semiconductor device | |
| JP3980985B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH09260655A (en) | Manufacture of semiconductor device | |
| KR100387721B1 (en) | Manufacturing method of semiconductor device | |
| KR100273325B1 (en) | Method for manufacturing semiconductor device | |
| US20020090771A1 (en) | Self-align offset gate structure and method of manufacture | |
| KR20010054169A (en) | Method for manufacturing semiconductor device | |
| KR100280521B1 (en) | Semiconductor device and manufacturing method | |
| KR100226778B1 (en) | The manufacturing method of semiconductor device | |
| KR100269628B1 (en) | A method of fabricating semiconductor device | |
| KR100486120B1 (en) | Method for forming of mos transistor | |
| JP3523244B1 (en) | Method for manufacturing semiconductor device | |
| KR100359766B1 (en) | Method for manufacturing fo semiconductor device | |
| KR19980058381A (en) | Semiconductor device and other manufacturing method | |
| JP4308341B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20020055174A (en) | Method for fabricating analog device | |
| KR101271309B1 (en) | Method for manufacturing a semiconductor device | |
| KR100317333B1 (en) | Method for manufacturing semiconductor device | |
| KR100280528B1 (en) | Internal wiring formation method of semiconductor device | |
| KR100273299B1 (en) | Method for fabricating mos transistor | |
| KR100475135B1 (en) | Method for Forming Contact of Semiconductor Device | |
| JPH11274486A (en) | Semiconductor device and its manufacturing method | |
| JPH09321287A (en) | Fabrication of semiconductor device | |
| KR100269629B1 (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090828 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |