KR20040084470A - A method for forming a contact of a semiconductor device - Google Patents

A method for forming a contact of a semiconductor device Download PDF

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Publication number
KR20040084470A
KR20040084470A KR1020030019586A KR20030019586A KR20040084470A KR 20040084470 A KR20040084470 A KR 20040084470A KR 1020030019586 A KR1020030019586 A KR 1020030019586A KR 20030019586 A KR20030019586 A KR 20030019586A KR 20040084470 A KR20040084470 A KR 20040084470A
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South Korea
Prior art keywords
forming
gate electrode
contact
landing plug
semiconductor device
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KR1020030019586A
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Korean (ko)
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고욱현
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주식회사 하이닉스반도체
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Priority to KR1020030019586A priority Critical patent/KR20040084470A/en
Publication of KR20040084470A publication Critical patent/KR20040084470A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

PURPOSE: A method for forming a contact of a semiconductor device is provided to restrain the damage of a gate electrode by forming a passivation layer on the gate electrode. CONSTITUTION: Gate electrodes(45) with a hard mask(47) and a spacer are formed on a substrate(41). Landing plugs(53) are formed between the gate electrodes. A passivation layer(54) made of a nitride layer is formed on the gate electrode. Bit lines(59) are formed to connect the landing plug through the first interlayer dielectric(55). A storage node contact hole(63) is then formed to expose the landing plug through the second interlayer dielectric(61).

Description

반도체소자의 콘택 형성방법{A method for forming a contact of a semiconductor device}A method for forming a contact of a semiconductor device

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로,The present invention relates to a method for forming a contact of a semiconductor device,

특히 비트라인 및 저장전극 콘택 공정시 게이트전극이 손상되는 현상을 방지하기 위하여, 절연막 스페이서가 구비되는 게이트전극 상부에 보호막을 형성하는 방법에 관한 것이다.In particular, the present invention relates to a method of forming a protective film on the gate electrode provided with the insulating film spacer in order to prevent the gate electrode from being damaged during the bit line and storage electrode contact process.

종래기술에 따른 저장전극 콘택 노드의 형성 기술은 다음의 두 가지 방법이 있다.There are two methods for forming a storage electrode contact node according to the prior art.

첫째, 비트라인이 형성된 전체표면상부에 절연막을 형성하고 저장전극 콘택 영역을 식각하고 이를 매립하는 것이다.First, an insulating film is formed on the entire surface where the bit lines are formed, and the storage electrode contact region is etched and buried.

둘째, 비트라인이 형성된 전체표면상부에 절연막을 형성하고 이를 평탄화식각한 다음, 비트라인과 교차하는 라인 타입 패터닝을 실시하여 콘택영역의 절연막을 식각하는 것으로서, 콘택 마진을 증가시킬 수 있다.Second, by forming an insulating film on the entire surface where the bit lines are formed and flattening the etching, and then etching the insulating film of the contact region by performing line type patterning that intersects the bit lines, the contact margin can be increased.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 콘택 형성방법을 도시한 평면도이다.1A and 1B are plan views illustrating a method for forming a contact of a semiconductor device according to the related art.

도 1a 를 참조하면, 반도체기판(11)에 트렌치형 소자분리막(13)을 형성한다.Referring to FIG. 1A, a trench type isolation layer 13 is formed on a semiconductor substrate 11.

상기 반도체기판(11) 상부에 게이트산화막(도시안됨), 게이트전극용 도전층(15) 및 하드마스크층(17)을 형성하고 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 게이트전극을 형성한다.A gate oxide layer (not shown), a gate electrode conductive layer 15, and a hard mask layer 17 are formed on the semiconductor substrate 11, and the gate electrode is formed by a photolithography process using a gate electrode mask (not shown). do.

상기 게이트전극을 포함한 전체표면상부에 산화막(19) 및 질화막(21)을 적층한다.The oxide film 19 and the nitride film 21 are laminated on the entire surface including the gate electrode.

상기 적층구조를 이방성식각하여 상기 게이트전극 측벽에 산화막(19) 스페이서 및 질화막(21) 스페이서의 적층구조를 형성한다.The stack structure is anisotropically etched to form a stack structure of an oxide film 19 spacer and a nitride film 21 spacer on sidewalls of the gate electrode.

후속공정으로 전체표면상부에 하부절연층(도시안됨)을 형성하고 랜딩 플러그 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 하부절연층을 식각하여 상기 반도체기판(11)의 활성영역을 노출시키는 랜딩 플러그 콘택홀(도시안됨)을 형성한다.In a subsequent process, a lower insulating layer (not shown) is formed on the entire surface, and the lower insulating layer is etched by a photolithography process using a landing plug contact mask (not shown) to expose the active region of the semiconductor substrate 11. Form a landing plug contact hole (not shown).

상기 랜딩 플러그 콘택홀을 매립하는 랜딩 플러그 폴리를 전체표면상부에 증착하고 상기 하드마스크층(17)을 노출시키는 평탄화식각공정을 실시하여 랜딩 플러그(23)를 형성한다.A landing plug 23 is formed by depositing a landing plug poly filling the landing plug contact hole on the entire surface and exposing the hard mask layer 17.

도 1b를 참조하면, 전체표면상부에 제1층간절연막(25)을 형성한다. 이때, 상기 제1층간절연막(25)은 BPSG ( boro phospho silicate glass )를 이용하여 형성한다.Referring to FIG. 1B, a first interlayer insulating film 25 is formed over the entire surface. In this case, the first interlayer insulating layer 25 is formed using boro phospho silicate glass (BPSG).

비트라인 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 제1층간절연막(25)을 식각하여 상기 랜딩 플러그(23)를 노출시키는 비트라인 콘택홀(27)을 형성한다. 이때, ⓐ 와 같이 상기 게이트전극의 측벽에 형성된 스페이서(19,21)가 손상된다.In the photolithography process using a bit line contact mask (not shown), the first interlayer insulating layer 25 is etched to form a bit line contact hole 27 exposing the landing plug 23. At this time, the spacers 19 and 21 formed on the sidewalls of the gate electrode are damaged as shown by.

상기 비트라인 콘택홀(27)을 매립하는 비트라인(29)을 형성한다.The bit line 29 filling the bit line contact hole 27 is formed.

전체표면상부에 제2층간절연막(31)을 형성한다.A second interlayer insulating film 31 is formed over the entire surface.

저장전극 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 제2층간절연막(31) 및 제1층간절연막(25)을 식각하여 상기 랜딩 플러그(23)를 노출시키는저장전극 콘택홀(33)을 형성한다. 이때, ⓑ 와 같이 상기 게이트전극의 측벽에 형성된 스페이서(19,21)가 손상되되, 상기 ⓐ 보다 과도하게 식각된다.The storage electrode contact hole 33 exposing the landing plug 23 by etching the second interlayer insulating layer 31 and the first interlayer insulating layer 25 by a photolithography process using a storage electrode contact mask (not shown). Form. At this time, the spacers 19 and 21 formed on the sidewalls of the gate electrode are damaged, such as ⓑ, but are excessively etched than ⓐ.

후속 공정으로 상기 저장전극 콘택홀(33)을 매립하는 저장전극(도시안됨)을 형성한다.In a subsequent process, a storage electrode (not shown) filling the storage electrode contact hole 33 is formed.

도 2a 및 도 2b 는 상기 종래기술에 따른 문제점을 도시한 셈사진으로서, 비트라인 콘택 불량과 저장전극 콘택 불량 상태를 각각 도시한 것이다. 이때, 콘택 공정시 게이트전극의 어깨 부분이 손상됨을 알 수 있다.2A and 2B illustrate a problem according to the related art, showing bit line contact failures and storage electrode contact failures, respectively. At this time, it can be seen that the shoulder portion of the gate electrode is damaged during the contact process.

상기한 바와 같이 종래기술에 따른 반도체소자의 콘택 형성방법은,As described above, the method for forming a contact of a semiconductor device according to the prior art,

콘택 공정시 게이트전극이 손상되고 심할 경우 게이트전극용 도전층이 노출될 수 있어 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.If the gate electrode is damaged or severe during the contact process, the conductive layer for the gate electrode may be exposed, thereby degrading the characteristics and reliability of the semiconductor device and consequently making it difficult to integrate the semiconductor device.

본 발명은 이러한 종래기술의 문제점을 해결하기 위하여, 게이트전극 상부에 보호막을 패터닝하고 후속 콘택 공정을 실시하여 상기 콘택 공정시 상기 게이트전극의 손상을 방지할 수 있도록 함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art, the protective film is patterned on the gate electrode and a subsequent contact process is performed to prevent damage to the gate electrode during the contact process, thereby improving the characteristics and reliability of the semiconductor device. It is an object of the present invention to provide a method for forming a contact for a semiconductor device, which enables high integration of the semiconductor device.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 콘택 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the prior art.

도 2a 및 도 2b 는 종래기술에 따른 문제점이 도시된 셈사진.Figures 2a and 2b is a photo showing a problem according to the prior art.

도 3a 내지 도 3c 는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도.3A to 3C are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

< 도면의 주요부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>

11,41 : 반도체기판 13,43 : 소자분리막11,41: semiconductor substrate 13,43: device isolation film

15,45 : 게이트전극용 도전층 17,47 : 하드마스크층15,45: conductive layer for gate electrode 17,47: hard mask layer

19,49 : 산화막 21,51 : 질화막19,49 oxide film 21,51 nitride film

23,53 : 랜딩 플러그 25,55 : 제1층간절연막23,53: landing plug 25,55: first interlayer insulating film

27,57 : 비트라인 콘택홀 29,59 : 비트라인27,57: bit line contact hole 29,59: bit line

31,61 : 제2층간절연막 33,63 : 저장전극 콘택홀31,61: Second interlayer insulating film 33,63: Storage electrode contact hole

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 콘택 형성방법은,In order to achieve the above object, the contact forming method of a semiconductor device according to the present invention,

사이에 랜딩 플러그가 구비되는 게이트전극 상부에 보호막을 형성하는 공정과,Forming a protective film on the gate electrode provided with a landing plug therebetween;

전체표면상부에 제1층간절연막을 형성하고 이를 통하여 상기 랜딩 플러그에 접속되는 비트라인을 형성하는 공정과,Forming a first interlayer insulating film over the entire surface and thereby forming a bit line connected to the landing plug;

전체표면상부에 제2층간절연막을 형성하고 이를 통하여 상기 랜딩 플러그가 노출되는 저장전극 콘택홀을 형성하는 공정을 포함하는 것과,Forming a second interlayer insulating film over the entire surface and forming a storage electrode contact hole through which the landing plug is exposed;

상기 보호막은 전체표면상부에 질화막을 증착하고 게이트전극 마스크를 이용한 사진식각공정으로 형성하는 것을 특징으로 한다.The protective film is formed by depositing a nitride film on the entire surface and forming a photolithography process using a gate electrode mask.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3b 는 본 발명의 실시예에 따른 반도체소자의 콘택 형성방법을 도시한 단면도이다.3A to 3B are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

도 3a 를 참조하면,Referring to FIG. 3A,

반도체기판(41)에 트렌치형 소자분리막(43)을 형성한다.A trench type isolation layer 43 is formed on the semiconductor substrate 41.

상기 반도체기판(41) 상부에 게이트산화막(도시안됨), 게이트전극용 도전층(45) 및 하드마스크층(47)을 형성하고 게이트전극 마스크(도시안됨)를 이용한 사진식각공정으로 게이트전극을 형성한다.A gate oxide layer (not shown), a gate electrode conductive layer 45, and a hard mask layer 47 are formed on the semiconductor substrate 41 and the gate electrode is formed by a photolithography process using a gate electrode mask (not shown). do.

상기 게이트전극을 포함한 전체표면상부에 산화막(49) 및 질화막(51)을 적층한다.An oxide film 49 and a nitride film 51 are laminated on the entire surface including the gate electrode.

상기 적층구조를 이방성식각하여 상기 게이트전극 측벽에 산화막(49) 스페이서 및 질화막(51) 스페이서의 적층구조를 형성한다.The stack structure is anisotropically etched to form a stack structure of an oxide film 49 spacer and a nitride film 51 spacer on the sidewalls of the gate electrode.

후속공정으로 전체표면상부에 하부절연층(도시안됨)을 형성하고 랜딩 플러그 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 하부절연층을 식각하여 상기 반도체기판(41)의 활성영역을 노출시키는 랜딩 플러그 콘택홀(도시안됨)을 형성한다.In a subsequent process, a lower insulating layer (not shown) is formed on the entire surface, and the lower insulating layer is etched by a photolithography process using a landing plug contact mask (not shown) to expose the active region of the semiconductor substrate 41. Form a landing plug contact hole (not shown).

상기 랜딩 플러그 콘택홀을 매립하는 랜딩 플러그 폴리를 전체표면상부에 증착하고 상기 하드마스크층(47)을 노출시키는 평탄화식각공정을 실시하여 랜딩 플러그(53)를 형성한다.A landing plug 53 is formed by depositing a landing plug poly filling the landing plug contact hole on the entire surface and performing a planar etching process of exposing the hard mask layer 47.

전체표면상부에 보호막(54)을 증착한다. 이때, 상기 보호막(54)은 질화막으로 형성한다.The protective film 54 is deposited on the entire surface. In this case, the protective film 54 is formed of a nitride film.

도 3b를 참조하면, 게이트전극 마스크를 이용한 사진식각공정으로 상기 보호막(54)을 식각하여 상기 게이트전극 상부에만 남긴다.Referring to FIG. 3B, the passivation layer 54 is etched by a photolithography process using a gate electrode mask to leave only the gate electrode.

도 3c를 참조하면, 전체표면상부에 제1층간절연막(55)을 형성한다. 이때, 상기 제1층간절연막(55)은 BPSG ( boro phospho silicate glass )를 이용하여 형성한다.Referring to FIG. 3C, a first interlayer insulating film 55 is formed on the entire surface. In this case, the first interlayer insulating layer 55 is formed using borophospho silicate glass (BPSG).

비트라인 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 제1층간절연막(55)을 식각하여 상기 랜딩 플러그(53)를 노출시키는 비트라인 콘택홀(57)을 형성한다.In the photolithography process using a bit line contact mask (not shown), the first interlayer insulating layer 55 is etched to form a bit line contact hole 57 exposing the landing plug 53.

상기 비트라인 콘택홀(57)을 매립하는 비트라인(59)을 형성한다.A bit line 59 is formed to fill the bit line contact hole 57.

전체표면상부에 제2층간절연막(61)을 형성한다.A second interlayer insulating film 61 is formed over the entire surface.

저장전극 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 제2층간절연막(61) 및 제1층간절연막(55)을 식각하여 상기 랜딩 플러그(53)를 노출시키는 저장전극 콘택홀(63)을 형성한다.The storage electrode contact hole 63 exposing the landing plug 53 by etching the second interlayer insulating layer 61 and the first interlayer insulating layer 55 by a photolithography process using a storage electrode contact mask (not shown). Form.

후속 공정으로 상기 저장전극 콘택홀(63)을 매립하는 저장전극(도시안됨)을 형성한다.In a subsequent process, a storage electrode (not shown) filling the storage electrode contact hole 63 is formed.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 콘택 형성방법은,As described above, the method for forming a contact of a semiconductor device according to the present invention,

게이트전극 상부에 질화막으로 보호막을 형성하여 후속 콘택 공정시 게이트전극의 손상을 억제함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.By forming a protective film on the gate electrode with a nitride film to suppress damage of the gate electrode in a subsequent contact process, thereby improving the characteristics and reliability of the semiconductor device and thereby providing high integration of the semiconductor device.

Claims (2)

랜딩 플러그가 사이에 구비되는 게이트전극 상부에 보호막을 형성하는 공정과,Forming a protective film on the gate electrode having a landing plug interposed therebetween; 전체표면상부에 제1층간절연막을 형성하고 이를 통하여 상기 랜딩 플러그에 접속되는 비트라인을 형성하는 공정과,Forming a first interlayer insulating film over the entire surface and thereby forming a bit line connected to the landing plug; 전체표면상부에 제2층간절연막을 형성하고 이를 통하여 상기 랜딩 플러그가 노출되는 저장전극 콘택홀을 형성하는 공정을 포함하는 반도체소자의 콘택 형성방법.And forming a storage electrode contact hole through which the second interlayer insulating layer is formed on the entire surface, and through which the landing plug is exposed. 제 1 항에 있어서,The method of claim 1, 상기 보호막은 전체표면상부에 질화막을 증착하고 게이트전극 마스크를 이용한 사진식각공정으로 형성하는 것을 특징으로 하는 반도체소자의 콘택 형성방법.The protective film is a contact forming method of a semiconductor device, characterized in that the nitride film is deposited on the entire surface and formed by a photolithography process using a gate electrode mask.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100685108B1 (en) * 2003-08-27 2007-02-22 노발레드 아게 Light emitting device and method for producing thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100685108B1 (en) * 2003-08-27 2007-02-22 노발레드 아게 Light emitting device and method for producing thereof

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