KR100231598B1 - Method for forming contact hole of semiconductor device - Google Patents

Method for forming contact hole of semiconductor device Download PDF

Info

Publication number
KR100231598B1
KR100231598B1 KR1019960034200A KR19960034200A KR100231598B1 KR 100231598 B1 KR100231598 B1 KR 100231598B1 KR 1019960034200 A KR1019960034200 A KR 1019960034200A KR 19960034200 A KR19960034200 A KR 19960034200A KR 100231598 B1 KR100231598 B1 KR 100231598B1
Authority
KR
South Korea
Prior art keywords
interlayer insulating
semiconductor device
conductive layer
film
pattern
Prior art date
Application number
KR1019960034200A
Other languages
Korean (ko)
Other versions
KR19980014993A (en
Inventor
전범진
이동덕
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019960034200A priority Critical patent/KR100231598B1/en
Publication of KR19980014993A publication Critical patent/KR19980014993A/en
Application granted granted Critical
Publication of KR100231598B1 publication Critical patent/KR100231598B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 워드라인용 도전층/실리사이드막/층간절연막의 적층구조를 각각 일정두께 증착하고, 상기 층간절연막, 실리사이드막 및 워드라인용도전층을 콘택마스크를 이용하여 순차적으로 식각함으로써 층간절연막패턴, 실리사이드막패턴 및 워드라인용 도전층패턴을 형성하되, 상기 실리사이드막은 상기 층간절연막 하부로 언더컷을 형성한 다음, 상기 층간절연막패턴, 실리사이드막패턴 및 워드라인용 도전층패턴 측벽에 절연막 스페이서를 형성하고, 상기 반도체기판의 전체표면상부를 평탄화시키는 하부절연층을 형성한 다음, 상기 콘택마스크를 이용하여 자기정렬적으로 콘택식각함으로써 상기 반도체기판을 노출시키는 콘택홀을 형성하되, 콘택마스크의 미스얼라인 유발시에도 안정된 콘택홀을 형성하여 반도체소자의 수율 및 생산성을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, wherein a stacked structure of a word line conductive layer / silicide film / interlayer insulating film is deposited on a semiconductor substrate to a predetermined thickness, and the interlayer insulating film, the silicide film and the word line conductive layer are contacted. By sequentially etching using a mask, an interlayer insulating film pattern, a silicide film pattern, and a conductive layer pattern for word lines are formed, and the silicide film forms an undercut under the interlayer insulating film, and then the interlayer insulating pattern, the silicide film pattern, and the word An insulating layer spacer is formed on the sidewalls of the line conductive layer pattern, a lower insulating layer is formed to planarize the entire upper surface of the semiconductor substrate, and then the semiconductor substrate is exposed by self-aligned contact etching using the contact mask. Forms contact holes but is stable even when misalignment of contact masks occurs By forming a contact hole, the technology improves the yield and productivity of the semiconductor device, improves the characteristics and reliability of the semiconductor device, and accordingly, enables high integration of the semiconductor device.

Description

반도체소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

제1a도 내지 제1f도는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도.1A to 1F are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 워드라인용 도전층 13 : 텅스텐 실리사이드막11: conductive layer for word line 13: tungsten silicide film

15 : 층간절연막 17 : 언더컷15: interlayer insulating film 17: undercut

19 : 질화막 21 : 하부절연층19 nitride layer 21 lower insulating layer

23 : 감광막패턴 25 : 콘택홀23: photoresist pattern 25: contact hole

40 : 반도체기판40: semiconductor substrate

본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 특히 중첩마진을 확보할 수 있는 자기정렬적인 콘택공정으로 0.3㎛이하의 크기를 갖는 콘택홀을 형성하여 256 메가 디램(mega DRAM) 급 이상의 메모리소자를 형성할 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, a contact hole having a size of 0.3 μm or less is formed by a self-aligned contact process that can secure an overlap margin. It is related with the technique which can form an element.

반도체 메모리소자 중에서 디램은 반도체기판 상부에 게이트전극을 형성하고 상기 게이트전극과 게이트전극 사이에 형성된 소오스/드레인접합을 노출시키는 콘택홀을 형성한 다음, 상기 콘택홀을 통하여 상기 소오스/드레인접합에 접속되는 비트라인과 캐패시터를 형성하였다.Among semiconductor memory devices, a DRAM forms a gate electrode on a semiconductor substrate and forms a contact hole exposing a source / drain junction formed between the gate electrode and the gate electrode, and then connected to the source / drain junction through the contact hole. Bit lines and capacitors were formed.

최초에는 상기 게이트전극간의 폭이 넓어 상기 게이트전극과 비트라인 또는 상기 게이트전극과 캐패시터의 단락이 거의 없었다.Initially, the width between the gate electrodes was wide so that there was almost no short circuit between the gate electrode and bit line or the gate electrode and capacitor.

그러나, 반도체소자가 집적화됨에따라 도전층 간의 단락현상이 발생하여 상기 게이트전극의 측벽에 산화막 스페이서를 형성하였다.However, as semiconductor devices are integrated, a short circuit between conductive layers occurs to form oxide spacers on sidewalls of the gate electrode.

그리고, 반도체소자가 고집적화됨에따라 상기 산화막 스페이서만으로는 상기 게이트전극의 절연을 충분하게 할 수 없게 됨으로써 상기 게이트전극의 사이에 형성되며 측벽에 질화막 스페이서가 형성되는 콘택홀을 자기정렬적으로 형성하게 되었다.As the semiconductor device is highly integrated, insulation of the gate electrode cannot be sufficiently performed with only the oxide film spacer, thereby forming contact holes formed between the gate electrodes and having nitride spacers formed on sidewalls.

여기서, 상기 자기정렬적인 콘택홀 형성공정은 산화막 대 질하막의 식각선택비 차이가 15 이상이고 상기 질화막 대 산화막의 식각선택비 차이가 10 이상으로 구현될 때, 상기 식각선택비 차이를 이용하여 공정을 진행하였다.Here, the self-aligned contact hole forming process may be performed by using an etching selectivity difference when an etching selectivity difference between an oxide film and an oxide film is 15 or more and an etching selectivity difference between the nitride film and an oxide film is 10 or more. Proceeded.

그러나, 상기 식각선택비 차이를 구현하기 어려워 실제공정에 적용하기 어렵고, 이로인하여 상기 자기정렬적인 콘택홀 형성공정을 실시하기 어렵게되었다.However, since it is difficult to implement the difference in the etching selectivity, it is difficult to apply to the actual process, thereby making it difficult to perform the self-aligned contact hole forming process.

상기한 현상으로 인하여, 고집적화된 반도체소자를 형성하기가 어렵게 되고, 상기 반도체소자의 고집적화에 따른 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.Due to the above phenomenon, it is difficult to form a highly integrated semiconductor device, and there is a problem in that the characteristics and reliability of the semiconductor device are degraded due to the high integration of the semiconductor device.

그리고, 반도체소자가 고집적화 될수록 불순물 잡합층의 깊이가 얕게 형성되는 것을 필요로 하지만 공정이 복잡하고 고난도의 기술을 필요로 하여 반도체소자의 생산성을 저하시키는 문제점이 있다.Further, as the semiconductor device becomes more integrated, it is necessary to form a shallower depth of the impurity mixed layer, but there is a problem in that the productivity of the semiconductor device is reduced due to the complicated process and high technology.

따라서, 본 발명은 상기한 문제점들을 해결하기위하여, 콘택홀과 워드라인의 계면에 두껍게 절연막을 형성하되, 중첩되는 부분의 절연막을 특히 두껍게 형성하여 콘택식각공정시 워드라인이 손상되지않도록 자기정렬적인 콘택홀을 형성함으로써 반도체소자의 생산성을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problems, the present invention forms a thick insulating film at the interface between the contact hole and the word line, and forms a particularly thick insulating film at the overlapping portion so that the word line is not damaged during the contact etching process. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device which improves the productivity of the semiconductor device by forming contact holes, improves the characteristics and reliability of the semiconductor device, and thereby enables high integration of the semiconductor device.

이상의 목적을 달성하기위해 본 발명에 따른 반도체소자의 콘택홀 형성방법의 특징은, 반도체기판 상부에 워드라인용 도전층/실리사이드막/층간절연막의 적층구조를 각각 일정한 두께로 증착하는 공정과, 상기 층간절연막, 실리사이드막 및 워드라인용 도전층을 콘택마스크를 이용하여 순차적으로 식각함으로써 층간절연막패턴, 실리사이드막패턴 및 워드라인용 도전층패턴을 형성화되, 상기 실리사이드막은 상기 층간절연막 하부로 언더컷을 형성하는 공정과, 상기 층간절연막패턴, 실리사이드막패턴 및 워드라인용 도전층패턴 측벽에 절연막 스페이서를 형성하는 공정과, 상기 반도체기판의 전체표면상부를 평탄화시키는 하부절연층을 형성하는 공정과, 상기 콘택마스크를 이용하여 자기정렬적으로 콘택식각함으로써 상기 반도체기판을 노출시키는 콘택홀을 형성하는 공정을 포함하는 것이다.In order to achieve the above object, a method of forming a contact hole in a semiconductor device according to the present invention includes the steps of depositing a stacked structure of a conductive layer / silicide film / interlayer insulating film for word lines on a semiconductor substrate with a predetermined thickness, respectively, The interlayer insulating layer, the silicide layer and the word line conductive layer are sequentially etched using a contact mask to form an interlayer insulating layer pattern, the silicide layer pattern and the word line conductive layer pattern, wherein the silicide layer forms an undercut under the interlayer insulating layer. Forming an insulating film spacer on the sidewalls of the interlayer insulating film pattern, the silicide film pattern, and the word line conductive layer pattern; forming a lower insulating layer to planarize the entire upper surface of the semiconductor substrate; When the semiconductor substrate is exposed by self-aligned contact etching using a mask Is to include a step of forming a contact hole.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a도는 내지 제1f도는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.

먼저, 반도체기판(40) 상부에 워드라인용 도전층(11)을 소정두께 형성한다.First, a word line conductive layer 11 is formed on the semiconductor substrate 40.

그리고, 상기 워드라인용 도전층(11) 상부에 텅스텐 실리사이드막(13)을 소정두께 형성한다.A tungsten silicide film 13 is formed on the word line conductive layer 11 at a predetermined thickness.

이때, 상기 워드라인용 도전층(11)은 다결정실리콘이나 폴리사이드와 유사한 특성을 갖는 물질로 형성한다.In this case, the word line conductive layer 11 is formed of a material having properties similar to those of polycrystalline silicon or polyside.

그리고, 상기 텅스텐 실리사이드막(13)은 500∼2000Å 정도의 두께로 형성한다.The tungsten silicide film 13 is formed to a thickness of about 500 to 2000 kPa.

그리고, 상기 텅스텐 실리사이드막(13) 상부에 층간절연막(15)을 100∼1000Å 정도의 두께로 형성한다.Then, an interlayer insulating film 15 is formed on the tungsten silicide film 13 to a thickness of about 100 to 1000 Å.

이때, 상기 층간절연막(15)은 질화막으로 형성한다.At this time, the interlayer insulating film 15 is formed of a nitride film.

그 다음에, 워드라인마스커(도시안됨)를 이용한 식각공정으로 상기 층간절연막(15)을 식각하여 층간절연막(15)패턴을 형성한다. (제1a도)Next, the interlayer insulating layer 15 is etched by an etching process using a word line masker (not shown) to form the interlayer insulating layer 15 pattern. (Figure 1a)

그리고, 상기 텅스텐 실리사이드막(13)을 건식방법으로 등방성식각하여 상기 층간절연막(15)패턴 하부로 언더컷(under cut)(17)을 형성하는 동시에 텅스텐 실리사이드막(13)패턴을 형성한다.The tungsten silicide layer 13 is isotropically etched by a dry method to form an under cut 17 under the interlayer dielectric layer 15 pattern and to form a tungsten silicide layer 13 pattern.

이때, 상기 등방성식각공정은 염소계 또는 불소계 플라즈마에 산소가스나 질소가스를 첨가하여 실시한다.At this time, the isotropic etching process is performed by adding oxygen gas or nitrogen gas to the chlorine or fluorine-based plasma.

또한, 상기 등방성식각공정은 습식방법으로 실시할 수 있다.In addition, the isotropic etching process may be performed by a wet method.

그 다음에, 연속적으로 상기 텅스텐 실리사이드막(13)의 남은 부분과 워드라인용 도전층(11)을 이방성식각하여 워드라인용 도전층(11)패턴을 형성한다.(제1b도)Subsequently, the remaining portion of the tungsten silicide film 13 and the word line conductive layer 11 are subsequently anisotropically etched to form a word line conductive layer 11 pattern (FIG. 1B).

그리고, 전체표면상부에 질화막(19)을 100∼1000Å 정도의 두께로 형성한다. (제1c도)Then, a nitride film 19 is formed on the entire surface with a thickness of about 100 to 1000 mm 3. (Figure 1c)

그 다음에, 상기 질화막(19)을 이방성식각하여 상기 층간절연막(15)패턴, 텅스텐 실리사이드막(13)패턴 및 워드라인용 도전층(11)패턴 측벽에 질화막(19) 스페이서를 형성한다. (제1d도)Next, the nitride film 19 is anisotropically etched to form a nitride film spacer 19 on the sidewalls of the interlayer insulating film 15 pattern, the tungsten silicide film 13 pattern, and the word line conductive layer 11 pattern. (Figure 1d)

그리고, 전체표면상부를 평탄화시키는 하부절연층(21)을 형성한다.Then, the lower insulating layer 21 is formed to planarize the entire upper surface.

이때, 상기 하부절연층(35)은 비.피.에스.지 (Boro Phospho Silicate Galss, 이하에서 BPSG 라함) 와 같이 유동성이 우수한 절연물질로 형성한다.In this case, the lower insulating layer 35 is formed of an insulating material having excellent fluidity, such as B.P.S. paper (hereinafter referred to as BPSG).

그리고, 상기 하부절연층(35) 상부에 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(23)을 형성한다.The photoresist pattern 23 is formed on the lower insulating layer 35 by an exposure and development process using a contact mask (not shown).

이때, 상기 콘택마스크는 상기 제1a도에 사용된 콘택마스크에 비하여 미스얼라인(misalign)된 것이다. (제1e도)In this case, the contact mask is misaligned compared to the contact mask used in FIG. 1A. (Figure 1e)

그 다음에, 상기 감광막패턴(23)을 마스크로하여 상기 하부절연층(21)을 식각하되, 상기 질화막(19) 스페이서 및 층간절연막(15)패턴과 상기 하부절연층과의 식각선택비 차이를 이용하여 식각함으로써 상기 반도체기판(40)을 노출시키는 콘택홀(25)을 형성한다.Subsequently, the lower insulating layer 21 is etched using the photoresist pattern 23 as a mask, and the difference in etching selectivity between the nitride layer 19 spacer and the interlayer insulating layer 15 pattern and the lower insulating layer is determined. Etching to form a contact hole 25 exposing the semiconductor substrate 40.

이때, 상기 콘택식각공정은 상기 층간절연막(15)패턴도 중첩된만큼 식각되고, 중첩되지않은 워드라인 측벽에 형성된 상기 질화막(19) 스페이서가 중첩된 부분의 스페이서보다 많이 남는다. (제1f도)In this case, the contact etching process is etched by overlapping the interlayer insulating layer 15 pattern, and the spacers of the nitride layer 19 formed on the sidewalls of the non-overlapping word lines remain more than the spacers of the overlapped portions. (Figure 1f)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 콘택홀 형성방법은, 워드라인용 도전층/실리사이드막/층간절연막의 적층구조로 형성된 워드라인에서 상기 실리사이드막을 등방성식각하여 언더컷을 형성한 다음, 자기정렬적인 콘택공정을 실시함으로써 콘택공정시 중첩마진을 향상시켜 반도체소자의 수율 및 생산성을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 향상시키는 잇점이 있다.As described above, in the method for forming a contact hole in a semiconductor device according to the present invention, an undercut is formed by isotropically etching the silicide layer in a word line formed of a laminated structure of a conductive layer / silicide layer / interlayer insulating layer for word lines, and then By performing the ordered contact process, the overlap margin is improved during the contact process, thereby improving the yield and productivity of the semiconductor device, improving the characteristics and reliability of the semiconductor device, and thus improving the integration of the semiconductor device.

Claims (10)

반도체기판 상부에 워드라인용 도전층/실리사이드막/층간절연막의 적층구조를 각각 일정한 두께로 증착하는 공정과, 상기 층간절연막, 실리사이드막 및 워드라인용 도전층을 콘택마스크를 이용하여 순차적으로 식각함으로써 층간절연막패턴, 실리사이드막패턴 및 워드라인용 도전층패턴을 형성하되, 상기 실리사이드막은 상기 층간절연막 하부로 언더컷을 형성하는 공정과, 상기 층간절연막패턴, 실리사이드막패턴 및 워드라인용 도전층패턴 측벽에 절연막 스페이서를 형성하는 공정과, 상기 반도체기판의 전체표면상부를 평탄화시키는 하부절연층을 형성하는 공정과, 상기 콘택마스크를 이용하여 자기정렬적으로 콘택식각함으로써 상기 반도체기판을 노출시키는 콘택홀을 형성하는 공정을 포함하는 반도체소자의 콘택홀 형성방법.Depositing a stacked structure of a word line conductive layer / silicide film / interlayer insulating film on a semiconductor substrate with a predetermined thickness, and sequentially etching the interlayer insulating film, silicide film, and word line conductive layer using a contact mask. Forming an interlayer insulating layer pattern, a silicide layer pattern, and a conductive layer pattern for a word line, wherein the silicide layer is formed under the interlayer insulating layer, and on the sidewalls of the interlayer insulating layer pattern, the silicide layer pattern, and the conductive layer pattern for a word line. Forming an insulating film spacer, forming a lower insulating layer to planarize the entire upper surface of the semiconductor substrate, and forming a contact hole exposing the semiconductor substrate by self-aligning contact etching using the contact mask. A contact hole forming method of a semiconductor device comprising the step of. 제1항에 있어서, 상기 워드라인용 도전층은 다결정실리콘막이나 폴리사이드와 유사한 특성을 갖는 물질로 형성하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the word line conductive layer is formed of a material having properties similar to those of a polysilicon film or a polyside. 제1항에 있어서, 상기 실리사이드막은 텅스텐 실리사이드막으로 형성하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the silicide layer is formed of a tungsten silicide layer. 제1항 또는 제3 항에 있어서, 상기 실리사이드막은 500∼2000 Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 1 or 3, wherein the silicide film is formed to a thickness of about 500 to 2000 GPa. 제1항에 있어서, 상기 층간절연막은 질화막으로 형성하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the interlayer insulating film is formed of a nitride film. 제1항 또는 제5 항에 있어서, 상기 층간절연막은 100∼1000 Å 정도의 두께로 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 5, wherein the interlayer insulating film is formed to a thickness of about 100 to about 1000 GPa. 제1항에 있어서, 상기 실리사이드막 식각공정은 등방성식각공정과 이방성식각공정을 연속적으로 실시하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the silicide layer etching process comprises performing an isotropic etching process and an anisotropic etching process. 제1항 또는 제7 항에 있어서, 상기 언더컷은 습식방법의 등방성식각공정이나 건식방법의 등방성식각공정으로 형성하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the undercut is formed by an isotropic etching process of a wet method or an isotropic etching process of a dry method. 제8항에 있어서, 상기 건식방법의 등방성식각공정은 염소계 또는 불소계 플라즈마에 산소가스나 질소가스를 첨가하여 실시하는 것을 특징으로하는 반도체소자의 콘택홀 형성방법.9. The method of claim 8, wherein the isotropic etching process of the dry method is performed by adding oxygen gas or nitrogen gas to a chlorine or fluorine plasma. 제1항에 있어서, 상기 자기정렬적인 콘택공정은 상기 미스얼라인된 콘택마스크를 이용하여 실시한 것을 특징으로하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the self-aligned contact process is performed using the misaligned contact mask.
KR1019960034200A 1996-08-19 1996-08-19 Method for forming contact hole of semiconductor device KR100231598B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960034200A KR100231598B1 (en) 1996-08-19 1996-08-19 Method for forming contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960034200A KR100231598B1 (en) 1996-08-19 1996-08-19 Method for forming contact hole of semiconductor device

Publications (2)

Publication Number Publication Date
KR19980014993A KR19980014993A (en) 1998-05-25
KR100231598B1 true KR100231598B1 (en) 1999-11-15

Family

ID=19469895

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960034200A KR100231598B1 (en) 1996-08-19 1996-08-19 Method for forming contact hole of semiconductor device

Country Status (1)

Country Link
KR (1) KR100231598B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434962B1 (en) * 1997-12-27 2004-07-16 주식회사 하이닉스반도체 Method of forming contact hole of semiconductor device without additional process for removing etch stop pattern

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560294B1 (en) * 1998-12-29 2006-06-13 주식회사 하이닉스반도체 Self-aligned contact formation method of semiconductor device
KR20030096832A (en) * 2002-06-18 2003-12-31 동부전자 주식회사 Method for etching insulator film of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100434962B1 (en) * 1997-12-27 2004-07-16 주식회사 하이닉스반도체 Method of forming contact hole of semiconductor device without additional process for removing etch stop pattern

Also Published As

Publication number Publication date
KR19980014993A (en) 1998-05-25

Similar Documents

Publication Publication Date Title
KR0155886B1 (en) High integrated dram cell fabrication method
KR100231598B1 (en) Method for forming contact hole of semiconductor device
KR20050013830A (en) Method for manufacturing semiconductor device
JP3209639B2 (en) Method for manufacturing semiconductor device
KR100378689B1 (en) Method for forming contact of semiconductor device
KR100505399B1 (en) Method for forming contact in semiconductor device
KR100396685B1 (en) Interconnection of semiconductor device and manufacturing method thereof
KR100277905B1 (en) Manufacturing Method of Semiconductor Memory Device
KR0140733B1 (en) Method of forming dontact in semiconductor device
KR0120568B1 (en) Semiconductor device connection apparatus and manufacture of the same
KR100600288B1 (en) Method of forming a semiconductor device
KR0141949B1 (en) Manufacturing method of semiconductor device
KR20000045437A (en) Method for forming self aligned contact of semiconductor device
KR100195837B1 (en) Micro contact forming method of semiconductor device
KR100506050B1 (en) Contact formation method of semiconductor device
JPH10209402A (en) Semiconductor element and its manufacturing method
KR100198637B1 (en) Fabricating method of semiconductor device
KR20000027911A (en) Method of forming contact of semiconductor device
KR100277883B1 (en) Manufacturing Method of Semiconductor Device
US6277734B1 (en) Semiconductor device fabrication method
KR100200740B1 (en) Manufacturing method of semiconductor device in contact structure
KR0159018B1 (en) Capacitor fabrication method of semiconductor device
KR100445408B1 (en) Contact method of semiconductor device for easily performing storage electrode contact process
KR20070002701A (en) Method for fabricating transistor of semiconductor device
KR20000052111A (en) Method for forming metal contact of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070720

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee