KR20030096832A - Method for etching insulator film of semiconductor device - Google Patents
Method for etching insulator film of semiconductor device Download PDFInfo
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- KR20030096832A KR20030096832A KR1020020033891A KR20020033891A KR20030096832A KR 20030096832 A KR20030096832 A KR 20030096832A KR 1020020033891 A KR1020020033891 A KR 1020020033891A KR 20020033891 A KR20020033891 A KR 20020033891A KR 20030096832 A KR20030096832 A KR 20030096832A
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- 238000005530 etching Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000012212 insulator Substances 0.000 title claims description 5
- 239000007789 gas Substances 0.000 claims abstract description 38
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 9
- 239000011737 fluorine Substances 0.000 claims abstract description 9
- 239000012495 reaction gas Substances 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000006243 chemical reaction Methods 0.000 claims description 22
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 18
- 230000003628 erosive effect Effects 0.000 abstract description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 절연막 식각 방법에 관한 것으로, 더욱 상세하게는 플루오르(Fluorine)가 포함된 가스를 이용하여 건식 방식으로 절연막을 식각할 때에 식각 반응이 발열 반응인 가스와 흡열 반응인 가스를 혼합 사용하여 포토레지스트 패턴의 침식을 막아주는 반도체 소자의 절연막 식각 방법에 관한 것이다.The present invention relates to a method for etching an insulating film of a semiconductor device, and more particularly, when the insulating film is etched in a dry manner using a gas containing fluorine, a gas in which the etching reaction is exothermic and an endothermic gas are mixed. The present invention relates to an insulating film etching method of a semiconductor device which prevents erosion of a photoresist pattern.
반도체 제조 공정 중 산화물 계열 필름은 절연막으로 사용하며, 상부와의 연결을 위하여 절연막의 홀 식각(Hole etch)을 행하는데, 통상적으로 산화물 계열 절연막을 식각할 때는 플루오르가 포함된 가스(CF4, C4F8, C2F6, CHF3 등)를 주로 이용한다.During the semiconductor manufacturing process, an oxide-based film is used as an insulating film, and a hole etch of the insulating film is performed to connect to the upper part. Generally, when etching an oxide-based insulating film, gases containing fluorine (CF4, C4F8, C2F6, CHF3, etc.) is mainly used.
종래 기술에 따른 반도체 소자의 절연막 식각 방법을 도 1 및 도 2를 참조하여 설명하면 다음과 같다.An insulating film etching method of a semiconductor device according to the prior art will be described with reference to FIGS. 1 and 2.
먼저, 기판(1) 상에 식각하고자 하는 물질, 예컨대 실리콘산화물 계열의 절연물(SiO2 등)을 증착하여 절연막(3)을 형성하고, 그 위에 식각 마스크로서 사용될 물질, 예컨대 포토레지스트를 도포하여 포토레지스트층(도시되지 않음)을 형성한다.First, a material to be etched, such as a silicon oxide-based insulator (SiO2, etc.) is deposited on the substrate 1 to form an insulating film 3, and then a material to be used as an etching mask, for example, a photoresist, is coated on the photoresist. Forms a layer (not shown).
다음, 상기 포토레지스트층을 패터닝하여, 식각하고자 하는 부분(빗금친 부분)을 노출시키는 포토레지스트 패턴(5)을 형성하고, 절연막(3)을 선택적으로 건식 식각하여 콘택홀을 형성한다.Next, the photoresist layer is patterned to form a photoresist pattern 5 exposing portions to be etched (hatched portions), and the insulating layer 3 is selectively dry etched to form contact holes.
상기의 건식 식각 공정에서 CF4, C4F8, C2F6, CHF3 등의 가스를 주로 이용하는데, 이런 식각 가스는 산화물 계열의 절연막과 반응하여 여러 부산물(Byproducts)을 만든다.In the dry etching process, gases such as CF4, C4F8, C2F6, and CHF3 are mainly used. The etching gas reacts with an oxide-based insulating layer to produce various byproducts.
일예로, 절연막(3)을 형성하기 위한 절연물로 SiO2를 이용하는 경우에 식각 가스는 SiO2와 반응하여 SiF4(↑), CO(↑), CO2(↑) 등의 부산물을 만든다.For example, when SiO 2 is used as an insulator for forming the insulating film 3, the etching gas reacts with SiO 2 to form by-products such as SiF 4 (↑), CO (↑), and CO 2 (↑).
이들 반응물은 발열 반응에 의하여 도 2에 점선으로 나타낸 바와 같이 홀 측벽 부분의 포토레지스트 패턴을 침식시키고, 하부 절연막 홀 패턴에도 일그러지는현상이 나오도록 만든다.These reactants erode the photoresist pattern of the hole sidewall portion as shown by the dotted line in FIG. 2 by exothermic reaction, and cause distortion in the lower insulating film hole pattern.
다시 말해서, 식각 시간이 오랜 시간 진행함에 따라 마스크 패턴 형태로의 반듯한 홀 형성이 더욱 어려운데, 도 4a의 에너지 변화 그래프에 나타낸 바와 같이 발열 반응(C + O2 → CO2 + 394kJ)에 의하여 포토레지스트 패턴에 손상을 일으키며 그 영향이 절연막으로 다시 돌아옴으로 인하여 발생된다.In other words, as the etching time progresses for a long time, it is more difficult to form a straight hole in the form of a mask pattern. As shown in the energy change graph of FIG. 4A, the photoresist pattern is formed by an exothermic reaction (C + O 2 → CO 2 + 394 kJ). It causes damage and its effect is caused by the return to the insulating film.
이러한 침식 현상은 특히 홀이 깊을수록 더욱 영향을 주게 되고, 패턴의 일그러짐 현상을 더욱 심화시키는 문제점이 있다.In particular, the erosion phenomenon affects the deeper the hole, the deeper the distortion of the pattern.
본 발명은 이와 같은 종래의 문제점을 해결하기 위하여 제안한 것으로, 플루오르가 포함된 가스를 이용하여 건식 방식으로 절연막을 식각할 때에 식각 반응이 발열 반응인 가스와 흡열 반응인 가스를 혼합 사용하여 포토레지스트 패턴의 침식을 막아주어 절연막 홀 패턴의 깨짐 현상을 방지하여 반도체 소자의 신뢰성 및 수율을 향상시키는 데 그 목적이 있다.The present invention has been proposed to solve such a conventional problem, and when using a fluorine-containing gas in the dry etching method of the insulating film by using a photoresist pattern by using a mixture of the gas is an endothermic reaction and the gas is an exothermic reaction The purpose of the present invention is to prevent erosion of the insulating layer and to prevent cracking of the insulating layer hole pattern, thereby improving reliability and yield of the semiconductor device.
이와 같은 목적을 실현하기 위한 본 발명에 따른 반도체 소자의 절연막 식각 방법은, 반도체 기판 상에 산화물 계열의 절연물을 증착하여 절연막을 형성하는 제 1 단계와, 상기 절연막 위에 식각 마스크로서 사용될 물질을 도포 및 패터닝하는 제 2 단계와, 식각 반응이 발열 반응인 플루오르가 포함된 가스와 흡열 반응인 가스를 혼합 사용하여 상기 식각 마스크를 통해 상기 절연막을 선택적으로 건식 식각하여 콘택홀을 형성하는 제 3 단계를 포함한다.In order to achieve the above object, an insulating film etching method of a semiconductor device according to the present invention includes a first step of forming an insulating film by depositing an oxide-based insulating material on a semiconductor substrate, and applying and using a material to be used as an etching mask on the insulating film. A second step of patterning, and a third step of selectively dry-etching the insulating film through the etching mask by using a mixture of fluorine-containing gas and an endothermic gas in which the etching reaction is exothermic; do.
도 1은 반도체 소자의 절연막 식각 방법을 설명하기 위한 소자 단면도,1 is a cross-sectional view of a device for explaining an insulating layer etching method of a semiconductor device;
도 2는 종래 기술에 따른 절연막 식각 공정 이후의 소자 단면도,2 is a cross-sectional view of a device after an insulating film etching process according to the prior art;
도 3은 본 발명에 따른 절연막 식각 공정 이후의 소자 단면도,3 is a cross-sectional view of the device after the insulating film etching process according to the present invention;
도 4a 및 도 4b는 발열 반응과 흡열 반응에서의 에너지 변화 그래프.4A and 4B are graphs of energy change in an exothermic reaction and an endothermic reaction.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 기판1: substrate
3 : 절연막3: insulation film
5 : 포토레지스트 패턴5: photoresist pattern
본 발명의 실시예로는 다수개가 존재할 수 있으며, 이하에서는 첨부한 도면을 참조하여 바람직한 실시예에 대하여 상세히 설명하기로 한다. 이 실시예를 통해 본 발명의 목적, 특징 및 이점들을 보다 잘 이해할 수 있게 된다.There may be a plurality of embodiments of the present invention. Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. This embodiment allows for a better understanding of the objects, features and advantages of the present invention.
본 발명에 따른 반도체 소자의 절연막 식각 방법을 도 1 및 도 3을 참조하여 설명하면 다음과 같다.An insulating film etching method of a semiconductor device according to the present invention will be described with reference to FIGS. 1 and 3 as follows.
먼저, 기판(1) 상에 식각하고자 하는 물질, 예컨대 실리콘산화물 계열의 절연물(SiO2 등)을 증착하여 절연막(3)을 형성하고, 그 위에 식각 마스크로서 사용될 물질, 예컨대 포토레지스트를 도포하여 포토레지스트층(도시되지 않음)을 형성한다.First, a material to be etched, such as a silicon oxide-based insulator (SiO2, etc.) is deposited on the substrate 1 to form an insulating film 3, and then a material to be used as an etching mask, for example, a photoresist, is coated on the photoresist. Forms a layer (not shown).
다음, 상기 포토레지스트층을 패터닝하여, 식각하고자 하는 부분(빗금친 부분)을 노출시키는 포토레지스트 패턴(5)을 형성하고, 절연막(3)을 선택적으로 건식 식각하여 콘택홀을 형성한다.Next, the photoresist layer is patterned to form a photoresist pattern 5 exposing portions to be etched (hatched portions), and the insulating layer 3 is selectively dry etched to form contact holes.
상기의 건식 식각 공정에서 식각 반응이 발열 반응인 가스와 흡열 반응인 가스를 혼합 사용한다. 일예로, 식각 반응이 발열 반응인 플루오르가 포함된 가스(CF4, C4F8, C2F6, CHF3 등)와 흡열 반응인 N2 가스를 함께 사용한다. 이러한 건식 식각 공정의 화학반응식은 『xSiO2+xC+xN2 → xCO+xCO2+xNO』이다.In the dry etching process, a gas in which the etching reaction is an exothermic reaction and a gas in which the endothermic reaction is mixed are used. For example, a fluorine-containing gas (CF4, C4F8, C2F6, CHF3, etc.) having an exothermic reaction and an N2 gas having an endothermic reaction are used together. The chemical reaction of the dry etching process is 『xSiO 2 + xC + xN 2 → xCO + xCO 2 + xNO』.
이때, 산화물 계열의 절연막(3)에서 O2는 C기와 반응하여 CO2로 되면서 발열 반응을 만들게 되지만, 도 4b에 나타낸 바와 같이 N2 가스와 반응하여 NO(↑)로 흡열 반응(N2 + O2 → 2NO - 181kJ)되어 제거된다.At this time, in the oxide-based insulating film 3, O2 reacts with the C group to form CO2, thereby generating an exothermic reaction. However, as shown in FIG. 4B, the endothermic reaction (N2 + O2 → 2NO −) reacts with N2 gas. 181kJ) to be removed.
이로서, 절연막 홀 패턴의 깨짐 현상이 방지되어 도 3에 나타낸 바와 같이절연막 홀 패턴을 반듯하게 만들 수 있다.As a result, cracking of the insulating film hole pattern can be prevented, so that the insulating film hole pattern can be made smooth as shown in FIG.
본 발명의 실험예에 따라 우수한 결과물이 획득된 공정 조건은 다음과 같다.Process conditions for obtaining excellent results according to the experimental example of the present invention are as follows.
플루오르가 포함된 발열 반응 가스로서 C4F8 가스(혹은 C5F8, C2F6)를 사용하는 경우에는 50sccm에서 200sccm 정도의 가스를 주입시키고, N2 가스는 10sccm에서 50sccm 정도의 가스를 주입시킨다. 이때 500watt에서 2500watt정도의 RF 파워를 사용할 수 있다.When using C4F8 gas (or C5F8, C2F6) as an exothermic reaction gas containing fluorine, a gas of about 50 sccm to about 200 sccm is injected, and an N2 gas is about 10 sccm to about 50 sccm gas. At this time, RF power of 500 to 2500 watts can be used.
CF4 가스를 사용하는 경우에는 100sccm에서 500sccm 정도의 가스를 주입시키고, N2 가스는 10sccm에서 50sccm 정도의 가스를 주입시킨다. 이때 500watt에서 2500watt정도의 RF 파워를 사용할 수 있다.In the case of using CF4 gas, gas of about 100 sccm to about 500 sccm is injected, and N2 gas is about 10 sccm to about 50 sccm. At this time, RF power of 500 to 2500 watts can be used.
상기에서는 본 발명의 일 실시예에 국한하여 설명하였으나 본 발명의 기술이 당업자에 의하여 용이하게 변형 실시될 가능성이 자명하다. 이러한 변형된 실시예들은 본 발명의 특허청구범위에 기재된 기술사상에 포함된다고 하여야 할 것이다.In the above description, but limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.
전술한 바와 같이 본 발명은 플루오르가 포함된 가스를 이용하여 건식 방식으로 절연막을 식각할 때에 식각 반응이 발열 반응인 가스와 흡열 반응인 가스를 혼합 사용함으로써, 발열 반응에 의한 포토레지스트 패턴의 침식을 막아주어 절연막 홀 패턴의 깨짐 현상을 방지하여 반도체 소자의 신뢰성 및 수율이 향상되는 효과가 있다.As described above, in the present invention, when etching the insulating film in a dry manner using a gas containing fluorine, the photoresist pattern is eroded by exothermic reaction by mixing the gas having the exothermic reaction with the gas having the endothermic reaction. This prevents cracking of the insulating film hole pattern, thereby improving reliability and yield of the semiconductor device.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980014993A (en) * | 1996-08-19 | 1998-05-25 | 김주용 | Method of forming a contact hole in a semiconductor device |
| KR19990065499A (en) * | 1998-01-14 | 1999-08-05 | 구본준 | Plug Formation Method |
| KR19990069180A (en) * | 1998-02-05 | 1999-09-06 | 윤종용 | Dry etching method of thin film for semiconductor device manufacturing |
| KR100257771B1 (en) * | 1997-12-30 | 2000-06-01 | 김영환 | Method for forming contact hole with different depth of semiconductor device |
| KR20010023462A (en) * | 1997-08-28 | 2001-03-26 | 리차드 에이치. 로브그렌 | Method for selective plasma etch |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980014993A (en) * | 1996-08-19 | 1998-05-25 | 김주용 | Method of forming a contact hole in a semiconductor device |
| KR20010023462A (en) * | 1997-08-28 | 2001-03-26 | 리차드 에이치. 로브그렌 | Method for selective plasma etch |
| KR100257771B1 (en) * | 1997-12-30 | 2000-06-01 | 김영환 | Method for forming contact hole with different depth of semiconductor device |
| KR19990065499A (en) * | 1998-01-14 | 1999-08-05 | 구본준 | Plug Formation Method |
| KR19990069180A (en) * | 1998-02-05 | 1999-09-06 | 윤종용 | Dry etching method of thin film for semiconductor device manufacturing |
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