KR20040058907A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20040058907A KR20040058907A KR1020020085425A KR20020085425A KR20040058907A KR 20040058907 A KR20040058907 A KR 20040058907A KR 1020020085425 A KR1020020085425 A KR 1020020085425A KR 20020085425 A KR20020085425 A KR 20020085425A KR 20040058907 A KR20040058907 A KR 20040058907A
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- film
- interlayer insulating
- etching
- capping
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000011229 interlayer Substances 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 230000009977 dual effect Effects 0.000 claims abstract description 9
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히, 금속 배선 공정의 층간 절연막 층착 공정과 듀얼 다마신 패턴의 금속 배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an interlayer insulating film layering step of a metal wiring step and a metal wiring forming step of a dual damascene pattern.
CMOS 로직 디바이스(Logic Device)의 속도를 향상시키기 위해 주로 게이트의 길이(Gate Length)를 감소 시켜 게이트 딜레이 타임(Gate Delay Time)을 줄이는 것에 의존하여 왔다. 하지만 소자가 집적 화될수록 백 앤드 오브 라인(Back End Of Line; BEOL)의 금속화(Metalization)에 의한 RC(Resistance Capacitance) 딜레이(Delay)가 소자의 속도(Device Speed)를 좌우하게 되었다. 이러한 RC 딜레이를 줄이기 위해 저항이 낮은 구리(Cu)를 메탈로 적용하고 유전체(Dielectric)로 저유전율(Low-k)의 물질을 사용하여 비아 홀(Via Hole)과 메탈 배선을 동시에 형성하는 듀얼 다마신(Dual Damascene) 방법을 사용한다.In order to improve the speed of CMOS logic devices, we have relied mainly on reducing the gate delay time by reducing the gate length. However, as the device is integrated, the resistance capacitance delay caused by the metallization of the back end of the line (BEOL) determines the device speed. In order to reduce the RC delay, a low-resistance copper (Cu) is used as a metal, and a dielectric material is used to form a via hole and a metal wiring at the same time using a low-k dielectric material. Use the Dual Damascene method.
듀얼 다마신 패턴에서 사용하는 저유전율의 물질은 수분 흡수나 후속 공정에 의한 데미지(Damage)가 심하게 발생한다. 이를 방지하기 위해 저 유전율의 물질 상부에 이를 보호하기 위한 캡핑막으로 PETEOS 또는 질화막(SiN, SiON 또는 Si3N4)을 증착한다.Low dielectric constant materials used in the dual damascene pattern are severely damaged by water absorption or subsequent processes. In order to prevent this, a PETEOS or a nitride film (SiN, SiON or Si 3 N 4 ) is deposited as a capping film to protect the upper dielectric material.
일반적으로, 질화막(Si3N4; K=~ 7)은 산화막(SiO2; K=~ 4.0) 보다 높은 유전율을 가지고 있기 때문에 이를 캡핑막으로 사용하게 되면 인터 커패시턴스(Inter Capacitance)를 증가시키는 요인으로 작용하여 소자의 특성을 악화시킨다.In general, since the nitride film (Si 3 N 4 ; K = ~ 7) has a higher dielectric constant than the oxide film (SiO 2 ; K = ~ 4.0), when used as a capping film, the factor of increasing the intercapacitance is increased. It acts as a deterioration of device characteristics.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 비하 홀 형성후 포토레지스트 스트립 공정에서 다운 스트림 방식의 O2플라즈마를 이용하여 스트립과 동시에 산화막을 형성하여, 캡핑막 증착을 위한 별도의 추가적인 장비나 공정을 수행하지 않고 인터 커패시턴스를 줄일 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problems, the present invention forms an oxide film simultaneously with the strip using O 2 plasma in a downstream method in a photoresist strip process after forming a bore hole, and thus additional additional equipment or process for capping film deposition. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of reducing intercapacitance without performing the above.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들 이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 구조물 12 : 하부 금속 배선10 semiconductor structure 12 lower metal wiring
14 : 캡핑막 16 : 층간 절연막14 capping film 16 interlayer insulating film
18, 26 : 감광막 패턴 20 : 비아홀18, 26: photosensitive film pattern 20: via hole
22 : 캡핑 산화막 24 : 유기 반사방지막22 capping oxide film 24 organic antireflection film
28 : 트랜치 30 : 상부 금속 배선28: trench 30: upper metal wiring
본 발명에 따른 하부 금속 배선이 형성된 반도체 구조물 상에 캡핑막과 층간 절연막을 형성하는 단계와, 상기 층간 절연막 상에 비아홀 형성을 위한 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 식각마스크로 하여 상기 층간절연막을 식각하여 비아홀을 형성하는 단계와, O2플라즈마를 이용한 식각을 실시하여 상기 감광막 패턴을 제거함과 동시에 상기 층간 절연막 상부에 캡핑 산화막을 형성하는 단계와, 상기 캡핑 산화막과 상기 층간 절연막의 일부를 식각하여 상기 비아홀 보다 넓은 개구부를 갖는 상부 금속 배선용 트랜치를 형성하는 단계와, 상기 비아홀을 통해 노출된 상기 캡핑막을 제거하는 단계와, 전기도금 방법으로 상기 비아홀과 상기 트랜치를 금속으로 매립하여 상부 금속배선을 형성하는 단계 및 열처리 공정과 상기 상부 금속배선의 평탄화 공정을 실시하여 듀얼 다마신 구조의 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.Forming a capping layer and an interlayer insulating layer on the semiconductor structure on which the lower metal wiring is formed, forming a photoresist pattern for forming a via hole on the interlayer insulating layer, and using the photoresist pattern as an etching mask Forming a via hole by etching the interlayer insulating film, etching using O 2 plasma to remove the photoresist pattern, and simultaneously forming a capping oxide film on the interlayer insulating film, and a part of the capping oxide film and the interlayer insulating film. Etching to form an upper metal wiring trench having an opening wider than the via hole, removing the capping film exposed through the via hole, and filling the via hole and the trench with metal by an electroplating method. Forming a wiring and a heat treatment process and the upper metal It provides a method of manufacturing a semiconductor device comprising the step of performing a planarization process of the wiring to form a metal wiring of a dual damascene structure.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들 이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 1a를 참조하면, 트렌지스터 및 커패시터를 포함하는 반도체 소자가 형성되고, 또한 싱글 다마신(Single damascene)공정을 이용하여 하부 금속 배선(Under Metal line; 12)이 형성된 반도체 구조물(10) 상에 메탈의 확산을 방지하기 위한 하부 캡핑막(Bottom Capping Barrier Layer; 14)을 형성한다. 하부 금속 배선(12)으로는 구리(Cu)를 사용하고, 캡핑막(14)은 질화막을 약 500Å의 두께로 증착하여 형성한다.Referring to FIG. 1A, a semiconductor device including a transistor and a capacitor is formed, and a metal is formed on the semiconductor structure 10 on which an under metal line 12 is formed using a single damascene process. Bottom Capping Barrier Layer 14 is formed to prevent diffusion. Copper (Cu) is used as the lower metal wiring 12, and the capping film 14 is formed by depositing a nitride film with a thickness of about 500 kPa.
도 1b를 참조하면, 캡핑막(14) 상에 층간 절연막(16)을 증착한다. 층간 절연막(16) 상부에 감광막(Photoresist)을 도포한 후 비아 포토 마스크(Via Photomask)를 이용한 포토리소그라피(Photolithography) 공정을 실시하여 제 1 감광막 패턴(18)을 형성한다. 층간 절연막(16)은 저 유전율의 인터 메탈 다이일렉트릭 (Inter Metal Dielectric; IMD)물질인 SiOC를 4000 내지 5000Å의 두께로 증착하여 형성한다. SiOC는 실리콘(Silicon)과 산소(Oxygen)로 구성된 케이지(Gage)구조에카본(Carbon)이 다량 도핑(Doping)되어 있다. 상기 감광막은 제 1 감광막패턴(18)의 가장자리의 거칠기(Edge Roughness)를 최소화하기 위해 분자량(Molecular Weight)이 작은 물질을 사용한다.Referring to FIG. 1B, an interlayer insulating layer 16 is deposited on the capping layer 14. After the photoresist is applied on the interlayer insulating layer 16, a photolithography process using a via photomask is performed to form a first photoresist pattern 18. The interlayer insulating layer 16 is formed by depositing SiOC, which is a low dielectric intermetal dielectric (IMD) material, at a thickness of 4000 to 5000 kPa. SiOC has a large amount of carbon doped in a cage structure composed of silicon and oxygen. The photoresist uses a material having a low molecular weight in order to minimize edge roughness of the edge of the first photoresist pattern 18.
도 1c를 참조하면, 제 1 감광막 패턴(18)을 식각마스크로 하는 식각공정을 실시하여 하부 금속 배선(12) 상부에 비아홀(20)을 형성한다. O2플라즈마를 이용한 식각공정을 실시하여 제 1 감광막 패턴(18)을 제거함과 동시에 층간 절연막(16) 상부에 층간 절연막(16)을 보호하기 위한 캡핑 산화막(22)을 형성한다.Referring to FIG. 1C, the via hole 20 is formed on the lower metal wire 12 by performing an etching process using the first photoresist pattern 18 as an etching mask. An etching process using an O 2 plasma is performed to remove the first photoresist layer pattern 18 and to form a capping oxide layer 22 to protect the interlayer insulation layer 16 on the interlayer insulation layer 16.
구체적으로, 비아홀(20) 형성을 위한 식각은 캡핑막(14) 보다 층간 절연막(16)이 식각에 대한 높은 선택비를 갖는 식각을 실시하여 노출된 층간 절연막(16)을 제거한다. 층간절연막(16)을 제거하기 위해 C/F율이 높은 C4F8또는 C5F8과 같은 가스를 사용하여 폴리머를 다량 발생하게 하거나, 하부 기판의 온도를 20 내지 40℃의 높은 온도에서 식각을 실시하여 하부에 적층되는 폴리머 구조를 카본성분이 많이 함유된 폴리머구조(CFx)로 변화시킨다. 또한, 층간절연막(16)은 낮은 유전물질인 SiOC를 이용하여 형성되어 있다. 따라서, 층간절연막(16) 식각시 C4F8또는 C5F8을 과다하게 적용할 경우 산소에 비해 물질 자체에 카본이 다량 함유되어 있어서 식각 정지가 발생하게 될 수 있다. 이를 방지하기 위하여 가스의 유량을 조절하고, 저유전율의 층간절연막(16)의 손상을 최소화하기 위해 N2가스를 적용한다. 상술한 원인에 의해 층간절연막(16)의 일부를 식각하기 위한 구체적인 식각 조건은다음과 같다. 50 내지 80mT의 압력, 1200 내지 1500와트(W)의 소스 파워와 1500 내지 1800와트(W)의 바이어스 파워 하에서, 3 내지 8sccm의 C4F8또는 C5F8가스, 100 내지 200sccm의 N2가스와 400 내지 800sccm의 Ar 가스를 주입하여 식각을 실시한다.Specifically, etching for forming the via hole 20 removes the exposed interlayer insulating layer 16 by etching the interlayer insulating layer 16 having a higher selectivity to etching than the capping layer 14. In order to remove the interlayer insulating film 16, a large amount of polymer may be generated using a gas such as C 4 F 8 or C 5 F 8 having a high C / F ratio, or the lower substrate may be heated at a high temperature of 20 to 40 ° C. Etching is performed to change the polymer structure stacked below to a polymer structure containing a large amount of carbon (CFx). The interlayer insulating film 16 is formed using SiOC, which is a low dielectric material. Therefore, when C 4 F 8 or C 5 F 8 is excessively applied when the interlayer insulating layer 16 is etched, a large amount of carbon may be contained in the material itself compared to oxygen, thereby causing etch stop. In order to prevent this, the flow rate of the gas is adjusted, and N 2 gas is applied to minimize damage of the interlayer insulating film 16 having a low dielectric constant. Specific etching conditions for etching a part of the interlayer insulating film 16 due to the above-described causes are as follows. Under a pressure of 50 to 80 mT, a source power of 1200 to 1500 watts (W) and a bias power of 1500 to 1800 watts (W), 3 to 8 sccm of C 4 F 8 or C 5 F 8 gas, 100 to 200 sccm of N 2 Etching is performed by injecting a gas and 400 to 800 sccm of Ar gas.
비아홀(20) 형성 후 0 내지 100℃ 이하의 낮은 온도에서 다운 스트림 방식의 O2플라즈마를 이용한 비등방성 식각을 실시하여 제 1 감광막 패턴(18)을 제거한다. 이때 O2플라즈마와 층간 절연막(16)이 반응하여 캡핑 산화막(22)을 형성하게 된다.After the via hole 20 is formed, the first photoresist pattern 18 is removed by anisotropic etching using a downstream O 2 plasma at a low temperature of 0 to 100 ° C. or less. At this time, the O 2 plasma and the interlayer insulating layer 16 react to form the capping oxide layer 22.
O2플라즈마와 층간 절연막(16)의 반응식은 다음과 같다.The reaction scheme of the O 2 plasma and the interlayer insulating film 16 is as follows.
SiOC + O2-> SiO2+ CO2 SiOC + O 2- > SiO 2 + CO 2
상기의 화학식과 같이 O2플라즈마와 층간 절연막(16)을 이루고 있는 SiOC가 반응하여 SiO2가 생성되고, 다운 스트림 방식으로 인해 층간 절연막(16) 상부에만 캡핑 산화막(22)이 형성된다. 공정 조건을 살펴 보면, 10 내지 100mT의 압력, 1200 내지 1500와트(W)의 소스 파워와 100 내지 200와트(W)의 바이어스 파워 하에서, 100 내지 300sccm의 O2가스를 주입하여 제 1 감광막 패턴(18)의 스트립을 실시한다.As described above, SiO 2 is formed by reacting the O 2 plasma with the SiOC forming the interlayer insulating layer 16, and the capping oxide layer 22 is formed only on the interlayer insulating layer 16 due to the downstream method. Referring to the process conditions, under a pressure of 10 to 100 mT, a source power of 1200 to 1500 watts (W) and a bias power of 100 to 200 watts (W), 100 to 300 sccm of O 2 gas is injected to form a first photoresist pattern ( Perform the strip 18).
100℃ 이하의 낮은 온도에서 형성된 O2플라즈마를 이용하기 때문에 층간 절연막(16)에는 열에 의해 층간 절연막이 열화되는 것을 방지할 수 있다. O2플라즈마를 이용한 식각공정의 시간을 조절(오버 스트립 되는 비율에 따라 조절)함으로써층간 절연막(16) 상부에 형성되는 캡핑 산화막(22)의 두께를 조절할 수 있다.Since the O 2 plasma formed at a low temperature of 100 ° C. or less is used, the interlayer insulating film 16 can be prevented from deteriorating due to heat. The thickness of the capping oxide layer 22 formed on the interlayer insulating layer 16 may be adjusted by adjusting the time of the etching process using the O 2 plasma (based on the ratio of overstriping).
도 1d를 참조하면, 회전 도포 방식을 이용하여 유기 반사방지막(Organic BARC; 24)을 도포하여 비아 홀(20)을 매립한다. 감광막 도포한 후 트랜치 포토 마스크(Trench Photomask)를 이용한 포토리소그라피(Photolithography) 공정을 실시하여 제 2 감광막 패턴(26)을 형성한다. 유기 반사 방지막(24)을 도포함으로써 비아홀(20)에 의해 제 2 감광막 패턴(26)이 왜곡되는 현상을 방지할 수 있다. 상기 감광막은 제 2 감광막패턴(26)의 가장자리의 거칠기를 최소화하기 위해 분자량이 작은 물질을 사용한다.Referring to FIG. 1D, the via hole 20 is filled by applying an organic antireflection film 24 using a rotation coating method. After applying the photoresist film, a photolithography process using a trench photomask is performed to form a second photoresist pattern 26. By applying the organic anti-reflection film 24, the phenomenon in which the second photosensitive film pattern 26 is distorted by the via hole 20 can be prevented. The photoresist uses a material having a low molecular weight in order to minimize the roughness of the edge of the second photoresist pattern 26.
도 1e를 참조하면, 제 2 감광막 패턴(26)을 식각마스크로 하는 식각공정을 실시하여 유기 반사 방지막(24)을 제거하고, 캡핑 산화막(22) 및 층간 절연막(16)의 일부를 제거하여 상부 금속 배선용 트랜치(28)를 형성한다. 제 2 감광막 패턴(26)과 잔류하는 유기 반사 방지막(24)을 제거하고, 하부 금속 배선(12)과 연결을 위해 비아홀(20) 하부에 노출된 캡핑막(14)을 제거하여 듀얼 다마신 패턴을 형성한다.Referring to FIG. 1E, an etch process using the second photoresist layer pattern 26 as an etch mask is performed to remove the organic antireflection layer 24, and a portion of the capping oxide layer 22 and the interlayer insulating layer 16 is removed. A metal wiring trench 28 is formed. The dual damascene pattern is removed by removing the second photoresist layer pattern 26 and the remaining organic anti-reflection layer 24, and removing the capping layer 14 exposed under the via hole 20 for connection with the lower metal line 12. To form.
구체적으로, 상기 금속 배선용 트랜치(28) 형성을 위한 식각 공정은 바이어스드 O2플라즈마를 이용하여 유기 반사 방지막(24)을 제거한 다음, C4F8가스, N2가스 또는 Ar 가스를 활성화한 플라즈마를 이용한 식각을 실시하여 캡핑 산화막(22) 및 층간 절연막(16)의 일부를 제거하여 상부 금속 배선용 트랜치(28)를 형성한다. 100℃ 이하의 낮은 온도에서 다운 스트림 방식의 O2플라즈마를 이용한비등방성 식각을 실시하여 제 2 감광막 패턴(26)과 캡핑 산화막(22) 상부에 잔류하는 유기 반사 방지막(24)을 제거한다. 이때, 트랜치(28) 형성을 위해 실시하는 다운 스트림 방식의 O2플라즈마를 이용한 비등방성 식각에 있어서는 트랜치(28) 상부(노출된 캡핑 산화막)의 산화막은 SiO2의 강한 결합에 의해 더 이상 두껍게 성장하지 않는다. 캡핑막(14)은 CF4가스, CHF3가스, O2가스 또는 Ar 가스를 활성화한 플라즈마 건식 식각방법을 이용하여 식각한다. 상술한 식각공정들에서 발생할 수 있는 폴리머(Polymer)를 제거하기 위한 클리닝 공정을 실시한다.Specifically, in the etching process for forming the trench 28 for metal wiring, the organic anti-reflective film 24 is removed using a biased O 2 plasma, and then plasma activated with C 4 F 8 gas, N 2 gas, or Ar gas. Etching is performed to remove the capping oxide layer 22 and a part of the interlayer insulating layer 16 to form the upper metal wiring trench 28. Anisotropic etching using a downstream O 2 plasma at a temperature lower than 100 ° C. is performed to remove the organic anti-reflection film 24 remaining on the second photoresist pattern 26 and the capping oxide layer 22. At this time, in anisotropic etching using the downstream O 2 plasma to form the trench 28, the oxide film on the upper portion of the trench 28 (exposed capping oxide) is grown thicker by the strong bonding of SiO 2 . I never do that. The capping layer 14 is etched using a plasma dry etching method in which CF 4 gas, CHF 3 gas, O 2 gas, or Ar gas is activated. A cleaning process is performed to remove polymers that may occur in the above etching processes.
도 1f를 참조하면, 비아홀(20)과 트랜치(28)로 구성된 듀얼 다마신 패턴의 단차를 따라 시드층(미도시)을 증착한 다음 전기도금 방법으로 상부 금속 배선(30)을 형성한다. 열공정과 CMP(Chemical Vaper Deposition)를 이용한 평탄화 공정을 실시하여 듀얼 다마신 구조의 금속 배선을 형성한다.Referring to FIG. 1F, a seed layer (not shown) is deposited along a step of a dual damascene pattern composed of a via hole 20 and a trench 28, and then an upper metal wiring 30 is formed by an electroplating method. The thermal process and the planarization process using the chemical vapor deposition (CMP) are performed to form a dual damascene structure metal wiring.
상술한 바와 같이, 본 발명은 층간 절연막 상부에 캡핑 산화막을 감광막 패턴 제거 공정에서 형성함으로 별도의 장착 장비를 사용하지 않고도 형성 할 수 있고, 이로써 공정을 단순화할 수 있다.As described above, the present invention can be formed without using a separate mounting equipment by forming a capping oxide film on the interlayer insulating film in the photosensitive film pattern removal process, thereby simplifying the process.
또한 유전율이 작은 SiO2산화막을 캡핑 산화막으로 형성하기 때문에 인터 커패시턴스를 줄일 수 있다.In addition, since the SiO 2 oxide film having a low dielectric constant is formed as a capping oxide film, intercapacitance can be reduced.
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| KR100840665B1 (en) * | 2007-05-18 | 2008-06-24 | 주식회사 동부하이텍 | A method for manufacturing a semiconductor device and system in package usimg the same |
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