KR19990055770A - Method for manufacturing metal wiring of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a metal wiring of a semiconductor device, in order to form a metal wiring using a copper film, a hard mask and an etch barrier layer are formed on and under the metal wiring, and after etching the wiring, spacers are formed for sidewall protection, and then planarized. By performing the step and subsequent metallization step, the present invention relates to a technology that can improve the reliability of the device by preventing the atoms of the copper thin film easily diffused into the silicon substrate or the oxide film to reduce the characteristics of the device.

Description

Method for manufacturing metal wiring of semiconductor device

The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, and the reliability of the device by forming a hard mask and an etching barrier layer above and below the metal wiring to prevent the copper atoms penetrate into the silicon substrate or oxide when using the Cu film as the lower metal wiring It is about a technology that can improve.

In general, after the semiconductor devices are formed with respective devices, metal wirings for applying a voltage to each device are formed on the uppermost layer of the device.

As the metal wiring, an Al-based metal having a simple deposition process and a low resistance characteristic is used, compared to other materials. In the case of an Al-based metal wiring contact, the diffusion of spikes or impurities in a portion in contact with the metal layer is used. In order to prevent this problem, a metal wiring layer having a Ti / TiN / Al lamination structure has been used between the contact surface and the metal wiring.

In recent years, a copper thin film, which is considered to be a metal wiring film material of a next-generation semiconductor device, has been applied as a wiring material.

However, copper atoms are easily oxidized because the atoms are very small in size and have a high chemical affinity, and thus have a problem in that the characteristics of the device are greatly deteriorated by being easily diffused into a silicon substrate or an oxide film.

Accordingly, the present invention is to solve the above problems and to form a TiN film with an Al ₂ O ₃ film and an etch barrier layer as a hard mask on the upper and lower Cu film formed by the lower metal wiring, PESiN film or Si ₃ N ₄ on the side wall It is an object of the present invention to provide a method for manufacturing a metal wiring of a semiconductor device in which a copper atom is prevented from penetrating into a silicon substrate or an oxide film to improve the reliability of the device by forming a spacer as a film.

1a to 1d is a manufacturing process diagram of the metal wiring of the semiconductor device according to the present invention

<Explanation of symbols for main parts of the drawings>

10 semiconductor substrate 12 first insulating film

14: first etching barrier layer 16: Cu film

18: Al ₂ O ₃ film 20: spacer

22: interlayer insulating film

According to the present invention to achieve the above object,

Sequentially forming a first insulating film, a first etching barrier layer, a metal wiring, and an Al ₂ O ₃ film on the semiconductor substrate having a predetermined substructure;

And a step of forming a first etch barrier layer to the dry etching in order Al ₂ O ₃ film pattern and a metal wiring pattern, a first etch barrier layer pattern as an etch mask in the Al ₂ O ₃ film,

Forming a second etching barrier layer on the entire surface of the structure and etching back to form spacers surrounding sidewalls of the Al ₂ O ₃ film pattern, the wiring metal wiring pattern, and the first etching barrier layer pattern;

And forming an interlayer insulating film on the entire surface of the structure to planarize it.

Hereinafter, a metal wire manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are diagrams illustrating a process for manufacturing metallization of a semiconductor device according to the present invention.

First, predetermined lower structures such as a device isolation oxide film, a MOS field effect transistor, a bit line, a capacitor, and the like are formed on the semiconductor substrate 10, and the first insulating film 12 made of an oxide film on the entire surface of the structure. To form.

In this case, the first insulating layer 12 is formed of one film from the group consisting of a CVD-oxide film, a Boro phosphor silicate glass (BPSG) film, and a spin on glass (SOG) film.

Next, a first etching barrier layer 14 is formed on the first insulating layer 12, a Cu layer 16 is formed by a lower metal wiring, and an Al ₂ O ₃ layer 18 is formed by a hard mask. do.

In this case, the first etching barrier layer 14 is formed of one film from the group consisting of a TiN film, a SiON film, a CrN film, a CoN film, and a WN film.

Here, the Cu film 16 and the Al ₂ O ₃ film 18 are formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

Preferably, the metal wiring may be formed as one film from the group consisting of Au film, Ag film, Co film, Cr film, and Pt film having similar characteristics to the Cu film 16. (See Fig. 1A. )

Then, the Al ₂ O as a dry etching (plasma etching) process of the _third membrane (18) 25 ~ 300 ℃ temperature using an etch mask in a first etch barrier layer 14 by etching in order Al ₂ O ₃ film (18) A pattern, a Cu film 16 pattern, and a first etching barrier layer 14 pattern are formed.

At this time, the first etching barrier layer 14 is to prevent the copper atoms of the Cu film 16 formed by the lower metal wiring from penetrating into the semiconductor substrate 10 or the first insulating film 12 (Fig. 1B). Reference)

Next, a second etching barrier layer is formed on the entire surface of the structure and etch-back etched to form the Al ₂ O ₃ film 18 pattern, the Cu film 16 pattern, and the first etching barrier layer 14. The spacer 20 surrounding the pattern sidewall is formed.

In this case, the second etching barrier layer is formed of a PESiN film or Si ₃ N ₄ film and serves as a sidewall protection (see FIG. 1C).

Then, the interlayer insulating film 22 is formed and planarized on the entire surface of the structure, and then a smooth wiring can be formed by performing a metal wiring process of a subsequent process.

In this case, the interlayer insulating layer 22 is formed of a spin on glass (SOG) film or a boro phosphor silicate glass (BPSG) film. (See FIG. 1D)

As described above, according to the present invention, by using a Cu film as a metal wiring between the etch barrier layer and the hard mask, copper atoms can be prevented from penetrating into the silicon substrate or the oxide film, and electrical conductivity, electromigration, and stress migration can be prevented. It is possible to form a smooth wiring and improve the electrical characteristics and reliability of the device.

Claims (6)

Sequentially forming a first insulating film, a first etching barrier layer, a metal wiring, and an Al ₂ O ₃ film on the semiconductor substrate having a predetermined substructure; And a step of forming a first etch barrier layer to the dry etching in order Al ₂ O ₃ film pattern and a metal wiring pattern, a first etch barrier layer pattern as an etch mask in the Al ₂ O ₃ film, Forming a second etching barrier layer on the entire surface of the structure and etching back to form spacers surrounding sidewalls of the Al ₂ O ₃ film pattern, the wiring metal wiring pattern, and the first etching barrier layer pattern; And forming an interlayer insulating film on the entire surface of the structure to planarize it. 2. The method of claim 1, wherein the first insulating film is formed of one film from the group consisting of a CVD oxide film, a BPSG film, and an SOG film. The method of claim 1, wherein the first etching barrier layer is formed of one film from the group consisting of a TiN film, SiON film, CrN film, CoN film, WN film, the second etching barrier layer is a PESiN film or Si ₃ N _{4. A} method for manufacturing metal wiring in a semiconductor device, characterized in that formed of _four films. The method of claim 1, wherein the Al ₂ O ₃ film and the metal wiring are formed by a CVD method or a PVD method. The method of claim 1, wherein the dry etching process is performed at a temperature of 25 ° C. to 300 ° C. 6. The method of claim 1, wherein the metal wiring is formed of one film from a group consisting of a Cu film, an Au film, an Ag film, a Co film, a Cr film, and a Pt film.