KR19990061043A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19990061043A KR19990061043A KR1019970081297A KR19970081297A KR19990061043A KR 19990061043 A KR19990061043 A KR 19990061043A KR 1019970081297 A KR1019970081297 A KR 1019970081297A KR 19970081297 A KR19970081297 A KR 19970081297A KR 19990061043 A KR19990061043 A KR 19990061043A
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- metal wiring
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체기판 상부에 제1금속배선을 형성하고 전체표면상부에 HDP-USG 막으로 제1층간절연막을 일정두께 형성한 다음, 상기 제1층간절연막 상부에 고농도의 HDP-FSG 막을 형성하고 상기 고농도의 HDP-FSG 막 상부에 저농도의 HDP-FSG 막을 형성한 다음, 상기 저농도의 HDP-FSG 막을 CMP 하고 후공정에서 비아콘택공정으로 제2금속배선을 형성하여 상하 좌우측 금속배선 간의 기생 캐패시턴스를 감소시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키며 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising forming a first metal wiring on an upper surface of a semiconductor substrate, forming a first interlayer insulating film with a HDP-USG film on the entire surface, and then forming the first interlayer insulating film. A high concentration of HDP-FSG film is formed on the top, a low concentration of HDP-FSG film is formed on the high density HDP-FSG film, CMP the low concentration of HDP-FSG film, and the second metal wiring is formed by a via contact process in a subsequent process. It is a technology to reduce the parasitic capacitance between the upper and lower left and right metal wiring, thereby improving the characteristics and reliability of the semiconductor device and to enable high integration of the semiconductor device.
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 금속배선층 간에 사용되는 층간절연막을 에프.에스.지. ( fluorinated silicate glass, 이하에서 FSG 라 함 ) 로 형성하여 기생 캐패시턴스를 감소시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. (fluorinated silicate glass, hereinafter referred to as FSG) relates to a technique that can reduce the parasitic capacitance.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착 ( Physical Vapor Deposition, 이하에서 PVD 라 함 ) 방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법이 가장 널리 이용되고 있다.The metal wiring includes a small amount of silicon or copper in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. The method of filling the contact hole and the via hole by sputtering of the method is most widely used.
상기 스퍼터링방법은, 화학기상증착 ( chemical vapor deposition, 이하에서 CVD 라 함 ) 방법에 비하여 저온에서 실시되며 공정이 단순한 장점이 있으나, 단차피복비가 낮아 고집적화된 반도체소자의 제조공정에는 적용하기 어려운 단점이 있다.The sputtering method is performed at a low temperature compared to chemical vapor deposition (CVD), but the process is simple, but it is difficult to be applied to the manufacturing process of highly integrated semiconductor devices due to low step coverage ratio. have.
이를 해결하기 위하여, 단차피복비가 우수한 화학기상증착 ( chemical vapor deposition, 이하에서 CVD 라 함 ) 방법을 사용하게 되었다.In order to solve this problem, chemical vapor deposition (CVD), which has excellent step coverage ratio, is used.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
먼저, 소자분리막, 워드라인, 비트라인 및 캐패시터가 구비된 평탄화절연막이 형성된 반도체기판(31) 상부에 제1금속배선(33)을 형성한다.First, the first metal wiring 33 is formed on the semiconductor substrate 31 on which the planarization insulating film including the device isolation layer, the word line, the bit line, and the capacitor is formed.
전체표면상부에 제1층간절연막(35)으로 산화막을 일정두께 형성한다.An oxide film is formed to a certain thickness on the entire surface of the first interlayer insulating film 35.
그리고, 상기 제1금속배선(33) 간의 공간을 완전히 매립할 수 있는 특성을 갖는 다시말하면 갭필 ( gap fill ) 특성이 우수한 FSG 막을 제2층간절연막(37)으로 형성하되, 고밀도 플라즈마 화학기상증착 ( high density plasma chemical vapor deposition, 이하에서 HDP CVD 라 함 ) 방법으로 형성한다.In addition, a FSG film having a property of completely filling the space between the first metal wires 33 may be formed as the second interlayer insulating film 37, and the high density plasma chemical vapor deposition ( high density plasma chemical vapor deposition (hereinafter referred to as HDP CVD).
여기서, 상기 제2층간절연막(37)은, 과거에 유전율이 4 이상인 절연막으로 형성하였다.Here, the second interlayer insulating film 37 is formed of an insulating film having a dielectric constant of 4 or more in the past.
한편, 상기 FSG 막의 유전율은 3 ∼ 3.5 정도로 제1금속배선 간의 기생 캐패시턴스를 감소시키나 제1금속배선과 제2금속배선과 같이 상하구조의 금속배선 간의 기생 캐패시턴스가 높은 단점이 있다. 그리고, F 의 농도가 높을수록 유전상수가 감소하나 수분에 취약하여 수분 흡수시 유전상수가 증가하고 금속배선의 부식을 유발할 수 있다. (도 1a)On the other hand, the dielectric constant of the FSG film is reduced to the parasitic capacitance between the first metal wiring to about 3 to 3.5, but the parasitic capacitance between the upper and lower metal wiring, such as the first metal wiring and the second metal wiring has a high disadvantage. In addition, the higher the concentration of F, the lower the dielectric constant, but vulnerable to moisture may increase the dielectric constant upon moisture absorption and cause corrosion of the metallization. (FIG. 1A)
그 다음에, 상기 제2층간절연막(37) 상부에 TEOS 계 산화막으로 제3층간절연막(39)을 형성한다. (도 1b)Next, a third interlayer insulating film 39 is formed on the second interlayer insulating film 37 with a TEOS-based oxide film. (FIG. 1B)
그리고, 상기 제3층간절연막(39)인 TEOS 계 산화막을 평탄화식각한다. 이때, 상기 평탄화식각공정은 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP 라 함 ) 방법으로 실시한다.The TEOS-based oxide film, which is the third interlayer insulating film 39, is planarized and etched. At this time, the planarization etching process is performed by chemical mechanical polishing (hereinafter referred to as CMP) method.
그 다음에, 비아콘택마스크(도시안됨)를 이용한 식각공정으로 상기 제1금속배선(33)을 노출시키는 비아콘택홀(41)을 형성한다. 그리고, 상기 비아콘택홀(41)을 매립하는 콘택플러그(43)를 형성한다.Next, a via contact hole 41 exposing the first metal wiring 33 is formed by an etching process using a via contact mask (not shown). In addition, a contact plug 43 filling the via contact hole 41 is formed.
그리고, 상기 콘택플러그(43)에 접속되는 제2금속배선(45)을 형성한다. (도 1c)Then, the second metal wiring 45 connected to the contact plug 43 is formed. (FIG. 1C)
여기서, 상기 제3층간절연막(39)인 TEOS 계 산화막의 증착공정까지 대기중에 노출시 수분이 흡수될 수 있으며, 상기 화학기계연마 ( CMP ) 공정시 상기 TEOS 계 산화막보다 높은 유동율을 갖는 FSG 막이 플로우되어 금속배선이 손상되는 경우가 발생된다.Here, moisture may be absorbed when exposed to the atmosphere until the deposition process of the TEOS-based oxide film, which is the third interlayer insulating film 39, and the FSG film having a higher flow rate than the TEOS-based oxide film during the chemical mechanical polishing (CMP) process flows. As a result, metal wiring may be damaged.
이상에서 설명한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 반도체소자가 고집적화됨에따라 기생 캐패시턴스로 인한 RC 시간 지연과 전력소모 감소를 위하여 저유전율을 갖는 층간절연막 물질을 필요로 하게 됨으로써 FSG 를 사용하였으나 상하측 금속배선 간의 기생 캐패시턴스가 증가되고 금속배선이 손상될 수 있어 그에 따른 반도체소자의 특성 및 신뢰성을 저하시킬 수 있는 문제점이 있다.As described above, the method of forming a metal wiring of the semiconductor device according to the related art requires an interlayer insulating film material having a low dielectric constant for reducing RC time delay and power consumption due to parasitic capacitance as the semiconductor device becomes highly integrated. Although parasitic capacitance between the upper and lower metal wirings is increased and the metal wirings may be damaged, there is a problem that the characteristics and reliability of the semiconductor device may be deteriorated.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 고농도의 FSG 막과 저농도의 FSG 막 적층구조를 동일장비내에서 층간절연막으로 형성하여 저농도 FSG 막의 CMP 공정으로까지 광역 평탄화를 이룸으로써 상하좌우측 금속배선 간의 기생 캐패시턴스를 감소시키고 CMP 공정으로 인한 손상을 방지할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a high-density FSG film and a low-density FSG film stacking structure are formed as an interlayer insulating film in the same equipment, thereby achieving wide-area flattening to the CMP process of the low-concentration FSG film. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device, which can reduce parasitic capacitance between wirings and prevent damage caused by a CMP process, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device. .
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
도 2a 및 도 2b 는 본 발명의 실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a metal wiring forming method of a semiconductor device in an embodiment of the present invention.
도면의주요부분에대한부호의설명Explanation of symbols on the main parts of the drawing
11,31 : 반도체기판 13,33 : 제1금속배선11,31: semiconductor substrate 13,33: first metal wiring
15,35 : 제1층간절연막 17,37 : 제2층간절연막15,35: first interlayer insulating film 17,37: second interlayer insulating film
19,39 : 제3층간절연막 41 : 비아콘택홀19,39: third interlayer insulating film 41: via contact hole
43 : 콘택플러그 45 : 제2금속배선43: contact plug 45: second metal wiring
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
반도체기판 상부에 제1금속배선을 형성하는 공정과,Forming a first metal wiring on the semiconductor substrate;
전체표면상부에 HDP-USG 막으로 제1층간절연막을 일정두께 형성하는 공정과,Forming a first interlayer insulating film with an HDP-USG film on the entire surface;
상기 제1층간절연막 상부에 고농도의 HDP-FSG 막을 형성하는 공정과,Forming a high concentration HDP-FSG film on the first interlayer insulating film;
상기 고농도의 HDP-FSG 막 상부에 저농도의 HDP-FSG 막을 형성하는 공정과,Forming a low concentration HDP-FSG film on the high concentration HDP-FSG film,
상기 저농도의 HDP-FSG 막을 CMP 하고 후공정에서 비아콘택공정으로 제2금속배선을 형성하는 공정을 포함하는 것을 특징으로한다.CMP the low-concentration HDP-FSG film and forming a second metal wiring by a via contact process in a later step.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 소자분리막, 워드라인, 비트라인 및 캐패시터가 구비된 평탄화절연막이 형성된 반도체기판(11) 상부에 제1금속배선(13)을 형성한다.First, the first metal wiring 13 is formed on the semiconductor substrate 11 on which the planarization insulating film including the device isolation layer, the word line, the bit line, and the capacitor is formed.
전체표면상부에 제1층간절연막(35)으로 HDP-USG 막을 500 ∼ 1000 Å 정도의 두께로 형성하되, SiH4가스와 O2가스를 이용하여 스퍼터링없이 형성한다.An HDP-USG film is formed on the entire surface of the first interlayer insulating film 35 to a thickness of about 500 to 1000 Å, and is formed without sputtering using SiH 4 gas and O 2 gas.
이때, 상기 제1층간절연막(35)인 HDP-USG 막은 후속공정으로 형성되는 FSG 막과 금속배선의 접촉으로 금속배선이 부식되는 현상을 방지하고, 후속공정에서의 스퍼터링으로 인한 금속배선의 코너 클리핑 ( conner clipping ) 을 방지하기 위한 것이다.At this time, the HDP-USG film, which is the first interlayer insulating film 35, prevents corrosion of the metal wiring due to contact between the FSG film formed in a subsequent process and the metal wiring, and corner clipping of the metal wiring due to sputtering in the subsequent process. It is to prevent (conner clipping).
그 다음에, 고농도의 HDP-FSG 막으로 제2층간절연막(17)을 형성하되, SiF4가스의 유량을 증가시켜 F 농도를 7 ∼ 15 % 정도로 한다.Next, the second interlayer insulating film 17 is formed of a high concentration HDP-FSG film, but the F concentration is increased to about 7 to 15% by increasing the flow rate of the SiF 4 gas.
이때, 상기 고농도의 HDP-FSG 막은, 갭필 특성을 위하여 스퍼터링을 동시에 진행한다. 그리고, 상기 고농도의 HDP-FSG 막의 두께는, 금속배선 두께의 0.7 배 이상 적당하게는 0.7 ∼ 3 배 정도의 두께로 형성하되, 후속공정으로 형성되는 상부 금속배선과 접속되지않도록 형성한다. 다시말하면, 후속공정으로 실시되는 CMP 공정시 노출되지않도록 실시한다. (도 2a)At this time, the HDP-FSG film of high concentration, sputtering at the same time for the gap fill characteristics. The high-density HDP-FSG film is formed to have a thickness of about 0.7 to 3 times as much as about 0.7 times or more of the thickness of the metal wiring, but not to be connected to the upper metal wiring formed by a subsequent process. In other words, it is carried out so as not to be exposed during the CMP process performed in the subsequent process. (FIG. 2A)
그 다음, 상기 제2층간절연막(17) 상부에 제3층간절연막(19)을 저농도의 HDP-FSG 막으로 형성하되, SiF4가스의 유량을 감소시켜 F 농도를 3 ∼ 7 % 정도로 하며, 스퍼터링없이 증착공정만 실시함으로써 증착율을 증가시킨다.Next, a third interlayer insulating film 19 is formed on the second interlayer insulating film 17 with a low concentration of HDP-FSG film, and the flow rate of SiF 4 gas is reduced so that the F concentration is about 3-7%, and sputtering is performed. The deposition rate is increased by only performing the deposition process without.
여기서, 상기 제3층간절연막(19)은 CMP 공정시 수분으로 인한 막질의 특성열화를 방지하기 위한 것이다. (도 2b)Here, the third interlayer insulating film 19 is to prevent deterioration of the film quality due to moisture during the CMP process. (FIG. 2B)
후속공정으로 CMP 공정, 비아콘택공정 및 제2금속배선 형성공정을 실시한다.Subsequent processes include a CMP process, a via contact process, and a second metal wiring formation process.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 층간절연막을 HDP-USG, 고농도의 HDP-FSG 및 저농도의 HDP-FSG 의 적층구조로 형성하여 상하 및 좌우측 금속배선의 기생 캐패시턴스를 감소시키고 막질의 특성열화를 방지하여 소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, the parasitic capacitance of the upper and lower sides and the left and right metal wirings is formed by forming the interlayer insulating film in a laminated structure of HDP-USG, HDP-FSG and HDP-FSG. By reducing the quality of the film and preventing the deterioration of the film quality, it is possible to improve the characteristics and reliability of the device, thereby enabling high integration of the semiconductor device.
Claims (5)
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030054782A (en) * | 2001-12-26 | 2003-07-02 | 동부전자 주식회사 | Method of forming metal wiring for semiconductor device |
| KR100505629B1 (en) * | 1999-03-02 | 2005-08-03 | 삼성전자주식회사 | Method for filling a trench |
| KR100687432B1 (en) * | 2005-12-28 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Method of forming an inter-insulating-layer |
| KR100769205B1 (en) * | 2001-12-28 | 2007-10-23 | 매그나칩 반도체 유한회사 | Method for Fabricating of Semiconductor Device |
| KR100781048B1 (en) * | 2006-12-26 | 2007-11-30 | 동부일렉트로닉스 주식회사 | Method for manufacturing pre metal dielectric layer |
| KR100787713B1 (en) * | 2006-12-26 | 2007-12-21 | 동부일렉트로닉스 주식회사 | Method of fabricating semiconductor devices |
| KR100855285B1 (en) * | 2002-06-27 | 2008-09-01 | 매그나칩 반도체 유한회사 | Method of manufacturing semiconductor device |
| KR100910508B1 (en) * | 2007-12-12 | 2009-07-31 | 주식회사 동부하이텍 | Method for flatting surface of wafer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101133513B1 (en) * | 2005-05-27 | 2012-04-05 | 매그나칩 반도체 유한회사 | Inter-metal layer dielectric formming method |
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1997
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505629B1 (en) * | 1999-03-02 | 2005-08-03 | 삼성전자주식회사 | Method for filling a trench |
| KR20030054782A (en) * | 2001-12-26 | 2003-07-02 | 동부전자 주식회사 | Method of forming metal wiring for semiconductor device |
| KR100769205B1 (en) * | 2001-12-28 | 2007-10-23 | 매그나칩 반도체 유한회사 | Method for Fabricating of Semiconductor Device |
| KR100855285B1 (en) * | 2002-06-27 | 2008-09-01 | 매그나칩 반도체 유한회사 | Method of manufacturing semiconductor device |
| KR100687432B1 (en) * | 2005-12-28 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Method of forming an inter-insulating-layer |
| KR100781048B1 (en) * | 2006-12-26 | 2007-11-30 | 동부일렉트로닉스 주식회사 | Method for manufacturing pre metal dielectric layer |
| KR100787713B1 (en) * | 2006-12-26 | 2007-12-21 | 동부일렉트로닉스 주식회사 | Method of fabricating semiconductor devices |
| KR100910508B1 (en) * | 2007-12-12 | 2009-07-31 | 주식회사 동부하이텍 | Method for flatting surface of wafer |
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| KR100271718B1 (en) | 2000-12-01 |
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