KR100781048B1 - Method for manufacturing pre metal dielectric layer - Google Patents

Method for manufacturing pre metal dielectric layer Download PDF

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KR100781048B1
KR100781048B1 KR1020060134214A KR20060134214A KR100781048B1 KR 100781048 B1 KR100781048 B1 KR 100781048B1 KR 1020060134214 A KR1020060134214 A KR 1020060134214A KR 20060134214 A KR20060134214 A KR 20060134214A KR 100781048 B1 KR100781048 B1 KR 100781048B1
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insulating film
interlayer insulating
interlayer dielectric
forming
semiconductor substrate
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KR1020060134214A
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Korean (ko)
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장성호
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming an interlayer dielectric of a semiconductor device is provided to prevent attack of an underlying pattern during a planarization process by planarizing the interlayer dielectric being rounded. A plurality of patterns(102) having constant intervals are formed on a semiconductor substrate(101). An interlayer dielectric(103) is formed on the whole surface of the semiconductor substrate having the patterns. A surface of the interlayer dielectric is formed as a rounded shape by using DHF(Diluted HF) chemical on the whole surface of the interlayer dielectric. A planarization process is performed by selectively polishing the rounded interlayer dielectric. The interlayer dielectric is formed by applying a USG(Undoped Silicate Glass) layer through an HDP(High Density Plasma) manner. The interlayer dielectric is one of a silicon oxide layer, a FSG(Silicon Oxy Fluoride), a low-k dielectric, a BPSG(Boron Phosphorus Silicate Glass).

Description

반도체 소자의 층간 절연막 형성방법{METHOD FOR MANUFACTURING PRE METAL DIELECTRIC LAYER}Method of forming interlayer insulating film of semiconductor device {METHOD FOR MANUFACTURING PRE METAL DIELECTRIC LAYER}

도 1a 내지 도 1b는 종래 기술에 의한 반도체 소자의 층간 절연막 형성방법을 나타낸 공정단면도1A to 1B are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to the related art.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 층간 절연막 형성방법을 나타낸 공정단면도.2A to 2C are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

본 발명에서는 반도체 소자의 층간 절연막 형성방법에 관해 개시된다.The present invention discloses a method for forming an interlayer insulating film of a semiconductor device.

일반적으로 반도체 소자는 기판 상에 다수의 층이 순차 적층되는 구조를 갖는데, 다층 구조에서 각 층간의 전기적인 절연 등을 위해 층간 절연막(PMD : Pre Metal Dielectric Layer)이 필요하다.In general, a semiconductor device has a structure in which a plurality of layers are sequentially stacked on a substrate, and an interlayer insulating layer (PMD) is required for electrical insulation between the layers in a multilayer structure.

이러한 층간 절연막은 센츄라(centura) 장비를 사용하여 기판 상에 형성되며, 층간 절연막 형성 장비는 2∼4개의 챔버들로 구성되어 있고, 필요에 따라 웨이퍼 정렬 챔버를 더 포함하고 있다.The interlayer insulating film is formed on a substrate using centura equipment, and the interlayer insulating film forming equipment is composed of two to four chambers, and further includes a wafer alignment chamber as necessary.

이와 같이 다수의 챔버로 구성된 층간 절연막 형성 장비가 반도체 기판 상에 층간 절연막을 증착하는 공정은 아래와 같다.As described above, a process of depositing an interlayer insulating film on a semiconductor substrate by an interlayer insulating film forming apparatus including a plurality of chambers is as follows.

먼저, 반도체 기판을 첫 번째 챔버에 로딩시킨 후 반도체 기판에 소정 두께를 갖는 절연막을 증착시키는 공정을 수행한 다음 반도체 기판을 배출시키고, 이후 클리닝 공정을 수행하여 첫 번째 챔버에 잔존하는 증착용 가스를 제거한다. First, the semiconductor substrate is loaded into the first chamber, and then a process of depositing an insulating film having a predetermined thickness on the semiconductor substrate is performed. Then, the semiconductor substrate is discharged. Then, the cleaning process is performed to remove the deposition gas remaining in the first chamber. Remove

이러한 과정을 장비 내의 챔버 수만큼 반복적으로 수행하여 다층의 절연막으로 이루어진 층간 절연막을 반도체 기판 상에 형성시킨다.This process is repeated as many as the number of chambers in the equipment to form an interlayer insulating film made of a multilayer insulating film on the semiconductor substrate.

이때 증착 공정을 수행하고 클리닝된 챔버들의 내부에는 완전히 클리닝되지 않고 남은 가스, 예를 들면, TEOS, TEPO가 존재하며, 또한 각각의 챔버들은 일정 시간 동안 휴지 시간, 즉 공정을 수행하지 않는 시간을 갖게 된다.In this case, there are remaining gases that are not completely cleaned, for example, TEOS and TEPO, which are performed after the deposition process and the chambers are cleaned, and each of the chambers has an idle time, that is, a time when the process is not performed. do.

이후, CMP 공정을 진행하여 층간 절연막을 평탄화시킴으로써, 층간 절연막 형성 공정을 완료한다.Thereafter, the CMP process is performed to planarize the interlayer insulating film, thereby completing the interlayer insulating film forming process.

이하, 첨부된 도면을 참고하여 종래 기술에 의한 반도체 소자의 층간 절연막 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming an interlayer insulating film of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 도 1b는 종래 기술에 의한 반도체 소자의 층간 절연막 형성방법을 나타낸 공정 단면도이다.1A to 1B are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to the prior art.

도 1a에 도시한 바와 같이, 반도체 기판(11)상에 일정한 간격을 갖는 플래시 소자의 컨트롤 게이트(12)와 같은 패턴을 형성한다.As shown in FIG. 1A, a pattern similar to that of the control gate 12 of the flash elements having a predetermined interval is formed on the semiconductor substrate 11.

이어서, 상기 컨트롤 게이트(12)를 포함한 반도체 기판(11)의 전면에 층간 절연막(13)으로 사용되어지는 HDP 방식을 이용하여 USG막를 형성한다.Subsequently, a USG film is formed on the entire surface of the semiconductor substrate 11 including the control gate 12 by using the HDP method used as the interlayer insulating film 13.

도 1b에 도시한 바와 같이, 상기 층간 절연막(13)의 전면에 CMP 공정을 실시 하여 평탄화 작업을 실시한다.As shown in FIG. 1B, a planarization operation is performed by performing a CMP process on the entire surface of the interlayer insulating film 13.

이때, 상기 HDP(High Density Plasma) 방식에 의해 형성된 USG막은 딥 앤드 식각(deep and etch) 방식으로 도포되는 특성으로 인하여 하부의 패턴에 따라 산(mount) 프로파일(profile)을 이루며, 이러한 구조는 CMP진행시 하부의 패터닝된 컨트롤 게이트(12)가 손상(화살표 A)을 입어 제품 수율 저하를 초래한다.At this time, the USG film formed by the HDP method is formed by a deep and etch method to form a mount profile according to a lower pattern. In progress, the lower patterned control gate 12 is damaged (arrow A), resulting in lower product yield.

본 발명은 평탄화 공정시 하부에 형성된 패턴을 손상을 방지하여 제품의 수율을 향상시키도록 한 반도체 소자의 층간 절연막 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device to improve the yield of the product by preventing damage to the pattern formed at the bottom during the planarization process.

본 발명에 따른 층간 절연막 형성방법은 반도체 기판상에 일정한 간격을 갖는 다수의 패턴들을 형성하는 단계; 상기 패턴들을 포함한 반도체 기판의 전면에 층간 절연막을 형성하는 단계; 상기 층간 절연막의 전면에 DHF 케미컬을 이용한 표면 처리로 상기 층간 절연막의 표면을 라운드 형태로 형성하는 단계; 및 상기 라운드 형태로 형성된 층간 절연막을 선택적으로 연마하여 평탄화하는 단계가 포함되어 구성되는 것을 특징으로 한다.An interlayer insulating film forming method according to the present invention comprises the steps of forming a plurality of patterns having a predetermined interval on the semiconductor substrate; Forming an interlayer insulating film on an entire surface of the semiconductor substrate including the patterns; Forming a surface of the interlayer insulating film in a round shape by surface treatment using DHF chemical on the entire surface of the interlayer insulating film; And selectively grinding and planarizing the interlayer insulating film formed in the round shape.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 층간 절연막 형성방법을 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of forming an interlayer insulating film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 층간 절연막 형성방법을 나타낸 공정단면도이다. 2A to 2C are process cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이, 반도체 기판(101)상에 일정한 간격을 갖는 플래시 소자의 컨트롤 게이트(102)와 같은 패턴을 형성한다.As shown in FIG. 2A, a pattern similar to that of the control gate 102 of the flash element having a predetermined interval is formed on the semiconductor substrate 101. FIG.

여기서, 상기 컨트롤 게이트(102)를 패턴의 한 예로 들어 설명하고 있지만, 트랜지스터의 게이트 전극, 이미지 센서의 게이트 전극 그리고 각종 금속배선을 등도 패턴의 한 예를 들 수 있다.Here, although the control gate 102 is described as an example of a pattern, an example of an even pattern may be used for the gate electrode of a transistor, the gate electrode of an image sensor, and various metal wirings.

이어서, 상기 컨트롤 게이트(102)를 포함한 반도체 기판(101)의 전면에 층간 절연막(103)으로 사용되어지는 HDP 방식을 이용하여 USG막를 형성한다.Subsequently, a USG film is formed on the entire surface of the semiconductor substrate 101 including the control gate 102 by using the HDP method used as the interlayer insulating film 103.

이때, 상기 HDP(High Density Plasma) 방식에 의해 형성된 USG막은 딥 앤드 식각(deep and etch) 방식으로 도포되는 특성으로 인하여 하부의 패턴에 따라 산(mount) 프로파일(profile)을 이룬다.At this time, the USG film formed by the high density plasma (HDP) method forms a mount profile according to a lower pattern due to the property of being applied by a deep and etch method.

한편, 상기 층간 절연막(103)은 USG 이외에 실리콘 산화막, FSG(Silicon Oxy Fluoride ; SiOF), Low-k 절연막, BPSG(Boron Phosphorus Silicate Glass) 중에서 어느 하나를 사용할 수 있다.The interlayer insulating film 103 may be any one of silicon oxide film, silicon oxide fluoride (SFG), low-k insulating film, and boron phosphorus silicate glass (BPSG) in addition to USG.

도 2b에 도시한 바와 같이, 상기 층간 절연막(103)의 전면에 DHF 케미컬(chemical)을 이용하여 표면 처리를 실시하여 상기 층간 절연막(102) 표면의 산(Mount) 프로파일을 라운드(round) 형태로 변화시킨다.As shown in FIG. 2B, a surface treatment is performed on the entire surface of the interlayer insulating film 103 using DHF chemical to form a round profile of the mount profile of the surface of the interlayer insulating film 102. Change.

여기서, 상기 DHF 케미컬(chemical)을 이용하여 표면 처리는 30 ~ 60% HF 용액과 DI를 1:50 ~ 1:300으로 혼합하여 실시한다.Here, the surface treatment using the DHF chemical (chemical) is carried out by mixing 30 ~ 60% HF solution and DI 1: 1: 50 ~ 1: 300.

도 2c에 도시한 바와 같이, 상기 표면이 라운드된 층간 절연막(103)의 전면에 CMP 공정을 실시하여 평탄화 작업을 실시한다.As shown in FIG. 2C, a planarization operation is performed by performing a CMP process on the entire surface of the interlayer insulating film 103 having the rounded surface.

이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 층간 절연막 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming an interlayer insulating film of a semiconductor device according to the present invention has the following effects.

즉, 라운드로 처리된 층간 절연막을 평탄화함으로써 평탄화 공정시에 하부 패턴의 어텍(attack)을 방지하여 제품의 수율을 향상시킬 수 있다.That is, by flattening the interlayer insulating film treated by round, the attack of the lower pattern may be prevented in the planarization process, thereby improving the yield of the product.

Claims (4)

반도체 기판상에 일정한 간격을 갖는 다수의 패턴들을 형성하는 단계;Forming a plurality of patterns at regular intervals on the semiconductor substrate; 상기 패턴들을 포함한 반도체 기판의 전면에 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on an entire surface of the semiconductor substrate including the patterns; 상기 층간 절연막의 전면에 DHF 케미컬을 이용한 표면 처리로 상기 층간 절연막의 표면을 라운드 형태로 형성하는 단계; 및Forming a surface of the interlayer insulating film in a round shape by surface treatment using DHF chemical on the entire surface of the interlayer insulating film; And 상기 라운드 형태로 형성된 층간 절연막을 선택적으로 연마하여 평탄화하는 단계가 포함되어 구성되는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.Selectively grinding and planarizing the interlayer insulating film formed in the round shape. 제 1항에 있어서, The method of claim 1, 상기 층간 절연막은 HDP 방식을 이용하여 USG막을 도포하여 형성하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.The interlayer insulating film is formed by applying a USG film using an HDP method. 제 1항에 있어서, The method of claim 1, 상기 DHF 케미컬을 이용한 층간 절연막의 표면 처리는 30~60% HF 용액과 DI를 1:0 ~ 1:300으로 혼합하여 실시하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.The surface treatment of the interlayer insulating film using the DHF chemical is a method of forming an interlayer insulating film of a semiconductor device, characterized in that the mixture of 30 to 60% HF solution and DI 1: 1: 0 to 1: 300. 제 1항에 있어서,The method of claim 1, 상기 층간 절연막은 실리콘 산화막, FSG(Silicon Oxy Fluoride ; SiOF), Low-k 절연막, BPSG(Boron Phosphorus Silicate Glass) 중 어느 하나인 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.The interlayer insulating film is a silicon oxide film, silicon oxide fluoride (FSG), low-k insulating film, BPSG (Boron Phosphorus Silicate Glass) method of forming an interlayer insulating film of a semiconductor device, characterized in that.
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Publication number Priority date Publication date Assignee Title
KR19990061043A (en) * 1997-12-31 1999-07-26 김영환 Metal wiring formation method of semiconductor device

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Publication number Priority date Publication date Assignee Title
KR19990061043A (en) * 1997-12-31 1999-07-26 김영환 Metal wiring formation method of semiconductor device

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한국공개특허번호 10-1999-0061043

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