KR100256818B1 - Semiconductor element isolation layer manufacturing method - Google Patents

Semiconductor element isolation layer manufacturing method Download PDF

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KR100256818B1
KR100256818B1 KR1019970014437A KR19970014437A KR100256818B1 KR 100256818 B1 KR100256818 B1 KR 100256818B1 KR 1019970014437 A KR1019970014437 A KR 1019970014437A KR 19970014437 A KR19970014437 A KR 19970014437A KR 100256818 B1 KR100256818 B1 KR 100256818B1
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film
trench
insulating film
forming
semiconductor substrate
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KR19980077341A (en
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이승무
김시범
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma

Abstract

PURPOSE: A method for forming an isolation layer is to improve a planarizing feature in a PECVD(plasma enhanced chemical vapor deposition) in such a manner that an inner wall of a PECVD chamber is coated with an oxide layer or a nitride layer before implementing a plasma treatment, and then implementing the plasma treatment without an in-situ cleaning. CONSTITUTION: The first and second insulating layers are formed on a semiconductor substrate(11). A trench is formed by etching the first and second insulating layers and the semiconductor substrate in a predetermined depth using an isolation mask. A thermal oxide layer is formed on the surface of the trench, and then removed. On the surface of the trench is formed a thermal oxide layer. An insulating layer is deposited on an inner wall of a chamber in which the semiconductor substrate is loaded. The surface of the semiconductor substrate is treated with N2/NH3 plasma. The trench is buried with an O3-TEOS USG(tetraethyl ortho-silicate undoped silicate glass) layer(19).

Description

반도체소자의 소자분리막 형성방법Method of forming device isolation film of semiconductor device

본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 플라즈마 유도화학기상증착(Plasma Enhanced Chemical Vapor Deposition, 이하 PECVD라함) 장비를 이용하는 소자분리공정에 있어서, PECVD 챔버에 의한 웨이퍼의 오염을 방지하여 반도체소자의 수율 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation film of a semiconductor device, and in particular, in a device separation process using plasma enhanced chemical vapor deposition (PECVD) equipment, to prevent contamination of a wafer by a PECVD chamber. The present invention relates to a technique for improving yield and reliability of semiconductor devices.

일반적인 반도체소자의 소자분리막 형성방법을 설명하면 다음과 같다.A method of forming a device isolation film of a general semiconductor device is as follows.

먼저, 반도체기판 상부에 열산화공정으로 제1절연막인 패드산화막을 100∼200Å의 두께로 형성하고, 전체표면 상부에 화학기상증착방법(Chemical Vapor Deposition, 이하 CVD라 함)으로 제2절연막인 질화막을 1500∼2500Å의 두께로 증착한다.First, a pad oxide film, which is a first insulating film, is formed on the semiconductor substrate by a thermal oxidation process to a thickness of 100 to 200Å, and a nitride film, which is a second insulating film, is deposited on the entire surface by chemical vapor deposition (CVD). Is deposited to a thickness of 1500-2500 mm 3.

그 다음에, 소자분리마스크를 이용한 식각공정으로 상기 제2절연막과 제1절연막 그리고 일정두께의 반도체기판을 식각하여 트렌치를 형성한다.Next, a trench is formed by etching the second insulating film, the first insulating film, and a semiconductor substrate having a predetermined thickness by an etching process using an element isolation mask.

그리고, 상기 트렌치의 표면에 제3절연막을 형성하고, 전체표면 상부를 질소와 암모니아 가스 분위기에서 플라즈마처리하는 공정을 실시한 다음, 전체표면 상부에 O3-TEOS USG막을 형성하여 평탄화를 시킨다.A third insulating film is formed on the surface of the trench, and a plasma treatment is performed on the entire surface of the trench in nitrogen and ammonia gas. Then, an O 3 -TEOS USG film is formed on the entire surface to be planarized.

이때, 상기 트렌치 표면은 상기 플라즈마처리공정시 반응챔버의 내벽에 포함된 금속물질로 인하여 오염될 수 있다.In this case, the trench surface may be contaminated due to the metal material included in the inner wall of the reaction chamber during the plasma treatment process.

상기한 바와 같이, 종래기술에 따른 반도체소자의 소자분리막 형성방법은, 플라즈마처리공정시 챔버에 의한 반도체기판 표면에 금속오염이유발되어 소자의 특성을 열화시키고 그로인한 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, in the method of forming a device isolation film of a semiconductor device according to the prior art, metal contamination is induced on the surface of a semiconductor substrate by a chamber during a plasma processing process, thereby deteriorating device characteristics and deteriorating characteristics and reliability of the device. There is a problem.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, PECVD 챔버에서 플라즈마처리를 실시하기 전에 챔버 내벽을 산화막이나 질화막으로 코팅을 실시하고, 인-시튜 클리닝없이 플라즈마처리하여 챔버 내벽으로 인한 금속오염의 발생을 최소화하며, 상기 플라즈마처리공정을 실시함으로써 O3-TEOS USG의 증착속도를 조절하여 자체 평탄화 특성을 향상시키고 후속공정을 용이하게 실시할 수 있는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, before the plasma treatment in the PECVD chamber, the chamber inner wall is coated with an oxide film or a nitride film, and plasma treatment is performed without in-situ cleaning to remove metal contamination caused by the inner wall of the chamber. The present invention provides a method of forming a device isolation film of a semiconductor device which can minimize the occurrence and improve the self-planarization characteristics by controlling the deposition rate of O 3 -TEOS USG by performing the plasma treatment process and easily perform the subsequent process. There is this.

제1a도 내지 제1e 도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체 기판 13 : 제1절연막11: semiconductor substrate 13: first insulating film

15 : 제2절연막 16 : 트렌치15: second insulating film 16: trench

17 : 제4절연막 19 : O3-TEOS USG막17: fourth insulating film 19: O 3 -TEOS USG film

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은,Device isolation film forming method of a semiconductor device according to the present invention for achieving the above object,

반도체기판 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the semiconductor substrate;

상기 제1절연막 상부에 제2절연막을 형성하는 공정과,Forming a second insulating film on the first insulating film;

상기 제2절연막과 제1절연막 그리고 일정두께의 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the second insulating film, the first insulating film, and a semiconductor substrate having a predetermined thickness;

상기 트렌치 표면에 제3절연막을 형성하는 공정과,Forming a third insulating film on the trench surface;

상기 제3절연막을 제거하는 공정과,Removing the third insulating film;

상기 트렌치 표면에 제4절연막을 형성하는 공정과,Forming a fourth insulating film on the trench surface;

상기 반도체기판이 내재된 챔버 내벽에 제5절연막을 형성하는 공정과,Forming a fifth insulating film on an inner wall of the chamber in which the semiconductor substrate is embedded;

상기 제4절연막을 N2/NH3플라즈마처리하는 공정과,Performing a N 2 / NH 3 plasma treatment on the fourth insulating film;

상기 트렌치를 O3-TEOS USG로 매립하는 공정을 포함하는 것을 특징으로 한다.And filling the trench with O 3 -TEOS USG.

한편, 이상의 목적을 달성하기위한 본 발명의 원리는, 얕은(shallow)트렌치소자분리공정을 실시하는데 있어서, 플라즈마 처리공정을 실시하기 전에 반응챔버인 PECVD 챔버의 내벽을 산화막이나 질화막으로 프리-코팅하여 금속오염의 가능성을 최소화하고, 플라즈마 처리공정을 실시한후 트렌치에 O3-TEOS USG를 증착함으로써 산화막 상부는 O3-TEOS USG를 빠르게 증착시키고 질화막 상부는 O3-TEO USG을 증착이 느리게 하여 자체 평탄화 특성을 향상시키며, 후속 공정인 CMP 공정의 공정시간을 감소시켜 공정 균일도 및 생산성을 향상시키는 것이다.On the other hand, the principle of the present invention for achieving the above object is, in performing a shallow trench isolation process, by pre-coating the inner wall of the PECVD chamber which is a reaction chamber with an oxide film or a nitride film before performing the plasma treatment process After minimizing the possibility of metal contamination and performing the plasma treatment process, O 3 -TEOS USG is deposited on the trench to rapidly deposit O 3 -TEOS USG on the oxide layer and O3-TEO USG on the nitride layer to slow down the deposition. It improves the characteristics and improves the process uniformity and productivity by reducing the process time of the subsequent CMP process.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a도 내지 제1e도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 형성공정을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a process of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

제1a도를 참조하면, 반도체기판(11) 상부에 제1절연막(13)인 패드산화막을 형성한다. 이때, 상기 패드산화막(13)은 열산화공정으로 형성하되, 50 내지 200Å 정도의 두께로 형성한다.Referring to FIG. 1A, a pad oxide film, which is the first insulating layer 13, is formed on the semiconductor substrate 11. At this time, the pad oxide film 13 is formed by a thermal oxidation process, but is formed to a thickness of about 50 to 200Å.

그리고, 상기 제1절연막(13) 상부에 제2절연막(15)인 질화막을 일정두께로 형성한다. 이때, 상기 질화막(15)은 화학기상증착방법으로 1500 내지 2500Å 정도의 두께로 형성한다.A nitride film, which is the second insulating film 15, is formed on the first insulating film 13 to have a predetermined thickness. In this case, the nitride film 15 is formed to a thickness of about 1500 to 2500Å by chemical vapor deposition.

그 다음에, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(11)의 셀부와 주변회로부에 트렌치(16)를 형성한다.Next, a trench 16 is formed in the cell portion and the peripheral circuit portion of the semiconductor substrate 11 by an etching process using an element isolation mask (not shown).

제1b도를 참조하면, 상기 트렌치(16)표면에 제3절연막인 제1열산화막(도시안됨)을 형성하는 제1차 산화공정을 실시한다. 이때, 상기 제1열산화막은 100 내지 200Å정도의 두께로 형성한다.Referring to FIG. 1B, a first oxidation process is performed to form a first thermal oxide film (not shown), which is a third insulating film, on the surface of the trench 16. In this case, the first thermal oxide film is formed to a thickness of about 100 ~ 200Å.

그리고, 상기 제1열산화막을 습식식각으로 제거한다.Then, the first thermal oxide film is removed by wet etching.

이때, 제1차 산화공정과 제1열산화막의 제거공정은 상기 트렌치(16)형성공정시 발생된 트렌치(16) 표면의 결함을 제거한다.In this case, the first oxidation process and the first thermal oxide film removal process remove defects on the surface of the trench 16 generated during the trench 16 formation process.

제1c도를 참조하면, 제2차 산화공정으로 트렌치(16) 표면에 제4절연막(17)인 제2열산화막을 100내지 200Å 정도의 두께로 형성한다.Referring to FIG. 1C, a second thermal oxide film, which is the fourth insulating film 17, is formed on the surface of the trench 16 to a thickness of about 100 to about 200 kPa by the second oxidation process.

제1d도를 참조하면, 제2차 열산화공정 후 챔버의 내벽에 절연막(도시되지 않음)인 산화막, 질화막 또는 산질화막 재질로 5 내지 10㎛의 두께로 프리-코팅한다.Referring to FIG. 1D, after the second thermal oxidation process, the inner wall of the chamber is pre-coated to an thickness of 5 to 10 μm of an oxide film, a nitride film, or an oxynitride film as an insulating film (not shown).

이때, 상기 프리-코팅공정은, PECVD에서 한종류의 증착재료가 진행되고 후속 공정으로 다른 증착재료가 진행될 때 인-시튜 클리닝공정없이 진행할 수 있다.In this case, the pre-coating process may be performed without an in-situ cleaning process when one kind of deposition material proceeds in PECVD and another deposition material proceeds in a subsequent process.

그 다음에, 절연막이 내벽에 프리코팅된 챔버(도시안됨)에서 웨이퍼(도시안됨)의 표면을 플라즈마 처리함으로써 O3-TEOS USG의 하지의존성을 감소시킨다.Subsequently, the underlying dependence of the O 3 -TEOS USG is reduced by plasma treating the surface of the wafer (not shown) in a chamber (not shown) with an insulating film precoated on the inner wall.

이때, 상기 플라즈마 처리공정은 O3-TEOS USG를 증착할 때의 조건 보다 약한 조건인 N2/NH3= 1∼3/2∼10 LSM의 유량, HF/LF=0.1∼1.0/0.1∼0.3kW의 전력, 300∼400℃의 온도 및 1.0∼2.0Torr의 압력을 갖는 조건으로 10∼50초의 시간동안 실시한다.At this time, the plasma treatment step is N 2 / NH 3 = 1 to 3/2 to 10 LSM, HF / LF = 0.1 to 1.0 / 0.1 to 0.3 which is weaker than the conditions when depositing O 3 -TEOS USG It is carried out for a time of 10 to 50 seconds under conditions having a power of kW, a temperature of 300 to 400 DEG C and a pressure of 1.0 to 2.0 Torr.

여기서, 본 발명자의 실험 결과에 따르면 상기 프리-코팅을 실시하고 플라즈마 처리공정을 실시할 때 트렌치(16) 표면에 존재하는 금속오염물질의 양은, 프리-코팅을 하지 않은 경우의 1/10정도로 감소된다.Here, according to the experimental results of the present inventors, the amount of metal contaminants present on the surface of the trench 16 during the pre-coating and the plasma treatment is reduced to about 1/10 of the case without the pre-coating. do.

그리고, 상기 플라즈마 처리공정에 의해 상기 트렌치(16)를 메우는 O3-TEOS USG막을 증착할 때 열산화막에서는 증착이 빠르고 질화막위에서는 증착이 느리게 되어 자체 평탄화 특성을 우수하게 함으로써 후속 CMP 공정의 공정시간을 최소화하여 평탄화된 트렌치 소자분리공정을 용이하게 한다.In addition, when the O 3 -TEOS USG film filling the trench 16 is deposited by the plasma treatment process, the deposition time is faster in the thermal oxide film and the deposition time is slower on the nitride film, thereby improving the self-planarization property, thereby improving the process time of the subsequent CMP process. Minimize the number to facilitate the planarized trench isolation process.

제1e도를 참조하면, 상기 플라즈마 처리공정 후 O3-TEOS USG(19)를 전면에 증착하여 상기 트렌치(16)를 O3TEOS USG(19)로 매립한다.Referring to FIG. 1E, after the plasma treatment process, the O 3 -TEOS USG 19 is deposited on the entire surface to fill the trench 16 with the O 3 TEOS USG 19.

이때, 상기 O3TEOS USG(19)의 증착 공정은, 80∼120SLM정도의 질소가스의 유량, 100∼140g/㎥ 정도의 오존농도에서 5000∼7000Å 정도의 두께로 형성한다.At this time, the deposition process of the O 3 TEOS USG 19 is formed in a thickness of about 5000 to 7000 Pa at a flow rate of nitrogen gas of about 80 to 120 SLM and an ozone concentration of about 100 to 140 g / m 3.

그후, 도시되지는 않았으나 후속 열처리 및 CMP공정을 실시하여 얕은 트렌치 소자분리(shallow trench isolation)공정을 완료한다.Subsequently, although not shown, subsequent heat treatment and a CMP process are performed to complete the shallow trench isolation process.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 챔버내벽을 산화막이나 질화막으로 프리-코팅함으로써 플라즈마처리공정으로 인한 금속오염을 최소화하고, O3TEOS USG의 자체 평탄화 특성을 향상시켜 CMP공정의 공정시간을 감소시키며, 후속공정을 용이하게 하여 반도체소자의 특성, 수율 및 생산성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method of forming a device isolation film of a semiconductor device according to the present invention minimizes metal contamination caused by a plasma treatment process by pre-coating a chamber inner wall with an oxide film or a nitride film, and improves the self-planarization characteristics of O 3 TEOS USG. By reducing the process time of the CMP process, and facilitates the subsequent process to improve the characteristics, yield, and productivity of the semiconductor device, and thereby the high integration of the semiconductor device is possible.

Claims (8)

반도체기판 상부에 제1절연막과 제2절연막을 형성하는 공정과, 상기 제2절연막과 제1절연막 그리고 일정두께의 반도체기판을 소자분리 마스크를 이용하여 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 표면에 열산화막을 형성한 후 제거하는 공정과, 상기 트렌치 표면에 열산화막을 형성하는 공정과, 상기 반도체기판이 탑재된 챔버의 내벽에 절연막을 형성하는 공정과, 상기 반도체기판의 표면을 N2/NH3플라즈마로 처리하는 공정과, 상기 트렌치를 O3TEOS USG로 매립하는 공정을 포함하는 반도체소자의 소자분리막 형성방법.Forming a first insulating film and a second insulating film on the semiconductor substrate; forming a trench by etching the second insulating film, the first insulating film, and a semiconductor substrate having a predetermined thickness using an isolation mask; and forming a trench surface. in the step of removing after the formation of the thermal oxide film, a step of forming a thermal oxide film on the trench surface, and forming an insulating film on the inner wall of the semiconductor substrate with the chamber, the surface of the semiconductor substrate N 2 / A method of forming an isolation film in a semiconductor device, the method comprising: treating with NH 3 plasma; and filling the trench with O 3 TEOS USG. 청구항 1에 있어서, 상기 제1절연막은 50∼200Å두께의 패드산화막인 것을 특징으로하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the first insulating film is a pad oxide film having a thickness of 50 to 200 kHz. 청구항 1에 있어서, 상기 제2절연막은 1500∼2500Å두께의 질화막인 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the second insulating film is a nitride film having a thickness of 1500 to 2500 Å. 청구항 1에 있어서, 상기 열산화막들을 100∼200Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the thermal oxide layers are formed to a thickness of about 100 to about 200 microns. 청구항 1에 있어서, 상기 챔버 내벽에 형성되는 절연막은 산화막, 질화막 또는 산질화막 중 하나로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the insulating film formed on the inner wall of the chamber is formed of one of an oxide film, a nitride film, and an oxynitride film. 청구항 1 또는 청구항 5에 있어서, 상기 챔버 내벽에 형성되는 절연막은 5∼10㎛두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The method of claim 1 or 5, wherein the insulating film formed on the inner wall of the chamber is formed to a thickness of 5 ~ 10㎛. 청구항 1에 있어서, 상기 플라즈마 처리공정은 1∼2/2∼10 SLM의 N2/NH3유량, 0.1∼1.0/0.1∼0.3kW의 HF/LF 전력, 300∼400℃온도, 1.0∼2.0Torr의 압력에서 10∼50초의 시간동안 실시하는 것을 특징으로하는 반도체소자의 소자분리막 형성방법.The method of claim 1, wherein the plasma treatment process is N 2 / NH 3 flow rate of 1 to 2/2 to 10 SLM, HF / LF power of 0.1 to 1.0 / 0.1 to 0.3 kW, 300 to 400 ℃ temperature, 1.0 to 2.0 Torr A device isolation film forming method for a semiconductor device, characterized in that carried out for a time of 10 to 50 seconds at a pressure of. 청구항 1에 있어서, 상기 O3-TEOS USG는 80∼120 SLM의 질소유량, 100∼140g/㎥의 오존농도, 350∼450℃의 온도에서 5000∼7000Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 형성방법.The semiconductor device according to claim 1, wherein the O 3 -TEOS USG is formed at a thickness of 5000 to 7000 Pa at a nitrogen flow rate of 80 to 120 SLM, an ozone concentration of 100 to 140 g / m 3, and a temperature of 350 to 450 ° C. 3. Device isolation film formation method of.
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