KR100787713B1 - Method of fabricating semiconductor devices - Google Patents

Method of fabricating semiconductor devices Download PDF

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KR100787713B1
KR100787713B1 KR1020060134036A KR20060134036A KR100787713B1 KR 100787713 B1 KR100787713 B1 KR 100787713B1 KR 1020060134036 A KR1020060134036 A KR 1020060134036A KR 20060134036 A KR20060134036 A KR 20060134036A KR 100787713 B1 KR100787713 B1 KR 100787713B1
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film
layer
teos
usg
fsg
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KR1020060134036A
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Korean (ko)
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조보연
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of fabricating a semiconductor device is provided to prevent a layer separation effect by adding a TEOS(Tetra Ethyl Ortho Silicate) layer between an FSG layer and a USG layer. An FSG layer(133) is laminated on an upper surface of a lower substrate including a wiring pattern. A TEOS layer(137) is laminated on the substrate including the FSG layer. A USG layer is formed on the substrate including the TEOS layer. An upper surface of the substrate including the USG layer is planarized by performing a chemical mechanical polishing process. A sacrificial layer is laminated on the USG layer in order to perform a planarization process. The sacrificial layer is formed with another TEOS layer to be removed by an etch-back process and is silicon oxidation film.

Description

반도체 장치 제조 방법{Method of fabricating semiconductor devices} Method of fabricating semiconductor devices

도1은 종래의 층간 절연막 형성의 일 단계에서의 문제점을 나타내는 공정 단면도이다. 1 is a cross sectional view showing a problem in one step of forming a conventional interlayer insulating film.

도2 내지 도4는 본 발명의 일 실시예의 중요 구성 단계에서의 반도체 장치 부분을 나타내는 공정 단면도들이다.2 to 4 are process cross sectional views showing a portion of a semiconductor device in an important construction step of an embodiment of the present invention.

본 발명은 반도체 장치 제조방법에 관한 것으로, 보다 상세하게는 반도체 장치에서 층을 달리하는 소자와 배선, 배선 및 배선 사이에 형성되는 층간 절연막을 형성하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an interlayer insulating film formed between an element having a different layer and a wiring, wiring, and wiring in a semiconductor device.

반도체 장치는 반도체 기판에 도체 및 부도체, 반도체 막을 형성하고 가공하여 전자, 전기 소자 및 배선을 형성하여 이루어지는 회로 장치의 일종이다. 반도체 장치의 고집적화가 진행되면서 반도체 장치는 매우 복잡하고 정밀하게 이루어지고 있으며, 그 형성 공정은 극도로 정밀하게 조건이 제어될 필요가 있다. A semiconductor device is a type of circuit device formed by forming a conductor, a non-conductor, and a semiconductor film on a semiconductor substrate to form an electronic, electrical element, and wiring. As the integration of semiconductor devices has progressed, semiconductor devices have become very complex and precise, and the formation process needs to be controlled with extreme precision.

반도체 장치의 고집적화를 위해 소자 및 배선의 크기가 점차 줄어들고, 한정 된 면적에 많은 소자를 형성하기 위해 다층화가 이루어진다. 소자와 배선을 연결하고, 상층 배선과 하층 배선을 연결하기 위해 층간 절연막에 홀을 형성하고 홀에 도체를 채워 콘택을 형성하게 된다.For high integration of semiconductor devices, the size of elements and wirings is gradually reduced, and multilayering is carried out to form many elements in a limited area. In order to connect the device and the wiring, and to connect the upper wiring and the lower wiring, a hole is formed in the interlayer insulating film and a conductor is filled in the hole to form a contact.

이때, 반도체 장치에서 층간 절연막은 상층 배선을 형성하면서 하층의 배선과 절연을 확보하기 위해 기본적으로 필요하다. 따라서, 층간 절연막은 내전압 강도가 크고, 절연성이 양호한 것이 요구된다. 그러나, 소자 고집적화에 따라 같은 층 내의 배선 사이의 간격이 짧아지면 반도체 장치 내에 기생 캐퍼시터 용량이 늘어나고, 저항 캐퍼시터 지연(RC DELAY) 등의 문제가 점차 중요하게 된다. 즉, 절연 특성 외에 그 형성되는 위치 및 주변 상황에 따라 여러 가지 다른 특성이 층간 절연막에 대해 요구될 수 있다. At this time, the interlayer insulating film is basically required in the semiconductor device to secure the wiring and the lower layer while forming the upper wiring. Therefore, the interlayer insulation film is required to have high withstand voltage strength and good insulation. However, when the spacing between wirings in the same layer is shortened due to high device integration, parasitic capacitor capacity increases in the semiconductor device, and problems such as resistance capacitor delay (RC DELAY) become increasingly important. That is, in addition to the insulating properties, various other properties may be required for the interlayer insulating film depending on the location and the surrounding situation.

또한, 하나의 층간 절연막으로 원하는 조건을 다 만족시키지 못함에 따라 여러 층으로 구분하여 층마다 적절한 층간 절연막 재질을 배분하게 된다.In addition, as one interlayer insulating film does not satisfy all of the desired conditions, an appropriate interlayer insulating film material is allocated to each layer by dividing into several layers.

도1은 종래의 층간 절연막 형성의 일 단계에서의 문제점을 나타내는 공정 단면도의 부분이다. 1 is a portion of a process cross-sectional view showing a problem in one step of forming a conventional interlayer insulating film.

도1을 참조하면, 먼저, 하부 기판(10)에 배선 패턴(20)이 형성된다. 배선 패턴(20) 위로 실리콘 산화막의 일종인 FSG(Fluorine doped Silicate Glass)막(33)과 USG(Undoped Silicate Glass)막(35)이 차례로 적층되어 층간 절연막(30)을 형성하게 된다. 그리고 배선 패턴(20)에 따라 고르지 못한 기판 수준에 의해 층간 절연막(30)의 상면도 단차지게 형성된다. Referring to FIG. 1, first, a wiring pattern 20 is formed on a lower substrate 10. The FSG (Fluorine doped Silicate Glass) 33 and the USG (Undoped Silicate Glass) 35 are sequentially stacked on the wiring pattern 20 to form the interlayer insulating film 30. In addition, the upper surface of the interlayer insulating layer 30 is also formed at an uneven substrate level according to the wiring pattern 20.

단차가 커질 경우, 후속 공정에서 식각용 포토레지스트 공정의 노광 촛점을 맞추기 힘들고, 구조가 불안정하게 되는 등의 문제가 있다. 이런 문제를 방지하기 위해 층간 절연막을 충분히 적층한 뒤 단차진 곳의 두꺼운 부분을 더 많이 제거하는 평탄화 작업을 할 수 있다. 화학적 기계적 연마는 기판 평탄화 작업에 많이 사용되는 방법이다. When the step is increased, it is difficult to focus the exposure of the photoresist process for etching in a subsequent process, and the structure becomes unstable. In order to prevent this problem, the interlayer insulating film may be sufficiently stacked and then planarized to remove more thick portions of the stepped portions. Chemical mechanical polishing is a popular method for substrate planarization operations.

그런데 일단, FSG막과 USG막이 차례로 적층된 상태에서 이들막의 상호 접착성이 약하고, 기판에 대한 열처리가 이루어지면 이들 재질의 차이로 인하여 계면에 열 스트레스가 발생하여 층분리가 되기 쉽다. 이런 상태에서 층간 절연막 편탄화를 위해 화학적 기계적 연마(CMP)를 실시하면 상부의 USG막이 떨어져 나와 도1의 손상부(40)을 형성하고, 파티클로 작용하면서 연마 과정에서 층간 절연막을 손상시킬 수 있고, 막이 떨어져 나온 부분에서는 층간절연막으로서의 기능을 가지지 못할 위험이 있다. However, once the FSG film and the USG film are laminated in order, the mutual adhesion of these films is weak, and when the heat treatment is performed on the substrate, thermal stress occurs at the interface due to the difference of these materials, and thus the layers are easily separated. In this state, when chemical mechanical polishing (CMP) is performed for interlayer insulation film carbonization, the upper USG film may come off to form the damage portion 40 of FIG. 1, and may act as a particle to damage the interlayer insulation film during polishing. However, there is a risk that the part where the film is separated does not have a function as an interlayer insulating film.

본 발명은 공정중에 표면 평탄화를 위한 CMP 작업시 층간 절연막의 층분리 및 탈락의 문제점을 경감, 해결하기 위한 것으로, 평탄하고 균일한 층구조의 층간 절연막을 가지는 반도체 장치 제조 방법을 제공하는 것을 목적으로 한다.The present invention is to alleviate and solve the problem of layer separation and dropping of the interlayer insulating film during CMP operation for surface planarization during the process, and to provide a method for manufacturing a semiconductor device having a flat and uniform interlayer insulating film. do.

본 발명은 2이상의 층이 겹쳐 층간 절연막을 형성할 때 두 층 사이의 계면에서 층분리 현상을 줄일 수 있는 반도체 장치 제조 방법을 제공하는 것을 목적으로 한다. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the delamination phenomenon at an interface between two layers when two or more layers overlap to form an interlayer insulating film.

상기 목적을 달성하기 위한 본 발명은, 배선 패턴이 형성된 하부 기판 위로 FSG막을 적층하는 단계, FSG막이 형성된 기판에 테오스(TEOS:Tetraethylorthosilicate)막을 적층하는 단계, TEOS막이 형성된 기판에 USG막을 형성하는 단계, 상기 USG막이 형성된 기판의 상면을 화학적 기계적 연마를 통해 평탄화하는 단계를 구비하여 이루어지는 것을 특징으로 한다. The present invention for achieving the above object, the step of stacking the FSG film on the lower substrate on which the wiring pattern is formed, the step of laminating a TEOS (TEe: Tetraethylorthosilicate) film on the substrate formed with the FSG film, the step of forming a USG film on the substrate formed TEOS film And planarizing the upper surface of the substrate on which the USG film is formed by chemical mechanical polishing.

본 발명에서 USG막 위로 별도의 TEOS막을 형성하는 단계가 더 구비될 수 있으며, 이 경우, 이 TEOS막을 에칭 공정을 통해 제거하는 단계가 더 구비될 수 있다. In the present invention, a step of forming a separate TEOS film over the USG film may be further provided. In this case, the step of removing the TEOS film through an etching process may be further provided.

본 발명에서 FSG막과 USG막 사이에 형성되는 테오스막은 두께 1000 옹스트롬 정도로 적층될 수 있다.In the present invention, the TOS film formed between the FSG film and the USG film may be laminated to about 1000 angstroms in thickness.

이하 도면을 참조하면서 실시예를 통해 본 발명을 보다 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

도2는 본 발명의 일 실시예에서의 각 단계 가운데 먼저 하부 기판(110)에 배선 패턴(120)이 형성된 상태에서 층간 절연막(130)으로서 FSG막(133), TEOS막(137), USG막(135)을 차례로 적층한 상태를 나타낸다. 배선 패턴(120)은 도핑된 폴리실리콘층 등으로 형성할 수도 있으나, 통상 알미늄층이나 구리층으로 이루어진다.FIG. 2 shows the FSG film 133, the TEOS film 137, and the USG film as the interlayer insulating film 130 in the state in which the wiring pattern 120 is formed on the lower substrate 110 among the steps of the exemplary embodiment of the present invention. The state which laminated | stacked 135 in order is shown. The wiring pattern 120 may be formed of a doped polysilicon layer or the like, but is usually made of an aluminum layer or a copper layer.

하부 배선 패턴(120)이 서로 나란히 형성된 공정 기판 위로 층간 절연막을 이루는 하층인 FSG막(133)이 적층된다. FSG막(133) 적층 전에 다음단계에서 층간 절연막에 콘택홀을 형성하는 단계에서 사용하기 위해 스토퍼층(미도시)으로 실리콘 질화막 적층이 이루어질 수 있다. 이 경우, 스토퍼막 위로 실리콘 산화막 가운데 3.6 내지 3.8 정도의 저유전율을 가지는 막으로 FSG막이 형성된다. FSG막(133)은 화학 기상증착(CVD0용 공정 챔버에 산소를 풍부하게 공급하면서 사일렌(SiH4) 가스 등 실리콘 함유 가스와 불소 함유 가스를 공급하여 형성할 수 있다. FSG막은 CVD 산화막 가운데 비유전율이 비교적 낮아 기생 캐퍼시터를 줄이기 위해 많이 사용된다.The FSG film 133, which is an underlayer that forms an interlayer insulating film, is stacked on the process substrate on which the lower wiring patterns 120 are formed side by side. The silicon nitride film stack may be formed as a stopper layer (not shown) for use in forming a contact hole in the interlayer insulating film in a next step before stacking the FSG film 133. In this case, the FSG film is formed of a film having a low dielectric constant of about 3.6 to 3.8 in the silicon oxide film over the stopper film. The FSG film 133 can be formed by supplying a chemical vapor deposition (abundant oxygen to the CVD0 process chamber while supplying a silicon-containing gas such as a silica (SiH 4 ) gas and a fluorine-containing gas. The FSG film is analogous to the CVD oxide film). The relatively low electric power is used to reduce parasitic capacitors.

다음으로 TEOS막(137)은 테트라에칠오르소실리케이트 가스를 실리콘 소오스로 공급하여 형성할 수 있다. 산소 분위기를 만들기 위해 오존이 풍부한 환경이 이루어질 수 있다. TEOS막(137)은 하지막인 FSG막(133)과의 접착성이 좋고 고온을 거쳐도 열충격(Thermal stress)를 적게 받는 특성이 있어서 FSG막(133)과의 층분리 현상을 방지할 수 있다. TEOS막(137)은 층간 절연막을 이루는 다른 막질 들 사이에 접착층의 일종으로 역할을 할 수 있으며 이런 역할을 하는 데 두껍게 형성될 필요는 없으므로 전체 층간 절연막 10000 옹스트롬 정도에서 TEOS막 1000 옹스트롬 정도로 적층할 수 있다.Next, the TEOS film 137 may be formed by supplying tetraethylorthosilicate gas to the silicon source. Ozone-rich environments can be created to create an oxygen atmosphere. The TEOS film 137 has good adhesiveness with the FSG film 133 which is the underlying film, and has a property of being less thermally stressed even at a high temperature, thereby preventing layer separation from the FSG film 133. . The TEOS film 137 may serve as a kind of adhesive layer between the other film qualities forming the interlayer insulating film, and may not be formed to be thick in such a role, so that the TEOS film 137 may be stacked at about 10 000 angstroms in the total interlayer insulating film. have.

이어서 형성되는 USG막(135)은 산소 함유 가스를 공급하여 산소 분위기를 형성하면서 P형이나 N형 불순물 없이 실리콘 소오스 가스로 사일렌 가스를 공급하는 방법으로 형성될 수 있다.Subsequently, the USG film 135 may be formed by supplying an oxygen-containing gas to form an oxygen atmosphere, and supplying a silylene gas to a silicon source gas without P-type or N-type impurities.

TEOS막(137)은 USG막(135)과의 접착성도 양호하므로 이들 사이의 계면에서의 층분리 현상도 일어나지 않게 된다. Since the TEOS film 137 also has good adhesion with the USG film 135, no layer separation phenomenon occurs at the interface therebetween.

도2를 참조하면 추가적으로 기판 전면에 다시 TEOS막(139)이 형성될 수 있다. 이때의 TEOS막(139)은 기판 상면의 스탭 커버리지를 위해 추가로 적층될 수 있다. 이때에는 TEOS막 외에 스탭 커버리지 능력이 뛰어난 USG막보다 뛰어난 다른 막질이 사용될 수 있다. Referring to FIG. 2, an additional TEOS layer 139 may be formed on the entire surface of the substrate. In this case, the TEOS layer 139 may be further stacked for the step coverage of the upper surface of the substrate. In this case, in addition to the TEOS film, another film quality superior to the USG film having excellent staff coverage ability may be used.

그리고, 기판 전면에 대한 평탄화를 실시한다. 표면이 TEOS막(139)인 경우 CMP작업에 적합하지 않으므로 전면 에치백에 의한 평탄화를 실시한다. 이때 USG막(135) 상층의 TEOS막(139)은 평탄화를 위한 희생막의 역할을 하면서 전체적으로 기판을 평탄화시키면서 제거될 수 있다. Then, the entire surface of the substrate is planarized. If the surface is the TEOS film 139, it is not suitable for CMP work and planarization is performed by front etch back. In this case, the TEOS film 139 on the upper layer of the USG film 135 may be removed while planarizing the substrate as a sacrificial film for planarization.

도3을 참조하면, 도2의 단계에 이어서 드러난 USG막(135)의 상면을 CMP를 통해 추가로 평탄화 작업을 한다. 따라서 원래의 두께보다 대략 50% 배선 패턴과 같이 도드러진 부분에 해당하는 부분은 90% 정도까지 제거된 상태의 잔류 USG막(135')이 남게 된다. Referring to FIG. 3, the top surface of the USG film 135, which is exposed after the step of FIG. 2, is further planarized through CMP. As a result, the remaining USG film 135 ′ in which the portion corresponding to the doped portion, such as the wiring pattern is approximately 50% of the original thickness, is removed by 90%.

이때의 전체적인 층간 절연막(130")은 처음의 층간 절연막(130)에 비해 상당히 평탄화된 형태를 나타낸다.In this case, the overall interlayer insulating film 130 ″ is considerably flattened compared to the first interlayer insulating film 130.

본 발명에 따르면 층간 절연막을 이루는 FSG막과 USG막 사이에 접착층의 역할을 할 수 있는 TEOS막을 추가로 적층함으로써 종래와 같은 층간 절연막 내의 층분리 현상을 방지하고, 이로 인한 후속 CMP공정에서의 층간 절연막 상층 뜯겨나감 을 방지할 수 있다.According to the present invention, by further stacking a TEOS film, which can serve as an adhesive layer, between the FSG film and the USG film forming the interlayer insulating film, it is possible to prevent the conventional layer separation phenomenon in the conventional interlayer insulating film, thereby resulting in the interlayer insulating film in the subsequent CMP process. The upper layer can be prevented from being torn off.

그리고, 이런 뜯겨나감 현상에 의한 공정 불량이나 완성된 반도체 장치의 불량을 방지할 수 있다.In addition, it is possible to prevent a process defect or a defect of the completed semiconductor device caused by such a tearing-off phenomenon.

Claims (5)

배선 패턴이 형성된 하부 기판 위로 FSG막을 적층하는 단계, Stacking the FSG film on the lower substrate having the wiring pattern formed thereon; 상기 FSG막이 형성된 기판에 테오스(TEOS:Tetraethylorthosilicate)막을 적층하는 단계, Stacking a teos (TEOS: Tetraethylorthosilicate) film on the substrate on which the FSG film is formed; 상기 TEOS막이 형성된 기판에 USG막을 형성하는 단계, Forming a USG film on the substrate on which the TEOS film is formed; 상기 USG막이 형성된 기판의 상면을 화학적 기계적 연마를 통해 평탄화하는 단계를 구비하여 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법. And planarizing the upper surface of the substrate on which the USG film is formed by chemical mechanical polishing. 제 1 항에 있어서,The method of claim 1, 상기 USG막 위로 평탄화를 위한 희생막을 더 적층하고 평탄화하는 단계가 구비되는 것을 특징으로 하는 반도체 장치 제조 방법.And further stacking and planarizing a sacrificial film for planarization on the USG film. 제 2 항에 있어서,The method of claim 2, 상기 희생막은 상기 TEOS막과 별도의 다른 TEOS막으로 이루어지며, The sacrificial film is made of another TEOS film separate from the TEOS film, 상기 다른 TEOS막은 기판에 대한 전면 에치백 공정을 통해 제거되는 단계가 구비되는 것을 특징으로 하는 반도체 장치 제조 방법.And the other TEOS film is removed through a front etch back process on a substrate. 제 2 항에 있어서,The method of claim 2, 상기 희생막은 TEOS막보다 스탭 커버리지 특성이 더 우수한 실리콘 산화막으 로 이루어지는 것을 특징으로 하는 반도체 장치 제조 방법.And the sacrificial film is made of a silicon oxide film having better step coverage characteristics than a TEOS film. 제 1 항에 있어서,The method of claim 1, 상기 USG막은 상기 평탄화 작업을 통해 적층 두께의 50 내지 90% 정도가 제거되는 것을 특징으로 하는 반도체 장치 제조 방법.The USG film is a method of manufacturing a semiconductor device, characterized in that 50 to 90% of the stack thickness is removed through the planarization operation.
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Publication number Priority date Publication date Assignee Title
KR19990061043A (en) * 1997-12-31 1999-07-26 김영환 Metal wiring formation method of semiconductor device

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