JP2009295733A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus which has a structure allowing the reduction in a parasitic capacitance between two conductors or between a conductor and a substrate as well as the maintenance of mechanical strength, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor apparatus 1 includes: a semiconductor substrate 2; first and second layer metallic wirings 11, 16 which are formed on the semiconductor substrate 2; and first and second interlayer insulation films 12, 14 which are formed between the first and second layer metallic wirings 11, 16. The first and second layer metallic wirings 11, 16 sandwich the first and second interlayer insulation films 12, 14, and the portions of the first and second interlayer insulation films 12, 14, which are sandwiched by the first and second metallic wirings 11, 16, include air gaps 13. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a metal wiring structure for a semiconductor device and a method for manufacturing the same, and more particularly to a metal wiring structure for reducing capacitance between conductors and maintaining mechanical strength and a method for manufacturing the same.

  The capacitance detection type surface shape recognition device is a device for recognizing the shape of the surface of an object by detecting the capacitance of a large number of arranged metal electrodes and the object. However, the presence of parasitic capacitance between the metal electrode and the metal wiring layer or parasitic capacitance between the metal wiring layer and the substrate deteriorates the detection accuracy of the capacitance between the object and the metal electrode. For this reason, many techniques have been developed to reduce parasitic capacitance. Further, not only the capacitance detection type surface shape recognition device but also the reduction of parasitic capacitance is indispensable in order to reduce the signal transmission delay of the semiconductor device constituting the device.

  Conventionally, silicon oxide films have been mainly used as insulating films for metal electrodes and metal wiring layers. Instead, the parasitic capacitance is reduced by using a configuration in which the relative dielectric constant of the insulating film is lowered.

  Patent Document 1 discloses that the parasitic capacitance in the semiconductor device can be reduced by forming the region of the interlayer insulating film with air. This can be formed as follows.

As shown in FIG. 7A, a MOS (Metal Oxide Semiconductor) transistor 102 formed on a semiconductor substrate 103 is added to a substrate covering film 104 made of SiO ₂ (silicon dioxide), and a lower carbon film 105. Then, a lower silicon dioxide film 106 and an upper carbon film 107 are sequentially deposited. Further, a wiring groove is formed in the upper carbon film 107 using the lower silicon dioxide film 106 as an etching stopper film, and a contact hole penetrating the lower silicon dioxide film 106 and the lower carbon film 105 is formed from the bottom surface of the groove. . Furthermore, after depositing the barrier metal film 108 and the Cu (copper) alloy film 109 by sputtering, the wiring grooves are filled by heat treatment, and planarized by CMP (Chemical Mechanical Polishing). A wiring layer made of the copper alloy film 109 is formed. Further, an upper silicon dioxide film 110 is deposited.

  By sequentially repeating these steps, as shown in FIG. 7B, after forming a multilayer wiring structure, a dummy opening 111 reaching the substrate coating film 104 is formed by etching.

  Finally, as shown in FIG. 7C, the lower carbon film 105 and the upper carbon film 107 are removed by, for example, ashing using oxygen plasma or the like. As a result, the semiconductor device 101 in which the region of the interlayer insulating film is configured by the air layer 112 is formed.

  Non-Patent Document 1 discloses that the parasitic capacitance in the semiconductor device can be reduced by forming the interlayer insulating film region with a low dielectric constant film. This can be formed as follows.

As shown in FIG. 8A, a contact etching stopper film 115 made of SiN (silicon nitride) and an interlayer insulating film 116 made of SiO ₂ (silicon dioxide) are sequentially deposited on a MOS transistor 113 formed on a semiconductor substrate 114. Let Further, a contact hole that penetrates the interlayer insulating film 116 and the contact etching stopper film 115 is formed.

  Subsequently, a metal barrier film 117 is deposited by sputtering, and a tungsten film 118 is deposited by CVD (Chemical Vapor Deposition). Thereafter, the tungsten film 118, the metal barrier film 117, and the interlayer insulating film 116 are polished and planarized by CMP. Further, a barrier film 119 made of SiC (silicon carbide) or SiCN (nitrogen-added silicon carbide) or the like is deposited by CVD, and an interlayer insulating film 120 having a low dielectric constant is deposited thereon by CVD or coating. To form. Further, a cap film 121 made of TEOS (tetraethoxysilane) is deposited by CVD.

  Next, as shown in FIG. 8B, grooves are formed in the cap film 121, the low dielectric constant interlayer insulating film 120, and the barrier film 119 by photolithography and etching. Subsequently, a metal barrier film 122 made of Ti / TiN (titanium / titanium nitride), Ta / TaN (tantalum / tantalum nitride), or the like is deposited by sputtering, and the trench is filled with the copper film 123. Subsequently, the copper film 123, the metal barrier film 122, and the cap film 121 are polished and planarized by CMP.

In this way, a wiring structure in which the low dielectric constant interlayer insulating film 120 and the copper film 123 are aligned at the same height is formed. By repeating these steps, a semiconductor device 124 having a low dielectric constant interlayer insulating film as shown in FIG. 8C is formed.
JP 11-126820 A (published on May 11, 1999) “Development of multilayer wiring technology for 45 nanometer generation LSIs-FUJITSU Japan”, [online], Fujitsu Laboratories Ltd. press release, [Search April 17, 2008], Internet <URL: http://pr.fujitsu .com / jp / news / 2005/06 / 6-1.html>

  In the technique disclosed in Patent Document 1, the parasitic capacitance is sufficiently reduced by the gaps extending between the entire metal wiring layers. However, the structure that supports each metal wiring layer formed in layers is only a contact portion that connects the upper and lower layers, and there is a problem that the mechanical strength is weak. For this reason, in dicing, wire bonding, etc., when stress is applied to the chip, problems such as disconnection or short circuit in the wiring occur.

  Also, other techniques disclosed in Non-Patent Document 1 can reduce the parasitic capacitance between metal wiring layers, but the molecular bonds of low-k (low dielectric constant) materials used as insulating films are weak. For this reason, the mechanical strength is similarly weak, and problems such as cracks occur when stress is applied to the chip as in the technique disclosed in Patent Document 1. Furthermore, in the prior art using a silicon oxide film as an interlayer insulating film, the mechanical strength is maintained, but parasitic capacitance becomes a problem.

  The present invention has been made in view of the above problems, and its object is to realize a reduction in parasitic capacitance between two conductors or between a conductor and a substrate while reducing mechanical capacitance. An object of the present invention is to provide a semiconductor device having a structure capable of maintaining strength and a method for manufacturing the same.

  In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate, a first conductor and a second conductor formed on the semiconductor substrate, the first conductor, and the second conductor. An interlayer insulating film layer formed between the first and second conductors, wherein at least a part of the first conductor and the second conductor are opposed to each other in the semiconductor device facing the interlayer insulating film layer. A region of the film layer sandwiched between the first conductor and the second conductor has a gap.

  According to the invention, since the gap is composed of air, the relative permittivity is 1, and the permittivity is lower than that of the interlayer insulating film layer having a relative permittivity of greater than 1. Therefore, by providing the gap, the parasitic capacitance between the first conductor and the second conductor is reduced.

  In addition, the portion of the region sandwiched between the first conductor and the second conductor that does not have the gap is composed of the interlayer insulating film layer, so that the mechanical strength can be maintained. .

  Accordingly, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In the semiconductor device, the interlayer insulating film layer includes a first interlayer insulating film layer and a second interlayer insulating film layer, and the first conductor, the first interlayer insulating film layer, the first interlayer insulating film layer, Two interlayer insulating layers and the second conductor are stacked, and the gap is a region of the first interlayer insulating layer sandwiched between the first conductor and the second conductor, Alternatively, the second interlayer insulating film layer may be formed in a region sandwiched between the first conductor and the second conductor.

  In the semiconductor device, the gap may be formed by a plurality of holes.

  Further, in the semiconductor device, the gap may be a hole formed in a direction perpendicular to a surface where the first conductor and the second conductor face each other.

  In the semiconductor device, a cross section of the hole parallel to the facing surface may be arranged at a position constituting a vertex of a polygon arranged periodically in the same plane.

  With these configurations, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the first conductor and the second conductor.

  In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate, a first conductor formed on the semiconductor substrate, and an interlayer formed between the semiconductor substrate and the first conductor. An insulating film layer, wherein at least a part of the semiconductor substrate and the first conductor is opposed to the first conductor of the interlayer insulating film layer in a semiconductor device facing the interlayer insulating film layer. The region sandwiched between the semiconductor substrates has a gap.

  According to the invention, since the gap is composed of air, the relative permittivity is 1, and the permittivity is lower than that of the interlayer insulating film layer having a relative permittivity of greater than 1. Therefore, by providing the gap, the parasitic capacitance between the first conductor and the semiconductor substrate is reduced.

  In addition, since a portion of the region sandwiched between the first conductor and the semiconductor substrate that does not have the gap is formed of the interlayer insulating film layer, the mechanical strength can be maintained.

  Therefore, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the first conductor and the semiconductor substrate. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In the semiconductor device, the interlayer insulating film layer includes a first interlayer insulating film layer and a second interlayer insulating film layer, and the semiconductor substrate, the first interlayer insulating film layer, the second interlayer insulating film layer, and the second interlayer insulating film layer. The interlayer insulating film layer and the first conductor are stacked and arranged, and the gap is a region of the first interlayer insulating film layer sandwiched between the semiconductor substrate and the first conductor, or the second conductor. The interlayer insulating film layer may be formed in a region sandwiched between the semiconductor substrate and the first conductor.

  In the semiconductor device, the gap may be formed by a plurality of holes.

  Furthermore, in the semiconductor device, the gap may be a hole formed in a direction perpendicular to a surface of the semiconductor substrate and the first conductor facing each other.

  In the semiconductor device, a cross section of the hole parallel to the facing surface may be arranged at a position constituting a vertex of a polygon arranged periodically in the same plane.

  With these configurations, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the semiconductor substrate and the first conductor.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device formed on a semiconductor substrate, the step of forming a first conductor on the semiconductor substrate, Depositing a first interlayer insulating film on the first conductor; forming a gap in a region of the first interlayer insulating film deposited on the first conductor; and the first interlayer A step of depositing a second interlayer insulating film on the insulating film; a step of planarizing the second interlayer insulating film; and a region of the second interlayer insulating film deposited on the gap. And a step of forming two conductors.

  According to the invention, the first conductor, the first interlayer insulating film, the second interlayer insulating film, and the second conductor are stacked, and the gap is formed in the first interlayer insulating film layer. A semiconductor device formed in a region sandwiched between the first conductor and the second conductor can be manufactured. Accordingly, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In the method for manufacturing a semiconductor device, in the step of forming the air gap, polygonal vertices arranged periodically are formed in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. A cross section of the gap that is parallel to the surface of the semiconductor substrate may be disposed at a position.

  In the method for manufacturing a semiconductor device, a plurality of voids may be formed simultaneously in the step of forming the voids.

  Furthermore, in the method for manufacturing a semiconductor device, in the step of planarizing the second interlayer insulating film, the gap may be planarized so as not to be exposed.

  The semiconductor device manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device formed on a semiconductor substrate, the step of depositing a first interlayer insulating film on the semiconductor substrate, Forming a gap in the first interlayer insulating film, depositing a second interlayer insulating film on the first interlayer insulating film, planarizing the second interlayer insulating film, and the second interlayer Forming a first conductor on a region of the insulating film deposited on the gap.

  According to the invention, the semiconductor substrate, the first interlayer insulating film, the second interlayer insulating film, and the first conductor are stacked, and the gap is formed in the first interlayer insulating film layer. A semiconductor device formed in a region sandwiched between the semiconductor substrate and the first conductor can be manufactured. Therefore, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the conductor and the substrate. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In the method for manufacturing a semiconductor device, in the step of forming the air gap, polygonal vertices arranged periodically are formed in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. A cross section of the gap that is parallel to the surface of the semiconductor substrate may be disposed at a position.

  In the method for manufacturing a semiconductor device, a plurality of voids may be formed simultaneously in the step of forming the voids.

  Furthermore, in the method for manufacturing a semiconductor device, in the step of planarizing the second interlayer insulating film, the gap may be planarized so as not to be exposed.

  The semiconductor device manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the conductor and the substrate. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device formed on a semiconductor substrate, the step of forming a first conductor on the semiconductor substrate, A step of depositing a first interlayer insulating film on the first conductor; a step of planarizing the first interlayer insulating film; and a region of the first interlayer insulating film deposited on the first conductor. A step of forming a void; a step of depositing a second interlayer insulating film on the first interlayer insulating film; and a region of the second interlayer insulating film deposited on the void. And a step of forming two conductors.

  According to the invention, the first conductor, the first interlayer insulating film, the second interlayer insulating film, and the second conductor are stacked, and the gap is formed in the first interlayer insulating film layer. A semiconductor device formed in a region sandwiched between the first conductor and the second conductor can be manufactured. Accordingly, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  Further, by flattening the first interlayer insulating film, a photoresist mask forming process when forming the gap can be improved. Specifically, the flattened shape further increases the process margin with respect to the depth of focus.

  In the method for manufacturing a semiconductor device, in the step of forming the air gap, polygonal vertices arranged periodically are formed in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. A cross section of the gap that is parallel to the surface of the semiconductor substrate may be disposed at a position.

  In the method for manufacturing a semiconductor device, a plurality of voids may be formed simultaneously in the step of forming the voids.

  The semiconductor device manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled. Further, by flattening the first interlayer insulating film, a photoresist mask forming process when forming the gap can be improved.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device formed on a semiconductor substrate, the step of depositing a first interlayer insulating film on the semiconductor substrate, Flattening the first interlayer insulating film, forming a gap in the first interlayer insulating film, depositing a second interlayer insulating film on the first interlayer insulating film, and the second interlayer Forming a first conductor on a region of the insulating film deposited on the gap.

  According to the invention, the semiconductor substrate, the first interlayer insulating film, the second interlayer insulating film, and the first conductor are stacked, and the gap is formed in the first interlayer insulating film layer. A semiconductor device formed in a region sandwiched between the semiconductor substrate and the first conductor can be manufactured. Therefore, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the conductor and the substrate. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  Further, by flattening the first interlayer insulating film, a photoresist mask forming process when forming the gap can be improved. Specifically, the flattened shape further increases the process margin with respect to the depth of focus.

  In the method for manufacturing a semiconductor device, in the step of forming the air gap, polygonal vertices arranged periodically are formed in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. A cross section of the gap that is parallel to the surface of the semiconductor substrate may be disposed at a position.

  In the method for manufacturing a semiconductor device, a plurality of voids may be formed simultaneously in the step of forming the voids.

  The semiconductor device manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the conductor and the substrate. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled. Further, by flattening the first interlayer insulating film, a photoresist mask forming process when forming the gap can be improved.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device formed on a semiconductor substrate, wherein a groove is formed in a first interlayer insulating film formed on the semiconductor substrate. Forming a first conductor having the same height as the first interlayer insulating film in the trench, and depositing a second interlayer insulating film on the first interlayer insulating film and the first conductor. A step of forming a void in a region of the second interlayer insulating film deposited on the first conductor, and a step of depositing a third interlayer insulating film on the second interlayer insulating film. And a step of forming a second conductor on a region of the third interlayer insulating film deposited on the gap.

  According to the invention, the first conductor, the second interlayer insulating film, the third interlayer insulating film, and the second conductor are stacked, and the gap is formed in the second interlayer insulating film layer. A semiconductor device formed in a region sandwiched between the first conductor and the second conductor can be manufactured. Accordingly, it is possible to realize a semiconductor device capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  In the manufacturing method of the semiconductor device, in the step of forming the air gap, polygonal vertices periodically arranged in a plane parallel to the surface of the semiconductor substrate of the second interlayer insulating film are formed. A cross section of the gap that is parallel to the surface of the semiconductor substrate may be disposed at a position.

  In the method for manufacturing a semiconductor device, a plurality of voids may be formed simultaneously in the step of forming the voids.

  The semiconductor device manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device can be freely controlled.

  As described above, in the semiconductor device according to the present invention, the region sandwiched between the first conductor and the second conductor in the interlayer insulating film layer has a gap.

  In the semiconductor device according to the present invention, as described above, the region sandwiched between the first conductor and the second conductor in the interlayer insulating film layer has a gap.

  Further, as described above, the semiconductor device according to the present invention includes the step of forming the first conductor on the semiconductor substrate, the step of depositing the first interlayer insulating film on the first conductor, and the first step. Forming a gap in a region of the interlayer insulating film deposited on the first conductor; depositing a second interlayer insulating film on the first interlayer insulating film; and second interlayer insulating The method includes a step of planarizing the film and a step of forming a second conductor in a region of the second interlayer insulating film deposited on the gap.

  Further, as described above, the semiconductor device according to the present invention includes a step of depositing a first interlayer insulating film on the semiconductor substrate, a step of forming a gap in the first interlayer insulating film, and the first interlayer insulating film. A step of depositing a second interlayer insulating film on the film; a step of planarizing the second interlayer insulating film; and a region of the second interlayer insulating film deposited on the gap in the first conductor. Forming the step.

  Furthermore, as described above, the semiconductor device according to the present invention includes a step of forming a first conductor on the semiconductor substrate, a step of depositing a first interlayer insulating film on the first conductor, and the first step. A step of planarizing the first interlayer insulating film; a step of forming a gap in a region of the first interlayer insulating film deposited on the first conductor; and a second on the first interlayer insulating film. The method includes a step of depositing an interlayer insulating film and a step of forming a second conductor in a region of the second interlayer insulating film deposited on the gap.

  Furthermore, as described above, the semiconductor device according to the present invention includes a step of depositing a first interlayer insulating film on the semiconductor substrate, a step of planarizing the first interlayer insulating film, and the first interlayer insulating film. Forming a gap in the first interlayer insulating film; depositing a second interlayer insulating film on the first interlayer insulating film; and a first conductor in a region of the second interlayer insulating film deposited on the gap. Forming the step.

  Further, as described above, the semiconductor device according to the present invention includes a step of forming a groove in the first interlayer insulating film formed on the semiconductor substrate, and the groove having the same height as the first interlayer insulating film. A step of forming a first conductor, a step of depositing a second interlayer insulating film on the first interlayer insulating film and the first conductor, and a step of forming the second interlayer insulating film on the first conductor. A step of forming a void in the region deposited in the step, a step of depositing a third interlayer insulating film on the second interlayer insulating film, and a region of the third interlayer insulating film deposited on the void. And a step of forming a second conductor.

  Therefore, a semiconductor device having a structure capable of maintaining mechanical strength while realizing reduction in parasitic capacitance between two conductors or parasitic capacitance between a conductor and a substrate, and a method for manufacturing the same are provided. The effect of doing.

  One embodiment of the present invention will be described below with reference to Examples 1 to 3 and FIGS. 1 to 6. In the drawings describing the embodiment, the same reference numerals are given to portions having the same function, and repeated description thereof is omitted. Moreover, a well-known means is used about the part which is not explained in full detail in a manufacturing process.

In the following examples, a metal wiring structure having an Al—Cu (aluminum-copper) alloy or Cu (copper) as a main material is taken as an example. However, in the present invention, other conductors are not limited to the above materials. May be used as wiring. The metal wiring structure may be an electrode structure for detecting capacitance. Furthermore, as an interlayer insulating film, an SiO ₂ (silicon dioxide) film or an FSG (Fluorinated Silicate Glass) film in which fluorine is added to SiO ₂ is taken as an example. However, in the present invention, other materials are not limited to the above materials. An insulating film material may be used as the interlayer insulating film.

[Example 1]
As shown in FIG. 1A, an element isolation region 3, a gate insulating film 4, a gate electrode 5, a sidewall 6, a metal silicide 7, a contact etching stopper film 8, a PMD film (Pre-Metal Dielectric) on a semiconductor substrate 2. A MOS (Metal Oxide Semiconductor) type semiconductor device including a pre-metal interlayer insulating film) 9 and a plug 10 is formed using a known means.

  On the MOS type semiconductor device thus formed, an Al—Cu alloy is deposited to a thickness of about 300 nm by a sputtering method, and a first layer metal wiring 11 having a desired pattern is formed by a photoresist mask and dry etching to form a PMD film. 9 is formed.

  Next, as shown in FIG. 1B, a first interlayer insulating film 12 made of a silicon oxide film is deposited to a thickness of about 800 nm by plasma CVD (Chemical Vapor Deposition). The gap 13 is formed by a photoresist mask and dry etching.

  At this time, the ratio (aspect ratio) between the width of the gap 13 and the height of the first interlayer insulating film 12 is set to about 3 or more, for example, 2.5 or more. This is because when the second interlayer insulating film 14 described later is deposited, the gap 13 is held without being filled. When the aspect ratio is 2.5 or more and the gap 13 is held without being filled, the gap is filled when the aspect ratio is 0 or more and less than 2.5.

  For the gap 13 that satisfies the above-described aspect ratio, when the second interlayer insulating film 14 is deposited, the entrance of the gap 13 is closed earlier than the gap 13 fills the insulating film. 13 can be held without being filled.

  More specifically, when the deposition of the second interlayer insulating film 14 is started, the second interlayer insulating film 14 is deposited on the first interlayer insulating film 12, and at the same time, the bottom of the gap 13 and the side wall of the gap 13. In addition, deposition of the second interlayer insulating film 14 proceeds. If the aspect ratio is about 3 or more, the amount of deposition of the second interlayer insulating film 14 inside the gap 13 is slightly smaller than the amount of deposition of the second interlayer insulating film 14 on the first interlayer insulating film 12. It becomes quantity. For this reason, the upper part of the space | gap 13 closes with the space | gap 13 hold | maintained.

  In the above description, an example of the aspect ratio is set to 2.5 or more. However, this numerical range changes depending on the interlayer film forming conditions, and may be 2.55 or more or 2.495 or more.

  Further, as long as the aspect ratio is ensured, the gap 13 does not need to reach the first layer metal wiring 11, that is, the first interlayer insulating film 12 is interposed between the gap 13 and the first layer metal wiring 11. May be present. This can be controlled by adjusting the dry etching time when the gap 13 is formed. By adjusting the width, depth, and number of the gaps 13, the capacitance between the first layer metal wiring 11 and a second layer metal wiring 16 described later can be controlled.

  The width and number of the gaps 13 can be easily changed by the pattern layout of the photoresist mask. An example of the pattern layout of the gap 13 is shown in FIGS. 2 (a) and 2 (b).

  Each void has a structure that is arranged at the positions of the apexes of periodically arranged polygons such as a honeycomb structure. Each gap is preferably arranged at a position that forms the apex of an equilateral triangle or rhombus arranged periodically, but periodically arranged, parallelogram, line-symmetric hexagon, or point-symmetric May be arranged at positions constituting the vertices of the hexagon. The diameter of each void is about 50 nm to 500 nm.

  In FIG. 2 (a), the respective gaps are arranged at positions constituting the vertices of the equilateral triangle. Further, as shown in FIG. 2 (b), each of the voids may be arranged at a position that forms an apex of an octagon in which equilateral triangles and squares are combined and arranged in two point contrasts. By arranging the respective gaps at these positions, the mechanical strength of the semiconductor device 1 described later is maintained.

  Next, as shown in FIG. 1C, a second interlayer insulating film 14 made of a silicon oxide film is deposited by about 500 nm by plasma CVD. Subsequently, the second interlayer insulating film 14 is polished by about 350 nm by CMP for planarization. Further, a pattern penetrating the second interlayer insulating film 14 and the first interlayer insulating film 12 is formed by a photoresist mask and dry etching, a barrier film is deposited on the penetrating pattern by a sputtering method, and a tungsten film is formed. The plug 15 is formed by embedding by CVD and polishing by CMP. Subsequently, an Al—Cu alloy is deposited to a thickness of about 300 nm by a sputtering method, and a second layer metal wiring 16 having a desired pattern is formed on the second interlayer insulating film 14 by a photoresist mask and dry etching. 1 is formed.

  As described above, the semiconductor device 1 according to the embodiment of the present invention includes the semiconductor substrate 2, the first layer metal wiring 11 and the second layer metal wiring 16 formed on the semiconductor substrate 2, and the first layer. An interlayer insulating film layer formed between the metal wiring 11 and the second layer metal wiring 16, and at least a part of the first layer metal wiring 11 and the second layer metal wiring 16 includes the interlayer insulating film layer. In the semiconductor device facing each other with a gap therebetween, a region between the first layer metal wiring 11 and the second layer metal wiring 16 in the interlayer insulating film layer has a gap 13.

  In the semiconductor device 1, since the air gap 13 is composed of air, the relative permittivity is 1, the relative permittivity is greater than 1, and the permittivity is higher than that of the first interlayer insulating film 12 and the second interlayer insulating film 14. Low. Therefore, by providing the air gap 13, the parasitic capacitance between the first layer metal wiring 11 and the second layer metal wiring 16 is reduced.

  In addition, a portion of the region sandwiched between the first layer metal wiring 11 and the second layer metal wiring 16 that does not have the gap 13 is composed of the first interlayer insulating film 12 and the second interlayer insulating film 14. Therefore, the mechanical strength can be maintained.

  Accordingly, it is possible to realize the semiconductor device 1 that can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction of parasitic capacitance and the mechanical strength in a specific region in the semiconductor device 1 can be freely controlled.

  The semiconductor device 1 includes a first interlayer insulating film 12 and a second interlayer insulating film 14, and includes a first layer metal wiring 11, a first interlayer insulating film 12, a second interlayer insulating film 14, and a second layer metal wiring. 16 are stacked, and the gap 13 is formed in the first interlayer insulating film 12 in the region sandwiched between the first layer metal wiring 11 and the second layer metal wiring 16 or in the first interlayer insulating film 14. It may be formed in a region sandwiched between the layer metal wiring 11 and the second layer metal wiring 16.

  In the semiconductor device 1, the gap 13 may be formed by a plurality of holes.

  Further, in the semiconductor device 1, the air gap 13 may be a hole formed in a direction perpendicular to the opposing surfaces of the first layer metal wiring 11 and the second layer metal wiring 16.

  In the semiconductor device 1, the cross section of the hole parallel to the facing surface may be arranged at a position that constitutes a vertex of a polygon arranged periodically in the same surface.

  In the manufacturing method of the semiconductor device 1 described above, the method of forming the air gap 13 in the first interlayer insulating film 12 between the first layer metal wiring 11 and the second layer metal wiring 16 in the semiconductor device 1 is taken as an example. The gap 13 may be provided in the second interlayer insulating film 14, and when a plurality of interlayer insulating films are formed, the gap may be formed in any one of them. Further, in the case of a semiconductor device having a multilayer wiring structure, even when a void is formed in an interlayer insulating film provided between two upper metal wirings, the same process can be realized.

  In addition, a gap can be formed between the semiconductor substrate and the first layer metal wiring by the same manufacturing method. As shown in FIG. 3A, a MOS semiconductor device including an element isolation region 19, a gate insulating film 20, a gate electrode 21, sidewalls 22, a metal silicide 23, and a contact etching stopper film 24 on a semiconductor substrate 18 is provided. It forms using a well-known means.

  Next, as shown in FIG. 3B, a first interlayer insulating film 25 made of a silicon oxide film is deposited to a thickness of about 800 nm by plasma CVD, and a void 26 is formed thereon by a photoresist mask and dry etching.

  At this time, the ratio (aspect ratio) between the width of the gap 26 and the height of the first interlayer insulating film 25 is set to about 3 or more, for example, 2.5 or more. This is because the gap 26 is held without being filled when a second interlayer insulating film 27 described later is deposited. When the aspect ratio is 2.5 or more and the gap 26 is held without being filled, the gap is filled when the aspect ratio is 0 or more and less than 2.5.

  For the gap 26 satisfying the above aspect ratio, when the second interlayer insulating film 27 is deposited, the entrance of the gap 26 is closed earlier than the gap 26 is filled with the insulating film. 26 can be held without being filled.

  More specifically, when the second interlayer insulating film 27 starts to be deposited, the second interlayer insulating film 27 is deposited on the first interlayer insulating film 25. At the same time, the bottom of the gap 26 and the side wall of the gap 26 are deposited. In addition, deposition of the second interlayer insulating film 27 proceeds. If the aspect ratio is about 3 or more, the deposition amount of the second interlayer insulating film 27 inside the gap 26 is slightly smaller than the deposition amount of the second interlayer insulating film 27 on the first interlayer insulating film 25. It becomes quantity. For this reason, the upper part of the space | gap 26 closes with the space | gap 26 hold | maintained.

  In the above description, an example of the aspect ratio is set to 2.5 or more. However, this numerical range changes depending on the interlayer film forming conditions, and may be 2.55 or more or 2.495 or more.

  Further, as long as the aspect ratio is ensured, the depth of the gap 26 does not need to reach the contact etching stopper film 24, that is, the first interlayer insulating film 25 between the gap 26 and the contact etching stopper film 24. May be present. This can be controlled by adjusting the dry etching time when forming the air gap 26. By adjusting the width, depth, and number of the gaps 26, the capacitance between the semiconductor substrate 18 and a first layer metal wiring 29 described later can be controlled.

  The width and number of the voids 26 can be easily changed by the pattern layout of the photoresist mask. The pattern layout of the gap 13 shown in FIGS. 2A and 2B may be used as the pattern layout of the gap 26. By adopting such a pattern layout, the mechanical strength of the semiconductor device 17 described later is maintained.

  Next, as shown in FIG. 3C, a second interlayer insulating film 27 made of a silicon oxide film is deposited by about 500 nm by plasma CVD. Subsequently, the second interlayer insulating film 27 is polished by about 350 nm by CMP for planarization. Further, a pattern penetrating the second interlayer insulating film 27, the first interlayer insulating film 25 and the contact etching stopper film 24 is formed by a photoresist mask and dry etching, and a barrier film is formed on the penetrating pattern by sputtering. The plug 28 is formed by depositing, filling the tungsten film by the CVD method, and polishing it by CMP. Subsequently, an Al—Cu alloy is deposited to a thickness of about 300 nm by a sputtering method, and a first layer metal wiring 29 having a desired pattern is formed on the second interlayer insulating film 27 by a photoresist mask and dry etching. 17 is formed.

  As described above, the semiconductor device 17 according to the embodiment of the present invention includes the semiconductor substrate 18, the first layer metal wiring 29 formed on the semiconductor substrate 18, and the semiconductor substrate 18 and the first layer metal wiring 29. An interlayer insulating film layer formed therebetween, and at least a part of the semiconductor substrate 18 and the first layer metal wiring 29 is formed on the interlayer insulating film layer in the semiconductor device facing the interlayer insulating film layer. A region sandwiched between the first layer metal wiring 29 and the semiconductor substrate 18 has a gap 26.

  In the semiconductor device 17, since the air gap 26 is composed of air, the relative permittivity is 1, the relative permittivity is greater than 1, and the permittivity is higher than that of the first interlayer insulating film 25 and the second interlayer insulating film 27. Low. Therefore, by providing the air gap 26, the parasitic capacitance between the first layer metal wiring 29 and the semiconductor substrate 18 is reduced.

  In addition, a portion of the region sandwiched between the first layer metal wiring 29 and the semiconductor substrate 18 that does not have the air gap 26 is composed of the first interlayer insulating film 25 and the second interlayer insulating film 27. Strength can be maintained.

  Therefore, the semiconductor device 17 capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the first layer metal wiring 29 and the semiconductor substrate 18 can be realized. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device 17 can be freely controlled.

  The semiconductor device 17 includes a first interlayer insulating film 25 and a second interlayer insulating film 27, and the semiconductor substrate 18, the first interlayer insulating film 25, the second interlayer insulating film 27, and the first layer metal wiring 29 are stacked. The gap 26 is a region of the first interlayer insulating film 25 sandwiched between the semiconductor substrate 18 and the first layer metal wiring 29 or the semiconductor substrate 18 and the first layer metal of the second interlayer insulating film 27. It may be formed in a region sandwiched between the wirings 29.

  In the semiconductor device 17, the gap 26 may be formed by a plurality of holes.

  Further, in the semiconductor device 17, the air gap 26 may be a hole formed in a direction perpendicular to a surface where the semiconductor substrate 18 and the first layer metal wiring 29 face each other.

  In the semiconductor device 17, the cross section of the hole parallel to the facing surface may be arranged at a position that constitutes the apexes of the polygons periodically arranged in the same plane.

  With these configurations, it is possible to realize a semiconductor device that can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the semiconductor substrate 18 and the first layer metal wiring 29.

  In the manufacturing method of the semiconductor device 17 described above, the method of forming the air gap 26 in the first interlayer insulating film 25 between the semiconductor substrate 18 and the first layer metal wiring 29 in the semiconductor device 17 is taken as an example. The gap 26 may be provided in the interlayer insulating film 27. When a plurality of interlayer insulating films are formed, the gap may be formed in any one of them. Further, in the case of a semiconductor device having a multilayer wiring structure, even when a void is formed in an interlayer insulating film provided between two upper metal wirings, the same process can be realized.

[Example 2]
As shown in FIG. 4A, an element isolation region 32, a gate insulating film 33, a gate electrode 34, a sidewall 35, a metal silicide 36, a contact etching stopper film 37, a PMD film 38, and a plug 39 are formed on a semiconductor substrate 31. The structure of the MOS type semiconductor device provided is formed using a known means.

  On the MOS type semiconductor device thus formed, an Al—Cu alloy is deposited to a thickness of about 300 nm by a sputtering method, and a first layer metal wiring 40 having a desired pattern is formed by a photoresist mask and dry etching. 38.

  Next, as shown in FIG. 4B, a first interlayer insulating film 41 made of a silicon oxide film is deposited by about 1100 nm by plasma CVD, and the first interlayer insulating film 41 is 300 nm by CMP for planarization. Polish to a certain extent. A gap 42 is formed in this by a photoresist mask and dry etching.

  At this time, the ratio (aspect ratio) between the width of the gap 42 and the height of the first interlayer insulating film 41 is set to about 3 or more, for example, 2.5 or more. This is because when the second interlayer insulating film 43 described later is deposited, the gap 42 is held without being filled. When the aspect ratio is 2.5 or more and the gap 42 is held without being filled, the gap is filled when the aspect ratio is 0 or more and less than 2.5.

  For the gap 42 satisfying the above aspect ratio, when the second interlayer insulating film 43 is deposited, the entrance of the gap 42 is closed earlier than the gap 42 is filled with the insulating film. 42 can be held without being filled.

  More specifically, when the second interlayer insulating film 43 starts to be deposited, the second interlayer insulating film 43 is deposited on the first interlayer insulating film 41. At the same time, the bottom of the gap 42 and the side wall of the gap 42 are deposited. In addition, the deposition of the second interlayer insulating film 43 proceeds. If the aspect ratio is about 3 or more, the amount of deposition of the second interlayer insulating film 43 inside the gap 42 is slightly smaller than the amount of deposition of the second interlayer insulating film 43 on the first interlayer insulating film 41. It becomes quantity. For this reason, the upper part of the space | gap 42 closes with the space | gap 42 hold | maintained.

  In the above description, an example of the aspect ratio is set to 2.5 or more. However, this numerical range changes depending on the interlayer film forming conditions, and may be 2.55 or more or 2.495 or more.

  Further, as long as the aspect ratio is ensured, the depth of the gap 42 does not need to reach the first layer metal wiring 40, that is, the first interlayer insulation between the gap 42 and the first layer metal wiring 40. A membrane 41 may be present. This can be controlled by adjusting the dry etching time when forming the air gap 42. By adjusting the width, depth, and number of the gaps 42, the capacitance between the first layer metal wiring and the second layer metal wiring 45 described later can be controlled.

  The width and number of the gaps 42 can be easily changed by the pattern layout of the photoresist mask. The pattern layout of the gap 13 shown in FIGS. 2A and 2B may be used as the pattern layout of the gap 42. By setting it as such a pattern layout, the mechanical strength of the semiconductor device 30 mentioned later is hold | maintained.

  Next, as shown in FIG. 4C, a second interlayer insulating film 43 made of a silicon oxide film is deposited by about 200 nm by plasma CVD. Subsequently, a pattern penetrating the second interlayer insulating film 43 and the first interlayer insulating film 41 is formed by a photoresist mask and dry etching, and a barrier film is deposited on the penetrating pattern by a sputtering method to form a tungsten film. The plug 44 is formed by embedding by CVD and further polishing by CMP. Subsequently, an Al—Cu alloy is deposited to a thickness of about 300 nm by a sputtering method, and a second layer metal wiring 45 having a desired pattern is formed on the second interlayer insulating film 43 by a photoresist mask and dry etching. 30 is formed.

  As described above, the semiconductor device 30 according to the embodiment of the present invention includes the semiconductor substrate 31, the first layer metal wiring 40 and the second layer metal wiring 45 formed on the semiconductor substrate 31, and the first layer. An interlayer insulating film layer formed between the metal wiring 40 and the second layer metal wiring 45, and at least a part of the first layer metal wiring 40 and the second layer metal wiring 45 is formed of the interlayer insulating film layer. In the semiconductor device facing each other with a gap therebetween, a region sandwiched between the first layer metal wiring 40 and the second layer metal wiring 45 in the interlayer insulating film layer has a gap 42.

  In the semiconductor device 30, since the air gap 42 is composed of air, the relative permittivity is 1, and the permittivity is lower than that of the first interlayer insulating film 41 and the second interlayer insulating film 43 that have a relative permittivity of greater than 1. . Therefore, by providing the air gap 42, the parasitic capacitance between the first layer metal wiring 40 and the second layer metal wiring 45 is reduced.

  In addition, a portion of the region sandwiched between the first layer metal wiring 40 and the second layer metal wiring 45 that does not have the air gap 42 is constituted by the first interlayer insulating film 41 and the second interlayer insulating film 43. Therefore, the mechanical strength can be maintained.

  Therefore, the semiconductor device 30 capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors can be realized. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device 30 can be freely controlled.

  The semiconductor device 30 includes a first interlayer insulating film 41 and a second interlayer insulating film 43, and includes a first layer metal wiring 40, a first interlayer insulating film 41, a second interlayer insulating film 43, and a second layer metal wiring. 45 are stacked, and the gap 42 is formed in the first interlayer insulating film 41 in the region sandwiched between the first layer metal wiring 40 and the second layer metal wiring 45 or in the second interlayer insulating film 43. It may be formed in a region sandwiched between the layer metal wiring 40 and the second layer metal wiring 45.

  In the semiconductor device 30, the gap 42 may be formed by a plurality of holes.

  Further, in the semiconductor device 30, the air gap 42 may be a hole formed in a direction perpendicular to the opposing surfaces of the first layer metal wiring 40 and the second layer metal wiring 45.

  In the semiconductor device 30, the cross section of the hole parallel to the facing surface may be arranged at a position that constitutes the apexes of the polygons periodically arranged in the same plane.

  In the manufacturing method of the semiconductor device 30 described above, the method of forming the air gap 42 in the first interlayer insulating film 41 between the first layer metal wiring 40 and the second layer metal wiring 45 in the semiconductor device 30 is taken as an example. The gap 42 may be provided in the second interlayer insulating film 43. When a plurality of interlayer insulating films are formed, the gap may be formed in any one of them. In a semiconductor device having a multilayer wiring structure, even when a void is formed in an interlayer insulating film between upper metal wirings, it can be realized by the same process.

  In addition, a gap can be formed between the semiconductor substrate and the first layer metal wiring by the same manufacturing method. As shown in FIG. 5A, a MOS type semiconductor device comprising an element isolation region 48, a gate insulating film 49, a gate electrode 50, a sidewall 51, a metal silicide 52, and a contact etching stopper film 53 on a semiconductor substrate 47. It forms using a well-known means.

  Next, as shown in FIG. 5B, a first interlayer insulating film 54 made of a silicon oxide film is deposited by a plasma CVD method to about 1100 nm, and about 300 nm is polished by CMP for planarization. A gap 55 is formed in this by a photoresist mask and dry etching.

  At this time, the ratio (aspect ratio) between the width of the gap 55 and the height of the first interlayer insulating film 54 is set to about 3 or more, for example, 2.5 or more. This is because the gap 55 is held without being filled when a second interlayer insulating film 56 described later is deposited. When the aspect ratio is 2.5 or more and the gap 55 is held without being filled, the gap is filled when the aspect ratio is 0 or more and less than 2.5.

  For the gap 55 satisfying the aspect ratio described above, when the second interlayer insulating film 56 is deposited, the entrance of the gap 55 is closed earlier than the gap 55 is filled with the insulating film. 55 can be held without being filled.

  More specifically, when the deposition of the second interlayer insulating film 56 starts, the second interlayer insulating film 56 is deposited on the first interlayer insulating film 54, and at the same time, the bottom of the gap 55 and the side wall of the gap 55. In addition, the deposition of the second interlayer insulating film 56 proceeds. If the aspect ratio is about 3 or more, the deposition amount of the second interlayer insulating film 56 in the gap 55 is slightly smaller than the deposition amount of the second interlayer insulating film 56 on the first interlayer insulating film 54. It becomes quantity. For this reason, the upper part of the space | gap 55 closes with the space | gap 55 hold | maintained.

  In the above description, an example of the aspect ratio is set to 2.5 or more. However, this numerical range changes depending on the interlayer film forming conditions, and may be 2.55 or more or 2.495 or more.

  Further, as long as the aspect ratio is ensured, the depth of the gap 55 does not need to reach the contact etching stopper film 53, that is, the first interlayer insulating film 54 between the gap 55 and the contact etching stopper film 53. May be present. This can be controlled by adjusting the dry etching time when forming the gap 55. By adjusting the width, depth, and number of the gaps 55, it is possible to control the capacitance between the substrate and a first layer metal wiring 58 to be described later.

  The width and number of the gaps 55 can be easily changed by the pattern layout of the photoresist mask. The pattern layout of the gap 13 shown in FIGS. 2A and 2B may be used as the pattern layout of the gap 55. By adopting such a pattern layout, the mechanical strength of the semiconductor device 46 described later is maintained.

  Next, as shown in FIG. 5C, a second interlayer insulating film 56 made of a silicon oxide film is deposited by about 200 nm by plasma CVD. Subsequently, a pattern penetrating the second interlayer insulating film 56, the first interlayer insulating film 54 and the contact etching stopper film 53 is formed by a photoresist mask and dry etching, and a barrier film is formed on the penetrating pattern by a sputtering method. A plug 57 is formed by depositing, filling the tungsten film with a CVD method, and polishing it with CMP. Subsequently, an Al—Cu alloy is deposited to a thickness of about 300 nm by a sputtering method, and a first layer metal wiring 58 having a desired pattern is formed on the second interlayer insulating film 56 by a photoresist mask and dry etching. 46 is formed.

  As described above, the semiconductor device 46 according to the embodiment of the present invention includes the semiconductor substrate 47, the first layer metal wiring 58 formed on the semiconductor substrate 47, and the semiconductor substrate 47 and the first layer metal wiring 58. An interlayer insulating film layer formed therebetween, and at least part of the semiconductor substrate 47 and the first-layer metal wiring 58 is formed on the interlayer insulating film layer in the semiconductor device facing the interlayer insulating film layer. A region sandwiched between the first layer metal wiring 58 and the semiconductor substrate 47 has a gap 55.

  In the semiconductor device 46, since the air gap 55 is made of air, the relative permittivity is 1, the relative permittivity is greater than 1, and the permittivity is higher than that of the first interlayer insulating film 54 and the second interlayer insulating film 56. Low. Therefore, by providing the gap 55, the parasitic capacitance between the first layer metal wiring 58 and the semiconductor substrate 47 is reduced.

  In addition, the portion between the first layer metal wiring 58 and the semiconductor substrate 47 that does not have the gap 55 is composed of the first interlayer insulating film 54 and the second interlayer insulating film 56, so that the machine Strength can be maintained.

  Therefore, the semiconductor device 46 capable of maintaining the mechanical strength while realizing the reduction of the parasitic capacitance between the first layer metal wiring 58 and the semiconductor substrate 47 can be realized. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device 46 can be freely controlled.

  The semiconductor device 46 includes a first interlayer insulating film 54 and a second interlayer insulating film 56, and the semiconductor substrate 47, the first interlayer insulating film 54, the second interlayer insulating film 56, and the first layer metal wiring 58 are stacked. The gap 55 is formed in the region between the semiconductor substrate 47 and the first layer metal wiring 58 in the first interlayer insulating film 54 or the semiconductor substrate 47 and the first layer metal in the second interlayer insulating film 56. It may be formed in a region sandwiched between the wirings 58.

  In the semiconductor device 46, the gap 55 may be formed by a plurality of holes.

  Further, in the semiconductor device 46, the air gap 55 may be a hole formed in a direction perpendicular to the facing surface of the semiconductor substrate 47 and the first layer metal wiring 58.

  In the semiconductor device 46, the cross section of the hole parallel to the facing surface may be arranged at a position that constitutes the apexes of the polygons periodically arranged in the same surface.

  With these configurations, it is possible to realize a semiconductor device that can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the semiconductor substrate 47 and the first layer metal wiring 58.

  In the manufacturing method of the semiconductor device 46 described above, the method of forming the air gap 55 in the first interlayer insulating film 54 between the semiconductor substrate 47 and the first layer metal wiring 58 in the semiconductor device 46 is taken as an example. The gap 55 may be provided in the interlayer insulating film 56, and when a plurality of interlayer insulating films are formed, the gap may be formed in any one of them. Further, in the case of a semiconductor device having a multilayer wiring structure, even when a void is formed in an interlayer insulating film provided between two upper metal wirings, the same process can be realized.

Example 3
As shown in FIG. 6A, an element isolation region 61, a gate insulating film 62, a gate electrode 63, a sidewall 64, a metal silicide 65, a contact etching stopper film 66, a PMD film 67, and a plug 68 are formed on a semiconductor substrate 60. The structure of the MOS type semiconductor device provided is formed using a known means.

  A barrier film 69 made of SiC (silicon carbide), SiN (silicon nitride), or SiCN (nitrogen-added silicon carbide) is deposited on the MOS type semiconductor device formed in this manner by a plasma CVD method to a thickness of about 50 nm. Further, an FSG film 70 is deposited by about 300 nm by plasma CVD. Then, a desired pattern is formed by a photoresist mask and dry etching, and a barrier film 71 made of Ti / TiN (titanium / titanium nitride) film or the like is deposited on the desired pattern by a sputtering method of about 30 nm. A first layer metal wiring 72 is formed by depositing a Cu film constituting the wiring by a plating method of about 600 nm and polishing it by CMP.

  Next, as shown in FIG. 6B, a barrier film 73 made of SiC, SiN, SiCN, or the like is deposited by a plasma CVD method to about 50 nm, and a first interlayer insulating film 74 made of an FSG film is made 800 nm by the plasma CVD method. Deposition to a degree. A gap 75 is formed in this by a photoresist mask and dry etching.

  At this time, the ratio (aspect ratio) between the width of the gap 75 and the height of the first interlayer insulating film 74 is about 3 or more, for example, 2.5 or more. This is because when the second interlayer insulating film 76 to be described later is deposited, the gap 75 is held without being filled. When the aspect ratio is 2.5 or more and the gap 75 is not filled, the gap is filled when the aspect ratio is 0 or more and less than 2.5.

  For the gap 75 satisfying the above aspect ratio, when the second interlayer insulating film 76 is deposited, the entrance of the gap 75 is closed earlier than the gap 75 is filled with the insulating film. 75 can be held without being filled.

  More specifically, when the deposition of the second interlayer insulating film 76 starts, the second interlayer insulating film 76 is deposited on the first interlayer insulating film 74, and at the same time, the bottom of the gap 75 and the side wall of the gap 75. In addition, the deposition of the second interlayer insulating film 76 proceeds. If the aspect ratio is about 3 or more, the deposition amount of the second interlayer insulating film 76 inside the gap 75 is slightly smaller than the deposition amount of the second interlayer insulating film 76 on the first interlayer insulating film 74. It becomes quantity. For this reason, the upper part of the space | gap 75 closes with the space | gap 75 hold | maintained.

  In the above description, an example of the aspect ratio is set to 2.5 or more. However, this numerical range changes depending on the interlayer film forming conditions, and may be 2.55 or more or 2.495 or more.

  In addition, as long as the aspect ratio is ensured, the depth of the gap 75 does not need to reach the barrier film 73, that is, the first interlayer insulating film 74 exists between the gap 75 and the barrier film 73. Also good. This can be controlled by adjusting the dry etching time when forming the gap 75. By adjusting the width, depth, and number of the gaps 75, the capacitance between the first layer metal wiring 72 and a second layer metal wiring 82 described later can be controlled.

  The width and number of the gaps 75 can be easily changed by the pattern layout of the photoresist mask. The pattern layout of the gap 13 shown in FIGS. 2A and 2B may be used as the pattern layout of the gap 75. With such a pattern layout, the mechanical strength of the semiconductor device 59 described later is maintained.

  Next, as shown in FIG. 6C, a second interlayer insulating film 76 made of an FSG film is deposited by about 200 nm by plasma CVD. Subsequently, a desired pattern is formed by a photoresist mask and dry etching, a barrier film 77 made of a Ti / TiN film or the like is deposited on the desired pattern by a sputtering method of about 30 nm, and a Cu film constituting a plug is formed. A plug 78 is formed by depositing by about 600 nm plating and polishing by CMP.

  Subsequently, a barrier film 79 made of SiC, SiN, SiCN, or the like is deposited by a plasma CVD method to a thickness of about 50 nm, and an FSG film 80 is deposited by a plasma CVD method to a thickness of about 300 nm. On this, a desired pattern is formed by a photoresist mask and dry etching, and a barrier film 81 made of a Ti / TiN film or the like is deposited on the desired pattern by a sputtering method of about 30 nm to form a Cu film constituting a metal wiring. Is deposited by a plating method of about 600 nm and polished by CMP to form the second layer metal wiring 82, and the semiconductor device 59 is formed.

  As described above, the semiconductor device 59 according to the embodiment of the present invention includes the semiconductor substrate 60, the first layer metal wiring 72 and the second layer metal wiring 82 formed on the semiconductor substrate 60, and the first layer. An interlayer insulating film layer formed between the metal wiring 72 and the second layer metal wiring 82, and at least a part of the first layer metal wiring 72 and the second layer metal wiring 82 includes the interlayer insulating film layer. In the semiconductor device facing each other with a gap therebetween, a region between the first layer metal wiring 72 and the second layer metal wiring 82 in the interlayer insulating film layer has a gap 75.

  In the semiconductor device 59, since the gap 75 is made of air, the relative dielectric constant is 1, the relative dielectric constant is larger than 1, and the dielectric constant is higher than that of the first interlayer insulating film 74 and the second interlayer insulating film 76. Low. Therefore, by providing the gap 75, the parasitic capacitance between the first layer metal wiring 72 and the second layer metal wiring 82 is reduced.

  In addition, a portion of the region sandwiched between the first layer metal wiring 72 and the second layer metal wiring 82 that does not have the gap 75 is configured by the first interlayer insulating film 74 and the second interlayer insulating film 76. Therefore, the mechanical strength can be maintained.

  Therefore, it is possible to realize the semiconductor device 59 that can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. In addition, the amount of reduction in parasitic capacitance and the mechanical strength in a specific region in the semiconductor device 59 can be freely controlled.

  The semiconductor device 59 includes a first interlayer insulating film 74 and a second interlayer insulating film 76, and includes a first layer metal wiring 72, a first interlayer insulating film 74, a second interlayer insulating film 76, and a second layer metal wiring. 82 are stacked and the gap 75 is formed in the first interlayer insulating film 74 in a region sandwiched between the first layer metal wiring 72 and the second layer metal wiring 82 or in the first interlayer insulating film 76. It may be formed in a region sandwiched between the layer metal wiring 72 and the second layer metal wiring 82.

  In the semiconductor device 59, the gap 75 may be formed by a plurality of holes.

  Further, in the semiconductor device 59, the gap 75 may be a hole formed in a direction perpendicular to the surfaces of the first layer metal wiring 72 and the second layer metal wiring 82 facing each other.

  In the semiconductor device 59, the cross section of the hole parallel to the facing surface may be arranged at a position that constitutes the apexes of the periodically arranged polygons in the same surface.

  In the manufacturing method of the semiconductor device 59 described above, the method of forming the void 75 in the first interlayer insulating film 74 between the first layer metal wiring 72 and the second layer metal wiring 82 in the semiconductor device 59 is taken as an example. The gap 75 may be provided in the second interlayer insulating film 76, and when a plurality of interlayer insulating films are formed, the gap may be formed in any one of them. Further, in the case of a semiconductor device having a multilayer wiring structure, even when a void is formed in an interlayer insulating film provided between two upper metal wirings, the same process can be realized.

  In the method of manufacturing the semiconductor device 1, in the step of forming the air gap 13, the polygonal vertices periodically arranged in the plane parallel to the surface of the semiconductor substrate 2 of the first interlayer insulating film 12 are formed. A cross section of the gap 13 that is parallel to the surface of the semiconductor substrate 2 may be disposed at the position.

  In the method for manufacturing the semiconductor device 1, a plurality of voids may be formed at the same time in the step of forming the voids 13.

  Furthermore, in the method for manufacturing the semiconductor device 1, in the step of planarizing the second interlayer insulating film 14, planarization may be performed so that the gap 13 is not exposed.

  The semiconductor device 1 manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors.

  In the method for manufacturing the semiconductor device 17, in the step of forming the air gap 26, the apexes of the polygons periodically arranged in the plane parallel to the surface of the semiconductor substrate 18 of the first interlayer insulating film 25 are formed. A cross section of the air gap 26 may be disposed at a position parallel to the surface of the semiconductor substrate 18.

  Further, in the method for manufacturing the semiconductor device 17, a plurality of voids may be formed simultaneously in the step of forming the voids 26.

  Furthermore, in the method for manufacturing the semiconductor device 17, in the step of planarizing the second interlayer insulating film 27, the planarization may be performed so that the gap 26 is not exposed.

  The semiconductor device 17 manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors.

  In the method of manufacturing the semiconductor device 30, in the step of forming the air gap 42, the apexes of the polygons periodically arranged in the plane parallel to the surface of the semiconductor substrate 31 of the first interlayer insulating film 41 are configured. The cross section of the air gap 42 that is parallel to the surface of the semiconductor substrate 31 may be disposed at the position.

  In the method for manufacturing the semiconductor device 30, a plurality of voids may be formed simultaneously in the step of forming the voids 42.

  The semiconductor device 30 manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. Further, by planarizing the first interlayer insulating film 41, the step of forming a photoresist mask when forming the air gap 42 can be improved. Specifically, the flattened shape further increases the process margin with respect to the depth of focus.

  In the method for manufacturing the semiconductor device 46, in the step of forming the gap 55, the apexes of the polygons periodically arranged in the plane parallel to the surface of the semiconductor substrate 47 of the first interlayer insulating film 54 are formed. A cross section of the gap 55 that is parallel to the surface of the semiconductor substrate 47 may be disposed at the position.

  In the method of manufacturing the semiconductor device 46, in the step of forming the gap 55, a plurality of gaps may be formed at the same time.

  The semiconductor device 46 manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors. Further, by flattening the first interlayer insulating film 54, the step of forming a photoresist mask when forming the air gap 42 can be improved. Specifically, the flattened shape further increases the process margin with respect to the depth of focus.

  In the method of manufacturing the semiconductor device 59, in the step of forming the gap 75, the apexes of the polygons periodically arranged in the plane parallel to the surface of the semiconductor substrate 60 of the first interlayer insulating film 74 are formed. The cross section of the gap 75 that is parallel to the surface of the semiconductor substrate 60 may be disposed at the position.

  In the method for manufacturing the semiconductor device 59, in the step of forming the gap 75, a plurality of gaps may be formed simultaneously.

  The semiconductor device 59 manufactured by these methods can maintain the mechanical strength while realizing the reduction of the parasitic capacitance between the two conductors.

  In the present embodiment, the first layer metal wiring and the second layer metal wiring need only face each other across the interlayer insulating film layer. The portions that do not sandwich the interlayer insulating film layer do not need to face each other. Further, the first-layer metal wiring and the second-layer metal wiring have the same area, and the interlayer insulating film layers may be sandwiched so as to completely face each other without shifting.

  Furthermore, in the present embodiment, the semiconductor substrate and the first layer metal wiring only have to face each other between the semiconductor substrate and the first layer metal wiring with the interlayer insulating film layer interposed therebetween.

  The semiconductor device of the present invention can maintain the mechanical strength while reducing the parasitic capacitance between two conductors or the parasitic capacitance between the conductor and the substrate. It can utilize suitably for a surface shape recognition apparatus.

It is a schematic cross section which shows the manufacture main process of the semiconductor device which concerns on the Example of this invention. It is a schematic diagram which shows an example of the layout pattern of the space | gap which concerns on embodiment of this invention. It is a schematic cross section which shows the manufacture main process of the other semiconductor device which concerns on the Example of this invention. It is a schematic cross section which shows the manufacture main process of the semiconductor device which concerns on the other Example of this invention. It is a schematic cross section which shows the manufacture main process of the other semiconductor device which concerns on the other Example of this invention. It is a schematic cross section which shows the manufacture main process of the semiconductor device which concerns on another Example of this invention. (A)-(c) is a schematic cross section which shows the manufacture main process of the conventional semiconductor device. (A)-(c) is a schematic cross section which shows the manufacture main process of the conventional semiconductor device.

Explanation of symbols

1, 17, 30, 46, 59 Semiconductor device 2, 18, 31, 47, 60 Semiconductor substrate 3, 19, 32, 48, 61 Element isolation region 4, 20, 33, 49, 62 Gate insulating film 5, 21, 34, 50, 63 Gate electrode 6, 22, 35, 51, 64 Side wall 7, 23, 36, 52, 65 Metal silicide 8, 24, 37, 53, 66 Contact etching stopper film 9, 38, 67 PMD film 10 15, 28, 39, 44, 57, 68, 78 Plug 11, 29, 40, 58, 72 First layer metal wiring (first conductor)
12, 25, 41, 54 First interlayer insulating film (first interlayer insulating film layer)
13, 26, 42, 55, 75 Void 14, 27, 43, 56 Second interlayer insulating film (second interlayer insulating film layer)
16, 45, 82 Second layer metal wiring (second conductor)
69, 71, 73, 77, 79, 81 Barrier film 70 FSG film (first interlayer insulating film layer)
74 First interlayer insulating film (second interlayer insulating film layer)
76 Second interlayer insulating film (third interlayer insulating film layer)
80 FSG film

Claims (27)

A semiconductor substrate;
A first conductor and a second conductor formed on the semiconductor substrate;
An interlayer insulating film layer formed between the first conductor and the second conductor;
In the semiconductor device in which at least a part of the first conductor and the second conductor are opposed to each other with the interlayer insulating film layer interposed therebetween,
A region of the interlayer insulating film layer sandwiched between the first conductor and the second conductor has a gap. The interlayer insulating film layer includes a first interlayer insulating film layer and a second interlayer insulating film layer,
The first conductor, the first interlayer insulating film layer, the second interlayer insulating film layer, and the second conductor are stacked and arranged,
The gap is a region of the first interlayer insulating film layer sandwiched between the first conductor and the second conductor, or the first conductor and the second interlayer insulating film layer. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a region sandwiched between the second conductors.   The semiconductor device according to claim 1, wherein the gap is formed by a plurality of holes.   2. The semiconductor device according to claim 1, wherein the gap is a hole formed in a direction perpendicular to a surface of the first conductor and the second conductor facing each other.   5. The cross section of the hole parallel to the facing surface is arranged at a position constituting a vertex of a polygon arranged periodically in the same surface. 6. Semiconductor device. A semiconductor substrate;
A first conductor formed on the semiconductor substrate;
An interlayer insulating film layer formed between the semiconductor substrate and the first conductor,
In the semiconductor device in which at least a part of the semiconductor substrate and the first conductor are opposed to each other with the interlayer insulating film layer interposed therebetween,
A region of the interlayer insulating film layer sandwiched between the first conductor and the semiconductor substrate has a gap. The interlayer insulating film layer includes a first interlayer insulating film layer and a second interlayer insulating film layer,
The semiconductor substrate, the first interlayer insulating film layer, the second interlayer insulating film layer, and the first conductor are stacked and arranged,
The void is a region of the first interlayer insulating film layer sandwiched between the semiconductor substrate and the first conductor, or the semiconductor substrate and the first conductor of the second interlayer insulating film layer. The semiconductor device according to claim 6, wherein the semiconductor device is formed in a region sandwiched between.   The semiconductor device according to claim 6, wherein the gap is formed by a plurality of holes.   The semiconductor device according to claim 1, wherein the gap is a hole formed in a direction perpendicular to a surface of the semiconductor substrate and the first conductor facing each other.   The cross section of the hole parallel to the facing surface is arranged at a position constituting a vertex of a polygon arranged periodically in the same surface. Semiconductor device. A method of manufacturing a semiconductor device formed on a semiconductor substrate,
Forming a first conductor on the semiconductor substrate;
Depositing a first interlayer insulating film on the first conductor;
Forming a void in a region of the first interlayer insulating film deposited on the first conductor;
Depositing a second interlayer insulating film on the first interlayer insulating film;
Planarizing the second interlayer insulating film;
Forming a second conductor on a region of the second interlayer insulating film deposited on the gap. A method for manufacturing a semiconductor device, comprising:   In the step of forming the air gap, the surface of the semiconductor substrate is positioned at a position constituting a vertex of a polygon arranged periodically in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. The method for manufacturing a semiconductor device according to claim 11, wherein a cross section of the air gap is disposed in parallel with the semiconductor device.   12. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of forming the gap, a plurality of gaps are formed simultaneously.   12. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of planarizing the second interlayer insulating film, the second interlayer insulating film is planarized so that the gap is not exposed. A method of manufacturing a semiconductor device formed on a semiconductor substrate,
Depositing a first interlayer insulating film on the semiconductor substrate;
Forming a void in the first interlayer insulating film;
Depositing a second interlayer insulating film on the first interlayer insulating film;
Planarizing the second interlayer insulating film;
Forming a first conductor on a region of the second interlayer insulating film deposited on the gap. A method for manufacturing a semiconductor device, comprising:   In the step of forming the air gap, the surface of the semiconductor substrate is positioned at a position constituting a vertex of a polygon arranged periodically in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. The method of manufacturing a semiconductor device according to claim 15, wherein a cross section of the air gap is disposed in parallel with each other.   16. The method of manufacturing a semiconductor device according to claim 15, wherein in the step of forming the gap, a plurality of gaps are formed simultaneously.   16. The method of manufacturing a semiconductor device according to claim 15, wherein in the step of planarizing the second interlayer insulating film, the second interlayer insulating film is planarized so that the gap is not exposed. A method of manufacturing a semiconductor device formed on a semiconductor substrate,
Forming a first conductor on the semiconductor substrate;
Depositing a first interlayer insulating film on the first conductor;
Planarizing the first interlayer insulating film;
Forming a void in a region of the first interlayer insulating film deposited on the first conductor;
Depositing a second interlayer insulating film on the first interlayer insulating film;
Forming a second conductor on a region of the second interlayer insulating film deposited on the gap. A method for manufacturing a semiconductor device, comprising:   In the step of forming the air gap, the surface of the semiconductor substrate is positioned at a position constituting a vertex of a polygon arranged periodically in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. The method of manufacturing a semiconductor device according to claim 19, wherein a cross section of the air gap that is parallel to the gap is disposed.   20. The method of manufacturing a semiconductor device according to claim 19, wherein in the step of forming the gap, a plurality of gaps are formed simultaneously. A method of manufacturing a semiconductor device formed on a semiconductor substrate,
Depositing a first interlayer insulating film on the semiconductor substrate;
Planarizing the first interlayer insulating film;
Forming a void in the first interlayer insulating film;
Depositing a second interlayer insulating film on the first interlayer insulating film;
Forming a first conductor on a region of the second interlayer insulating film deposited on the gap. A method for manufacturing a semiconductor device, comprising:   In the step of forming the air gap, the surface of the semiconductor substrate is positioned at a position constituting a vertex of a polygon arranged periodically in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. 23. The method of manufacturing a semiconductor device according to claim 22, wherein a cross section of the air gap that is parallel to the cross section is disposed.   23. The method of manufacturing a semiconductor device according to claim 22, wherein, in the step of forming the air gap, a plurality of air gaps are simultaneously formed. A method of manufacturing a semiconductor device formed on a semiconductor substrate,
Forming a groove in the first interlayer insulating film formed on the semiconductor substrate;
Forming a first conductor having the same height as the first interlayer insulating film in the trench;
Depositing a second interlayer insulating film on the first interlayer insulating film and the first conductor;
Forming a void in a region of the second interlayer insulating film deposited on the first conductor;
Depositing a third interlayer insulating film on the second interlayer insulating film;
Forming a second conductor on a region of the third interlayer insulating film deposited on the gap. A method for manufacturing a semiconductor device, comprising:   In the step of forming the air gap, the surface of the semiconductor substrate is positioned at a position constituting a vertex of a polygon arranged periodically in a plane parallel to the surface of the semiconductor substrate of the first interlayer insulating film. 26. The method of manufacturing a semiconductor device according to claim 25, wherein a cross section of the air gap is disposed in parallel with the semiconductor device.   26. The method of manufacturing a semiconductor device according to claim 25, wherein in the step of forming the gap, a plurality of gaps are formed simultaneously.

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