JP2006228977A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inexpensively manufacture a semiconductor device having copper wiring on which a MIM capacitance element is formed. <P>SOLUTION: An additional interlayer film 26 is formed between a copper diffusion preventing film 14 on the copper wiring 22 and a lower electrode 27 of the MIM capacitance element, and the copper wiring 22 is disposed below the MIM capacitance element. Consequently, the reduction of the thickness of the copper diffusion preventing film 14 at a step formed accompanied by a step at a boundary between the copper wiring 22 and an interlayer insulating layer 13 caused by a Dishing phenomenon occurring when the copper wiring 22 is formed in a trench in the interlayer insulating layer 13 by a CMP method. It is thus possible to suppress a leakage current and hence improve an yield and to reduce a chip area for increasing an yield per wafer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a copper wiring in which a capacitive element can be arranged without considering the position of a copper wiring directly below.

In recent years, in semiconductor devices with a design rule of quarter micron or less, copper (Cu) is used instead of conventional aluminum (Al) wiring as a metal wiring material for miniaturization of wiring structure and low wiring resistance for suppressing signal delay. A lot of wiring has been used.
However, even in such a semiconductor device, conventional aluminum is used for a bonding pad to which a bonding wire is connected in order to exchange electric signals with the outside. This is because a copper pad has a high hardness, and therefore, when processing conditions are set such that the connection can be made, there is a problem that a crack is generated in an interlayer film covering the periphery of the bonding pad made of copper.

  Hereinafter, a procedure for forming an aluminum film on a bonding pad in a semiconductor device having two layers of copper wiring in a semiconductor manufacturing process using copper wiring will be described with reference to FIGS. 4A to 4F. This aluminum film may be used not only as a bonding pad but also as a wiring.

First, as shown in FIG. 4A, a semiconductor wafer on which desired copper wiring is formed is manufactured.
The cross-sectional structure shown in FIG. 4A is an interlayer insulating film 11 in which a copper wiring 21 is embedded, and a copper diffusion prevention film 12 is provided on the interlayer insulating film 11 and the copper wiring 2 is further embedded thereon. The layer 13 is formed.
The cross-sectional structure of the lower copper wiring 21 shown in FIG. 4A is obtained by forming a semiconductor element on a semiconductor wafer by a known semiconductor manufacturing process, and then forming an interlayer insulating layer 11 on the upper surface of the wafer. A groove is formed in the interlayer insulating layer 11 by dry etching, and then a TaN film, a TiN film, or the like, which becomes a copper diffusion prevention film, is formed by sputtering, and then copper plating is performed on the entire surface of the semiconductor wafer to fill the groove. Excess copper and the barrier film on the interlayer insulating layer 11 are removed by polishing by CMP (Chemical and Mechanical Polishing) method to form a copper wiring 21 embedded in the groove of the interlayer insulating layer 11 and exposing the upper surface. To do.

  The cross-sectional structure shown in FIG. 4A has a silicon nitride (hereinafter referred to as P-SiN) film formed by, for example, plasma CVD, which becomes the copper diffusion prevention layer 12 on the entire surface of the interlayer insulating layer 11 in which the copper wiring 21 is embedded. After forming with a thickness of several tens of nm, the upper interlayer insulating layer 13 is formed, a groove is formed in the interlayer insulating layer 13 by well-known photolithography and dry etching, and the lower copper wiring is formed on the copper diffusion preventing layer 12 A hole exposing 21 is formed. Thereafter, as described above, a TaN film or a TiN film to be a copper diffusion preventing film is formed by sputtering, and then copper plating is performed on the entire surface of the semiconductor wafer to fill the groove, and finally, an excess on the interlayer insulating layer 13 is formed. By removing the copper and the barrier film by the CMP method, a copper wiring 22 embedded in the groove of the interlayer insulating layer 13 and exposed on the upper surface is formed. Thereby, the cross-sectional structure shown in FIG. 4A is formed.

Next, as shown in FIG. 4B, a copper diffusion prevention film 14 made of a P-SiN film having a thickness of, for example, several tens of nm is formed on the interlayer insulating layer 13 where the upper surface of the copper wiring 22 is exposed.
Next, as shown in FIG. 4C, silicon oxide (hereinafter referred to as P-TEOS) generated on the copper diffusion prevention film 14 by tetraethoxysilane with a plasma CVD apparatus having a thickness of several hundred nm, for example. An interlayer insulating film 15 made of a film is formed.
Next, as shown in FIG. 4D, a part of the copper diffusion preventing film 14 and the interlayer insulating film 15 is removed so that the copper wiring 22 is exposed. That is, a resist mask is formed on the interlayer insulating film 15 using normal lithography, and the copper diffusion prevention film 14 and the interlayer insulating film 15 are selectively etched using a dry etching method such as RIE (Reactive Ion Etching). A contact hole 30 is formed, and then the resist mask is removed.

Next, as shown in FIG. 4E, aluminum is formed from above by sputtering or the like, and the contact hole 30 shown in FIG. 4D is filled and formed on the entire surface of the wafer. A pattern of aluminum having a predetermined shape is formed.
Finally, as shown in FIG. 4F, after the overcoat film 10 is formed on the entire surface of the wafer, only the connection pad portion is exposed using normal lithography, and the bonding pad 31 made of an aluminum film is formed.

Conventionally, a process using an aluminum material for the film used for the bonding pad as shown in FIG. 4 has a MIM (Metal-Insulator-Metal) layer between the copper wiring 22 and the aluminum film in order to reduce the base parasitic capacitance. ) In some cases, a process for providing a capacitive element was added.
FIGS. 5A to 5G show process steps for providing a MIM (Metal-Insulator-Metal) capacitive element between the copper film 22 and the aluminum film forming the bonding pad 31.

First, as shown in FIG. 5A, a semiconductor wafer in which the upper surface of a desired copper wiring is exposed from the interlayer insulating layer is manufactured. Here, the semiconductor wafer is processed in the same manner as in the example of FIG. 4A, and the upper surface of the copper wiring 22 embedded and exposed in the groove of the interlayer insulating layer 13 is formed to have a larger area.
That is, the width of the upper surface shown in FIG. 5 is formed larger than the width of the upper surface of the copper wiring shown in FIG.

Next, as shown in FIG. 5B, a copper diffusion prevention film 14 made of, for example, a P-SiN film having a thickness of several tens of nm is formed on the interlayer insulating layer 13 in which the copper wiring 22 is embedded in the trench. .
Next, as shown in FIG. 5C, a lower electrode film 17, a dielectric film 18, and an upper electrode film 19 are sequentially deposited on the interlayer insulating layer 13 by sputtering or the like.
Here, TiN or TaN can be used as the material of the upper electrode, Ta ₂ O ₅ can be used as the material of the dielectric film, and TiN, TaN / Ta / TaN, or the like can be used as the material of the lower electrode.

Next, as shown in FIG. 5D, the upper electrode film 19 formed in the uppermost layer is patterned into a predetermined shape by a known lithography and etching process to form the upper electrode 29 of the MIM capacitor element.
Next, as shown in FIG. 6E, a resist mask is formed on the lower electrode film 17 and the dielectric film 18 formed between the upper electrode 29 and the copper diffusion prevention film 14 by using well-known lithography, and RIE is performed. The lower electrode 27 and the dielectric film 28 of the MIM capacitor element are formed by selective etching using a dry etching method such as the above.

  Next, as shown in FIG. 6F, after forming the interlayer insulating film 15 of, for example, a P-TEOS film having a thickness of several hundred nm, the dielectric film 28 and the interlayer insulating film 15 are exposed so that the lower electrode 27 is exposed. A part of the interlayer insulating film 15 is removed so that the upper electrode 29 is exposed while part of the interlayer insulating film 15 is exposed. That is, a resist mask is formed on the interlayer insulating film 15 using normal lithography, and the dielectric film 28 and the interlayer insulating film 15 are selectively etched on the lower electrode 27 by using a dry etching method such as RIE, By selectively etching the interlayer insulating film 15 on the electrode 29, contact holes 30 and 30 are formed, and the resist mask is removed.

  Finally, as shown in FIG. 6G, the contact holes 30 and 30 shown in FIG. 6F are filled with aluminum by sputtering or the like from above and a film is formed on the entire surface of the wafer, and then directly above the copper wiring 22 using ordinary lithography. A wiring pattern made of an aluminum film having a predetermined shape is formed on the substrate. Then, an overcoat film 10 is formed on the entire surface of the wafer from above. If necessary, a bonding pad (not shown) may be formed by exposing the aluminum film using ordinary lithography.

However, the structure in which the MIM capacitor element is disposed immediately above the copper wiring 22 in the examples of FIGS. 5 and 6 has a disadvantage that the leakage current is large and cannot be used.
FIG. 7 shows a semiconductor wafer on which a large number of semiconductor chips each having the MIM capacitance element having the cross-sectional structure shown in FIG. 6G are formed. The leakage current (A) between the copper wiring 22 and the lower electrode 27 was measured, and the result of evaluating the insulating properties of each chip is shown. FIG. 7 shows that there are a plurality of semiconductor chips having poor insulation (large leakage current) on the semiconductor wafer.
The applicant of the present application explained that the cause of the occurrence of a plurality of defective chips on the same wafer is that when the copper wiring 22 is formed in the groove of the interlayer insulating layer 13 by CMP, the interlayer insulating layer 13 and the copper wiring 22 are formed. It was found that there is a step inevitably formed on the upper boundary of the surface.

The step inevitably formed at the upper boundary between the interlayer insulating layer 13 and the copper wiring 22 by the CMP method will be described with reference to FIGS. 6G, 8 and 9.
Here, FIG. 8 shows a simplified MIM capacitive element composed of a lower electrode 27, a dielectric film 28, and an upper electrode 29 disposed on the copper diffusion prevention film 14 above the copper wiring 22 having the sectional structure shown in FIG. 6G. FIG. 9 is an enlarged cross-sectional view showing a boundary region between the interlayer insulating layer 13 and the copper wiring 22 indicated by a broken-line circle in FIG.
That is, as described above, the copper wiring 22 has a groove formed in the interlayer insulating layer 13 and then copper is deposited on the entire surface by plating, and excess copper is removed by CMP to leave the copper wiring 22 only in the groove. In this way, it is formed.
However, at the time of processing by the CMP method, as shown in FIG. 8, the copper wiring 22 having a large area is inevitably processed in the shape of a mortar deeper than the edge (this is the dishing in the processing by the CMP method). This is the phenomenon). Then, as shown in FIG. 8, the copper diffusion prevention film 14, the lower electrode 27, the dielectric film 28, and the upper electrode 29 are formed on the dished copper wiring 22 provided in the interlayer insulating layer 13.

  As shown in FIG. 9 in which the boundary between the interlayer insulating layer 13 and the chopped copper wiring 22 is enlarged, in the dishing phenomenon, not only the center of the copper wiring 22 becomes a mortar shape deeper than the edge but also a broken line in the figure. As shown by the circles, when viewed at the boundary with the interlayer insulating layer 13, the copper wiring 22 is deeply cut to form a step. And even if the copper diffusion prevention film 14 is formed on the chopped copper wiring 22 so as to cover this step, for example, P-SiN has insufficient coverage so that the generated film overhangs. The copper diffusion preventing film 14 is locally thinned, and this causes a defective chip having a large leakage current.

  Therefore, in order to reduce defective chips having a large leakage current as much as possible and improve the yield, the copper wiring layer 22 and the MIM capacitor element are formed at a distance as shown by an arrow in FIG. 10 to prevent copper diffusion accompanying the dishing phenomenon. It is necessary to have a structure that does not affect the insulating characteristics (leakage current) even if the step of the film 14 occurs.

  11 and 12 show a procedure for forming a semiconductor device having a structure in which the copper wiring layer 22 and the MIM capacitor element shown in FIG. 10 are separated from each other.

First, as shown in FIG. 11A, a semiconductor wafer on which desired copper wiring is formed is manufactured. Here, the semiconductor wafer is formed so that the upper surface of the copper wiring 22 embedded in the groove of the interlayer insulating layer 13 is exposed by the same process as in the example of FIG. 4A.
Next, as shown in FIG. 11B, a copper diffusion prevention film 14 made of a P-SiN film having a thickness of, for example, several tens of nm is formed on the interlayer insulating layer 13 in which the copper wiring 22 is embedded in the trench. .

Next, as shown in FIG. 11C, a lower electrode film 17, a dielectric film 18, and an upper electrode film 19 are sequentially deposited on the interlayer insulating layer 13 by sputtering or the like.
Next, as shown in FIG. 11D, the upper electrode film 19 formed in the uppermost layer is patterned into a predetermined shape by using well-known lithography to form the upper electrode 29 of the MIM capacitor element. At this time, the region of the MIM capacitor element, that is, the region of the upper electrode 29 and the region of the copper wiring 22 are formed so as not to overlap when viewed from above.

Next, as shown in FIG. 12E, a resist mask is formed on the lower electrode film 17 and the dielectric film 18 formed between the upper electrode film 19 and the copper diffusion prevention film 14 by using well-known lithography. The lower electrode 27 and the dielectric film 28 of the MIM capacitor element are formed by selective etching using a dry etching method such as RIE.
Next, as shown in FIG. 12F, after forming the interlayer insulating film 15 of, for example, a P-TEOS film having a thickness of several hundred nm, the dielectric film 28 and the interlayer insulating film 15 are exposed so that the lower electrode 27 is exposed. A part of the interlayer insulating film 15 is removed so that the upper electrode 29 is exposed while part of the interlayer insulating film 15 is exposed. Further, the copper diffusion preventing film 14 and a part of the interlayer insulating film 15 are removed on the right end side of the copper wiring 22 shown in FIG. 12F so that the copper wiring 22 is exposed.
That is, a resist mask is formed on the interlayer insulating film 15 using ordinary lithography, and a dry diffusion method such as RIE is used to form the copper diffusion prevention film 14 on the copper wiring 22, the interlayer insulating film 15 thereon, and the lower part. By selectively etching the dielectric film 28 and the interlayer insulating film 15 on the electrode 27 and the interlayer insulating film 15 on the upper electrode 29, contact holes 30, 30, and 30 are formed, and the resist mask is removed.

  Finally, as shown in FIG. 12G, the contact holes 30, 30, and 30 shown in FIG. 12F are filled with aluminum by sputtering or the like from above and a film is formed on the entire surface of the wafer. A pattern of an aluminum film having a predetermined shape is formed immediately above 22 and an overcoat film 10 is formed on the entire surface of the wafer from above, and then only a predetermined portion of the pattern of the aluminum film is exposed using normal lithography, A wiring portion made of aluminum connected to the bonding pad 31 made of an aluminum film and the upper and lower electrodes 29 and 27 of the MIM capacitor element is formed.

  However, in such a structure in which the copper wiring 22 and the MIM capacitor element as shown in FIGS. 10 and 12 are arranged apart from each other, the degree of integration of the chips cannot be increased, so that the number of chips formed on the wafer is small. As a result, there was an inconvenience that the unit price of chips increased.

In order to improve this, in the structure of the example of FIG. 10, an additional interlayer film 16 is formed on the copper wiring layer 22 as shown in FIG. 13 and insulated at the step portion of the copper diffusion prevention film 14 due to the dishing phenomenon. There is a method in which the structure (leakage current) is not affected.
An example of a semiconductor device having a conventionally known copper wiring and having an MIM capacitor element is disclosed in Patent Document 1.
Japanese Unexamined Patent Publication No. 2004-79924 (pages 2, 3 and 4)

However, when the additional interlayer film 16 is formed on the copper diffusion preventing film 14 on the copper wiring layer 22 as shown in FIG.
FIG. 13 shows a state in which an interlayer film 16 is additionally formed in FIG. 11B of the manufacturing procedure of the example of FIGS. 11 and 12 and processed in the same manner to form an MIM capacitor element and then an overcoat film 10 is provided. 14 shows a state in which, after the cross-sectional structure of FIG. 13 is formed, a resist mask is formed using lithography, and contact holes 30 and 30 for conduction are formed by dry etching such as RIE.

As shown in FIG. 13, the interlayer insulating film 15 is formed on the entire wafer by a CVD method or the like, and is not flattened. In this state, the thickness t1 of the copper diffusion prevention film 14, the thickness t2 of the additional interlayer film 16, and the thickness T of the interlayer insulating film 15 are T + t1 + t2, and the film thickness formed on the copper wiring 22 is MIM. The film formed on the upper electrode 29 of the capacitor element is only the interlayer insulating film 15 and the film thickness is T.
For this reason, as shown in FIG. 14, when a contact hole 30 for conducting with the copper wiring 22 is formed, if an attempt is made to simultaneously form a contact hole on the MIM capacitor element, the etching time on the MIM capacitor element is increased. Becomes over-etched for a long time and breaks through the upper electrode of the MIM capacitor element, so that sufficient conduction cannot be ensured. That is, even if the interlayer film 16 is added, the upper electrode 29 of the MIM capacitor element in which the film thickness of the interlayer insulating film 15 immediately above remains T remains excessively etched, and there is a risk of electrode penetration. is there.

The problem of electrode penetration due to the addition of the interlayer film 16 can also occur when the copper diffusion prevention film 14 itself is formed thick as shown in FIG. FIG. 16 shows a state in which an aluminum wiring is formed on the semiconductor element having the cross-sectional structure of FIG. 15 by sputtering or the like, and a bonding pad 31 is provided on the copper wiring 22.
In this way, a step is inevitably formed at the boundary between the copper wiring 22 and the interlayer insulating layer 13 in which the copper wiring 22 is buried by the dishing associated with the CMP method performed when the copper wiring 22 is formed. Therefore, the copper diffusion prevention film 14 formed thereon has a locally thin film thickness, which causes an insulation failure, and the MIM capacitor element cannot be disposed at the boundary between the copper wiring 22 and the interlayer insulating layer 13, The area of the semiconductor chip could not be reduced.

  In view of the above, the present invention is a semiconductor device having a copper wiring and a bonding pad made of aluminum and having an MIM capacitor element, which can improve a leakage current caused by dishing and reduce a chip area. A method for manufacturing a device is proposed.

  In order to solve the above problems, the semiconductor device of the present invention has a copper wiring embedded in an interlayer insulating film layer having a substantially constant upper surface height, and the upper surface of the copper wiring is at the boundary between the copper wiring and the interlayer insulating film layer. In a semiconductor device that is recessed with respect to the upper surface of the interlayer insulating film layer and in which a capacitor element is formed above the interlayer insulating film layer, a copper diffusion prevention film is provided on the upper surface of the interlayer insulating film layer and the copper wiring, and this copper diffusion An additional interlayer film is formed on one side and above the copper wiring region on the upper surface of the prevention film, and the capacitor element is provided with a lower electrode film provided on the upper surface of the additional interlayer film and a dielectric provided on the upper surface of the lower electrode film. A film and an upper electrode film provided on the upper surface of the dielectric film are formed.

  According to the present invention, in the semiconductor device described above, the capacitive element is an MIM capacitive element in which an upper electrode film and a lower electrode film are formed of a metal material.

  According to the present invention, in the semiconductor device described above, the bonding pad is formed of aluminum.

  According to the present invention, in the semiconductor device described above, the copper diffusion prevention film is formed by plasma CVD.

  Further, according to the present invention, in the semiconductor device described above, the copper diffusion preventing film is a silicon nitride film.

  According to the present invention, in the semiconductor device described above, the copper diffusion prevention film is a silicon carbide film.

  According to the present invention, in the semiconductor device described above, the additional interlayer film is formed of a material that is selectively etched with the copper diffusion prevention film during the reactive ion etching process.

  Further, according to the present invention, in the semiconductor device described above, the additional interlayer film is a silicon oxide film generated by tetraethoxy silane by plasma CVD.

  According to the semiconductor device configured as described above, an additional interlayer film is additionally formed on the copper diffusion prevention film on the copper wiring, and the additional interlayer film is selectively used when the copper diffusion prevention film and dry etching are performed by the RIE method. Therefore, the additional interlayer film is formed in substantially the same pattern as the lower electrode of the MIM capacitor element, and the additional interlayer film is left only directly under the MIM capacitor element, thereby suppressing the occurrence of leakage current. At the same time, the copper diffusion prevention film itself is left, and after forming the interlayer insulating film, a contact hole is formed without causing a penetration in the upper electrode of the MIM capacitor element, and a contact hole is formed on the upper side of the copper wiring, Further, a bonding pad made of, for example, aluminum connected to the copper wiring can be formed.

  In order to solve the above problems, a method of manufacturing a semiconductor device of the present invention has a copper wiring embedded in an interlayer insulating film layer having a substantially constant upper surface height, and a copper is formed at the boundary between the copper wiring and the interlayer insulating film layer. In a method of manufacturing a semiconductor device in which the upper surface of the wiring is recessed with respect to the upper surface of the interlayer insulating film layer and the capacitor element is formed on the upper layer of the interlayer insulating film layer, copper diffusion prevention is performed on the upper surface of the interlayer insulating film layer and the copper wiring. A step of providing a film, a step of sequentially providing an additional interlayer film, a lower electrode film, a dielectric film, and an upper electrode film above the copper diffusion prevention film, and the upper electrode film on one end side in the region of the copper wiring and Etching so as to be substantially opposite to the one end side above to form an upper electrode, and etching the dielectric film and the lower electrode film together to form a dielectric film and a lower electrode corresponding to the upper electrode film; The additional interlayer film is selectively etched to A step of forming an additional interlayer film having substantially the same shape as the lower electrode, a step of forming an interlayer insulating film, and the other end side in the copper wiring region. Forming a contact hole in the copper diffusion preventing film, the interlayer insulating film, the interlayer insulating film disposed on the upper electrode, the dielectric film disposed on the lower electrode, and the interlayer insulating film; And a pattern forming step of embedding a metal material and a step of exposing a bonding pad connected to a copper wiring after forming an overcoat film.

  According to the present invention, in the semiconductor device manufacturing method described above, the capacitive element is an MIM capacitive element in which an upper electrode film and a lower electrode film are formed of a metal material.

  According to the present invention, the bonding pad is formed of aluminum in the method for manufacturing a semiconductor device described above.

  According to the present invention, in the method for manufacturing a semiconductor device described above, the copper diffusion prevention film is a silicon nitride film generated by plasma CVD.

  According to the present invention, in the method for manufacturing a semiconductor device described above, the copper diffusion prevention film is formed by plasma CVD.

  According to the present invention, in the method for manufacturing a semiconductor device described above, the copper diffusion preventing film is a silicon nitride film.

  According to the present invention, in the method for manufacturing a semiconductor device described above, the copper diffusion prevention film is a silicon carbide film.

  According to the present invention, in the semiconductor device manufacturing method described above, the additional interlayer film is formed of a material that is selectively etched with the copper diffusion prevention film during the reactive ion etching process. is there.

  Further, according to the present invention, in the method for manufacturing a semiconductor device described above, the additional interlayer film is a silicon oxide film generated by tetraethoxy silane by plasma CVD.

  According to the method of manufacturing a semiconductor device configured as described above, an additional interlayer film is additionally formed on the copper diffusion prevention film on the copper wiring, and the additional interlayer film is formed when the copper diffusion prevention film and dry etching are performed by the RIE method. Therefore, the additional interlayer film is formed in substantially the same pattern as the lower electrode of the MIM capacitor element so that the additional interlayer film is left only directly under the MIM capacitor element, and leakage current is generated. The copper diffusion prevention film itself remains, and after the formation of the interlayer insulating film, a contact hole is formed in the upper electrode of the MIM capacitor element without causing penetration, and the contact hole is formed above the copper wiring. Further, for example, a bonding pad made of aluminum can be formed.

  According to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, the leakage current between the lower electrode of the MIM capacitor element and the copper wiring can be suppressed to reduce the number of chips that cause insulation failure on the wafer and to improve the yield. In addition, since the copper wiring and the MIM capacitor element can be arranged so as to overlap each other, the yield of chips per wafer can be increased.

Hereinafter, an example of the best mode for carrying out the present invention will be described with reference to FIGS.
In the semiconductor device of this example, an additional interlayer film is formed only under the MIM capacitor element on the copper diffusion prevention film, and the copper wiring region is also disposed below the MIM capacitor element. .
In the following description, FIGS. 1 to 3 will be described by assigning the same reference numerals to the portions corresponding to FIGS. 4 to 16.

FIG. 1 shows a cross-sectional structure of the semiconductor device of this example, in which an additional interlayer film 26 is formed on the copper diffusion prevention film 14 only under the MIM capacitor element composed of the lower electrode 27, the dielectric film 28 and the upper electrode 29. The region of the copper wiring 22 is arranged under this MIM capacitor element.
Hereinafter, the manufacturing procedure of FIG. 1 will be described in order with reference to FIGS.

First, as shown in FIG. 2A, a semiconductor wafer in which a copper diffusion prevention film 14 is formed on a desired copper wiring 22 is manufactured.
The cross-sectional structure shown in FIG. 2A is obtained by forming a semiconductor element or the like on a semiconductor wafer (hereinafter referred to as a wafer) by a well-known semiconductor manufacturing process, and then forming, for example, P-TEOS (tetra ethoxy. A silicon oxide film using silane) is formed, and a groove is formed in the interlayer insulating layer 13 by well-known photolithography and dry etching. Then, a TaN film or a TiN film (not shown) to be a copper diffusion preventing film is formed by sputtering, and then copper plating is performed on the entire surface of the semiconductor wafer to fill the groove, and then the excess copper on the interlayer insulating layer 13 and By removing the barrier film by polishing using the CMP method, a wide copper wiring 22 is embedded in the trench.
Then, a P-SiN film having a thickness of, for example, several tens of nanometers serving as a copper diffusion prevention film 14 is formed on the polished surface by the CMP method, that is, on the interlayer insulating layer 13 in which the copper wiring 22 is embedded in the groove. A film is formed by a CVD method. The copper diffusion preventing film 14 is not limited to the SiN film, but may be any other film as long as diffusion can be prevented, for example, a SiC film.

Next, as shown in FIG. 2B, after an additional interlayer film 16 of about 10 nm is formed by a P-TEOS film, a lower electrode film 17, a dielectric film 18, and an upper electrode film 19 are formed on the interlayer film 16 by sputtering or the like. Are sequentially deposited.
Here, the interlayer film 16 may be a film other than the P-TEOS film as long as it is a film material that can have a high etching selectivity in dry etching with the copper diffusion preventing film 14. Further, as the material of the upper electrode, TiN, TaN, TiN / Ti / Al, and those obtained by stacking these films can be used. Moreover, as a material of the dielectric film, SiO ₂ , Ta ₂ O ₅ , SiN, HfO ₂ , Al ₂ O _3, and a laminate of these films can be used. Further, as the material of the lower electrode, TiN, TaN / Ta / TaN, TiN / Ti, and a laminate of these films can be used.

  Next, as shown in FIG. 2C, the upper electrode film 19 formed in the uppermost layer is patterned into a predetermined shape using well-known lithography to form the upper electrode 29 of the MIM capacitor element. At this time, the region of the MIM capacitor element and the region of the copper wiring 22 on the left side shown in FIG.

Next, as shown in FIG. 2D, an additional interlayer film 16, a lower electrode film 17, and a dielectric film 18 formed between the upper electrode film 19 and the copper diffusion prevention film 14 are formed by using well-known lithography. A resist mask is formed and selectively etched using a dry etching method such as RIE to form a lower electrode 27 and a dielectric film 28 of the MIM capacitor element.
At this time, after forming a resist mask on the upper electrode 29 and the dielectric film 18, first, a pattern of the lower electrode 27 and the dielectric film 28 of the MIM capacitor is used as a processing gas, for example, and chlorine gas (Cl ₂ ) is 70 sccm (Standard cc). per minute), boron trichloride gas (BCl ₃ ) is etched at 20 sccm, and argon gas (Ar) as a carrier gas is etched at 40 sccm. Then, during this etching process, the processing gas components are switched to, for example, 8 sccm for C ₄ F ₈ gas, 60 sccm for carbon monoxide gas (CO), and 200 sccm for argon gas (Ar) as a carrier gas. Then, the P-TEOS film is dry-etched while ensuring the selection ratio with the underlying copper diffusion prevention film 14 of P-SiN or the like.

As a result, as shown in FIG. 2D, the interlayer film 16 forms the interlayer film 26 left between the lower electrode 27 and the copper diffusion prevention film 14, and the MIM capacitor element is formed on the interlayer film 26. The copper diffusion prevention film 14 is exposed.
Therefore, on the lower side of the interlayer film 26, the copper diffusion preventing film 14 is doubled with the copper diffusion preventing film 14, and the leakage current is suppressed even if there is a step at the boundary between the copper wiring 22 and the interlayer insulating layer 13. The film thickness is sufficient.

  Next, as shown in FIG. 3E, an interlayer insulating film 15 made of a P-TEOS film having a thickness of, for example, several hundred nm is formed.

Next, as shown in FIG. 3F, a part of the dielectric film 28 and the interlayer insulating film 15 is removed so that the lower electrode 27 is exposed from above, and one part of the interlayer insulating film 15 is exposed so that the upper electrode 29 is exposed. Remove the part. 3F, the copper diffusion preventing film 14 and a part of the interlayer insulating film 15 are removed so that the copper wiring 22 is exposed from above at the copper wiring 22 on the right end side shown in FIG. 3F. That is, a resist mask is formed on the interlayer insulating film 15 using ordinary lithography, and a dry diffusion method such as RIE is used to form the copper diffusion prevention film 14 on the copper wiring 22, the interlayer insulating film 15 thereon, and the lower part. By selectively etching the dielectric film 28 and the interlayer insulating film 15 on the electrode 27 and the interlayer insulating film 15 on the upper electrode 29, contact holes 30, 30, and 30 are formed, and the resist mask is removed.
In the step of forming the contact hole shown in FIG. 3F, a non-conductive film such as the copper diffusion prevention film 14, the interlayer insulating film 15 and the dielectric film 28, the copper wiring 22, and the lower electrode 27 are formed in a dry etching process such as RIE. Further, since the etching selectivity can be increased with the conductive film such as the upper electrode 29, the upper electrode 29 is not penetrated.

  Finally, as shown in FIG. 3G, the contact holes 30, 30, and 30 shown in FIG. 3F are filled with aluminum and formed on the entire surface of the wafer by sputtering or the like from above, and then the copper wiring is formed using ordinary lithography. A pattern of an aluminum film having a predetermined shape is formed immediately above 22 and an overcoat film 10 is formed on the entire surface of the wafer from above, and then only a predetermined portion of the pattern of the aluminum film is exposed using normal lithography, A bonding pad 31 made of an aluminum film is formed, and a wiring portion made of aluminum connected to the upper and lower electrodes 29 and 27 of the MIM capacitor element on the left copper wiring 22 shown in FIG. 3G is formed.

  That is, in the semiconductor device shown in FIGS. 1 and 2, when the contact hole 30 is formed, not only does not penetrate through the upper electrode 29 of the MIM capacitor element, but also an interlayer film in which a leakage current is added to the copper diffusion prevention film 14. 26, the MIM capacitor element can be arranged without having to consider the position of the copper wiring 22 immediately below.

  In addition, according to the method of manufacturing the semiconductor device of FIGS. 1 and 2, an interlayer film 16 is additionally formed on the copper diffusion prevention film 14 on the copper wiring 22, and the interlayer film 16 is formed of the copper diffusion prevention film 14. Therefore, the interlayer film 16 is left only in substantially the same pattern under the lower electrode 27 of the MIM capacitor element, and the copper diffusion prevention film 14 itself is entirely formed. In addition to suppressing the occurrence of leakage current, the contact hole 30 can be formed without causing a penetration in the upper electrode 29 of the MIM capacitor element after the formation of the interlayer insulating film 15. Further, the contact hole 30 can be formed on the upper side of the copper wiring 22 on the right side shown in FIG. 2, and the bonding pad 31 made of aluminum can be further formed.

  According to the semiconductor device and the manufacturing method of the semiconductor device of this example, the leakage current between the lower electrode 27 of the MIM capacitor element and the copper wiring 22 is suppressed, and the number of chips that cause an insulation failure on the wafer is reduced and the yield is improved. In addition, since the copper wiring 22 and the MIM capacitor element can be arranged so as to overlap with each other, the chip can be downsized and the yield per wafer can be increased.

Although the example of the P-TEOS film has been described as the interlayer insulating layers 13 and 15, the present invention is not limited to this, and any other insulating material having a low dielectric constant may be used. For example, SiO _{2 formed} at a low temperature, SiOF (silicon oxide with fluorine added) or SiOC (silicon oxide with carbon added) may be used.

  Of course, the semiconductor device and the method for manufacturing the semiconductor device of the present invention are not limited to the above-described examples, and various other configurations can be adopted without departing from the gist of the present invention.

It is a sectional view showing the structure of the semiconductor device of the present invention. FIG. 5 is a diagram for explaining a manufacturing procedure until forming a bonding pad made of an aluminum film, showing a method for manufacturing a semiconductor device of the present invention, where A is a copper diffusion prevention film and B is an additional interlayer film for an MIM capacitor element; After forming the electrode film and the dielectric film, C is a cross-sectional structure diagram after forming the upper electrode, and D is a sectional structure after forming the dielectric film for the MIM capacitor element, the lower electrode, and the additional interlayer film. FIG. 3 is a diagram for explaining a manufacturing procedure subsequent to FIG. 2, wherein E is a cross-sectional structure diagram after forming an interlayer insulating film, F after forming a contact hole, and G forming a bonding pad and providing an overcoat. It is a figure explaining the manufacturing procedure which forms an aluminum film in a bonding pad by the semiconductor manufacturing process which has the conventional copper wiring, A after copper wiring formation, B after copper diffusion prevention film formation, and C after interlayer insulation film formation , D is a cross-sectional structure diagram after contact hole formation, E is after bonding pad formation, and F is after overcoat formation. It is a figure explaining the manufacturing procedure which forms a MIM capacitor | condenser in the process of forming an aluminum film in a bonding pad by the semiconductor manufacturing process which has the conventional copper wiring, A is after copper wiring formation, B is after copper diffusion prevention film formation , C are cross-sectional structure diagrams after forming upper and lower electrode films and dielectric films for the MIM capacitor element, and D is an upper electrode formation. FIG. 6 is a diagram for explaining the manufacturing procedure following FIG. 5, where E is after forming the dielectric film for the MIM capacitor and the lower electrode, F is after the interlayer insulating film is formed and after the contact hole is formed, and G is the bonding pad formed and over It is sectional structure drawing which provided the coat. FIG. 5 is an explanatory diagram illustrating an example of excessive leakage current generation in an in-wafer chip in the example of FIG. 4. FIG. 5 is a cross-sectional view showing a simplified MIM structure portion of the example of FIG. 4 in order to explain the cause of excessive leakage current generation of the example of FIG. 4. FIG. 5 is an enlarged cross-sectional view illustrating a boundary between a copper wiring and an interlayer insulating layer after the formation of a copper diffusion prevention film in order to explain the cause of excessive leakage current generation in the example of FIG. It is explanatory sectional drawing which shows the structure which provided the MIM capacitive element apart in the conventional semiconductor device which has a copper wiring. FIG. 11 is a diagram for explaining a manufacturing procedure until an aluminum film bonding pad is formed in the semiconductor device of FIG. 10, where A is a copper wiring formation, B is a copper diffusion prevention film formation, and C is a top and bottom for MIM capacitor elements. After forming the electrode film and the dielectric film, D is a cross-sectional structure diagram after forming the upper electrode. FIG. 12 is a diagram for explaining a manufacturing procedure following FIG. 11, where E is after forming the dielectric film for the MIM capacitor and the lower electrode, F is after forming the interlayer insulating film and after forming the contact hole, and G is after forming the bonding pad. It is a cross-sectional structure diagram provided with an overcoat. It is explanatory sectional drawing which shows the structure which provided the MIM capacitive element apart after forming a copper diffusion prevention film and an additional interlayer film in the conventional semiconductor device having copper wiring. It is explanatory drawing of the malfunction of the upper electrode penetration in the example of FIG. It is explanatory drawing of the malfunction of an upper electrode penetration in the structure which formed the copper diffusion prevention film thickly with the conventional semiconductor device which has a copper wiring, and provided the MIM capacitive element apart. FIG. 16 is a cross-sectional structure diagram when bonding pads are formed in the example of FIG. 15.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 13 ... Interlayer insulation layer, 14 ... Copper diffusion prevention film, 15 ... Interlayer insulation film, 22 ... Copper wiring, 26 ... Added interlayer film, 27 ... Lower electrode, 28 ... Dielectric film, 29 ... Upper electrode

Claims (16)

A copper wiring embedded in an interlayer insulating film layer having a substantially constant upper surface height, the upper surface of the copper wiring being at the boundary between the copper wiring and the interlayer insulating film layer with respect to the upper surface of the interlayer insulating film layer; In the semiconductor device in which the capacitor element is formed in the upper layer of the interlayer insulating film layer that is recessed,
A copper diffusion prevention film is provided on the upper surface of the interlayer insulating film layer and the copper wiring,
Forming an additional interlayer film on one side and above the copper wiring region on the upper surface of the copper diffusion preventing film;
The capacitive element;
A lower electrode film provided on the upper surface of the additional interlayer film;
A dielectric film provided on the upper surface of the lower electrode film;
A semiconductor device comprising: an upper electrode film provided on an upper surface of the dielectric film. The semiconductor device according to claim 1,
A semiconductor device, wherein the capacitor element is an MIM capacitor element in which the upper electrode film and the lower electrode film are formed of a metal material. The semiconductor device according to claim 1,
A semiconductor device, wherein the bonding pad is made of aluminum. The semiconductor device according to claim 1,
A semiconductor device, wherein the copper diffusion prevention film is formed by plasma CVD. The semiconductor device according to claim 4.
A semiconductor device characterized in that the copper diffusion preventing film is a silicon nitride film. The semiconductor device according to claim 4.
A semiconductor device, wherein the copper diffusion preventing film is a silicon carbide film. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the additional interlayer film is formed of a material that can be selectively etched between the additional diffusion film and the copper diffusion prevention film during the reactive ion etching process. The semiconductor device according to claim 7.
A semiconductor device characterized in that the additional interlayer film is a silicon oxide film generated by tetra-ethoxy-silane by plasma CVD. A copper wiring embedded in an interlayer insulating film layer having a substantially constant upper surface height, the upper surface of the copper wiring being at the boundary between the copper wiring and the interlayer insulating film layer with respect to the upper surface of the interlayer insulating film layer; In the manufacturing method of the semiconductor device in which the capacitor element is formed in the upper layer of the interlayer insulating film layer that is recessed,
Providing a copper diffusion prevention film on the upper surface of the interlayer insulating film layer and the copper wiring;
A step of sequentially providing an additional interlayer film, a lower electrode film, a dielectric film, and an upper electrode film on the copper diffusion prevention film;
Etching the upper electrode film so as to be substantially opposite to the one end side in the copper wiring region at one end side, and forming an upper electrode;
Etching the dielectric film and the lower electrode film together to form the dielectric film and the lower electrode corresponding to the upper electrode film;
Selectively etching the additional interlayer film, and forming the additional interlayer film having substantially the same shape as the lower electrode between the lower electrode and the copper diffusion prevention film;
Forming an interlayer insulating film;
The copper diffusion prevention film and the interlayer insulating film disposed on the other end side in the copper wiring region, the interlayer insulating film disposed on the upper electrode, and the lower electrode. Forming a contact hole in the dielectric film and the interlayer insulating film,
Embedding a metal material in the contact hole and forming a pattern;
And a step of exposing a bonding pad connected to the copper wiring after forming an overcoat film. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the capacitive element is an MIM capacitive element in which the upper electrode film and the lower electrode film are formed of a metal material. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the bonding pad is made of aluminum. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the copper diffusion prevention film is formed by plasma CVD. In the manufacturing method of the semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein the copper diffusion prevention film is a silicon nitride film. In the manufacturing method of the semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein the copper diffusion preventing film is a silicon carbide film. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the additional interlayer film is formed of a material that is selectively etched with the copper diffusion prevention film during a reactive ion etching process. In the manufacturing method of the semiconductor device according to claim 15,
A method of manufacturing a semiconductor device, wherein the additional interlayer film is a silicon oxide film generated by tetra-ethoxy-silane by plasma CVD.

Images