KR20040002012A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR20040002012A KR20040002012A KR1020020037349A KR20020037349A KR20040002012A KR 20040002012 A KR20040002012 A KR 20040002012A KR 1020020037349 A KR1020020037349 A KR 1020020037349A KR 20020037349 A KR20020037349 A KR 20020037349A KR 20040002012 A KR20040002012 A KR 20040002012A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 융점이 높으면서 다른 물질과 잘 반응하지 않아 내산화성 및 내부식성이 우수한 루테늄(Ru)을 금속배선 재료로 사용하여 소자의 고집적화 및 고기능화를 실현할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, ruthenium (Ru), which has a high melting point and does not react well with other materials, has excellent oxidation resistance and corrosion resistance, thereby achieving high integration and high functionalization of the device. The present invention relates to a metal wiring forming method of a semiconductor device.
일반적으로, 반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속배선을 형성함에 있어서 구리는 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 반도체 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 널리 사용되고 있다.In general, as the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of devices continues to shrink into the sub-half-micron area, while improving performance and reliability. In terms of circuit density, circuit density is increasing. In response to these demands, copper has a higher melting point than aluminum in forming metal wirings of semiconductor devices, and thus has high resistance to electro-migration (EM), thereby improving reliability of semiconductor devices. Low signal transmission speeds are widely used as interconnect materials useful for integration circuits.
그러나, 구리 배선은 실리콘 또는 실리콘 산화막 내로 구리 원자가 쉽게 침투하여 들어가 소자의 전기적 특성 및 절연 특성을 악화시키는 문제점이 있으며, 산소와 쉽게 반응하여 구리 산화물을 형성하는 등의 내산화성 및 내부식성이 매우 취약하다. 또한, 구리 증착 방법으로 연구되고 있는 금속유기 화학기상증착(MOCVD) 방법은 양산 공정에 적용될 만큼 안정된 공정을 보이지 않고 있으며, 기존의 플라즈마 방법으로 식각시 낮은 증기압으로 인해 식각 공정 진행상 난제가 많다. 이러한 난제로 인하여 보다 성능이 우수하고 고집적화된 소자를 실현하는데 어려움이 따른다.However, copper wiring has a problem in that copper atoms easily penetrate into the silicon or silicon oxide film to deteriorate the electrical and insulating properties of the device, and are very weak in oxidation resistance and corrosion resistance such as easily reacting with oxygen to form copper oxide. Do. In addition, the metal organic chemical vapor deposition (MOCVD) method, which is being studied by the copper deposition method, does not show a stable process to be applied to the mass production process, and there are many difficulties in the progress of the etching process due to the low vapor pressure during etching with the conventional plasma method. These challenges make it difficult to realize better and more integrated devices.
따라서, 본 발명은 구리보다 융점이 높으면서 다른 물질과 잘 반응하지 않아 내산화성 및 내부식성이 우수한 루테늄(Ru)을 금속배선 재료로 사용하여 소자의 고집적화 및 고기능화를 실현할 수 있는 반도체 소자의 금속배선 형성방법은 제공함에 그 목적이 있다.Therefore, the present invention uses a ruthenium (Ru) as a metal wiring material that has a higher melting point than copper and does not react well with other materials, thereby forming metal wirings of semiconductor devices that can realize high integration and high functionalization of devices. Its purpose is to provide a method.
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법은 상부에 메탈 콘택 스톱 질화막을 갖는 하부 도전층이 형성된 반도체 기판이 제공되는 단계; 상기 하부 도전층을 포함한 전체 구조상에 층간 절연막, 메탈 스톱 질화막 및 패시베이션 산화막을 순차적으로 형성하는 단계; 콘택홀 및 트렌치로 이루어진 다마신 패턴을 형성하는 단계; 상기 다마신 패턴을 포함한 상기 패시베이션 산화막의 표면을 따라 루테늄 옥사이드층을 형성하는 단계; 상기 루테늄 옥사이드층이 형성된 다마신 패턴이 충분히 매립되도록 루테늄층을 형성하는 단계; 및 상기 패시베이션 산화막의 상단 표면이 노출될 때까지 상기 루테늄층 및 상기 루테늄 옥사이드층을 식각하고, 이로 인하여 루테늄 배선이 상기 다마신 패턴 내에 형성되는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: providing a semiconductor substrate having a lower conductive layer having a metal contact stop nitride film formed thereon; Sequentially forming an interlayer insulating film, a metal stop nitride film, and a passivation oxide film on the entire structure including the lower conductive layer; Forming a damascene pattern consisting of a contact hole and a trench; Forming a ruthenium oxide layer along a surface of the passivation oxide film including the damascene pattern; Forming a ruthenium layer to sufficiently fill the damascene pattern in which the ruthenium oxide layer is formed; And etching the ruthenium layer and the ruthenium oxide layer until the top surface of the passivation oxide film is exposed, thereby ruthenium wiring is formed in the damascene pattern.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판12: 하부 도전층11: semiconductor substrate 12: lower conductive layer
13: 메탈 콘택 스톱 질화막14: 층간 절연막13: metal contact stop nitride film 14: interlayer insulating film
15: 메탈 스톱 질화막16: 패시베이션 산화막15: metal stop nitride film 16: passivation oxide film
17: 제 1 포토레지스트 패턴18: 콘택홀17: first photoresist pattern 18: contact hole
19: 제 2 포토레지스트 패턴20: 트렌치19: second photoresist pattern 20: trench
21: 루테늄 옥사이드층22: 루테늄층21: ruthenium oxide layer 22: ruthenium layer
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.
도 1a 및 도 1f는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 소자의 단면도이다.1A and 1F are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 상부에 메탈 콘택 스톱 질화막(metal contact stop nitride film; 13)을 갖는 하부 도전층(12)이 형성된 반도체 기판(11)이 제공되고, 하부 도전층(12)을 포함한 전체 구조상에 층간 절연막(inter layer dielectric film; 14), 메탈 스톱 질화막(metal stop nitride film; 15) 및 패시베이션 산화막(passivation oxide film; 16)을 순차적으로 형성한다.Referring to FIG. 1A, a semiconductor substrate 11 having a lower conductive layer 12 having a metal contact stop nitride film 13 formed thereon is provided, and overall structure including the lower conductive layer 12 is provided. An interlayer dielectric film 14, a metal stop nitride film 15, and a passivation oxide film 16 are sequentially formed on the substrate.
상기에서, 하부 도전층(12)은 반도체 기판(11)에 형성된 확산층이나, 워드 라인, 비트 라인, 하부 금속 배선 등을 포함한다. 층간 절연막(14)은 산화물 계통의 절연물질을 사용하여 단층 또는 다층으로 형성할 수 있다. 예를 들어, 다층의 층간 절연막(14)은 SiON 계열의 산화물을 80 내지 120nm의 두께로 1차 증착하고, 1차 증착된 층 상에 SOD 계열의 산화물을 400 내지 600nm의 두께로 2차 증착하고, 2차 증착된 층 상에 SiON 계열의 산화물을 350 내지 500nm의 두께로 3차 증착하여 형성한다. 메탈 콘택 스톱 질화막(13) 및 메탈 스톱 질화막(15)은 질화물을 저압화학기상증착(LPCVD)법이나 플라즈마증가형 화학기상증착(PECVD)법으로 50 내지 120nm의 두께로 증착하여 형성한다. 패시베이션 산화막(16)은 고밀도 플라즈마 산화물(HDP oxide)을 900 내지 1100nm의 두께로 증착하여 형성한다.In the above, the lower conductive layer 12 includes a diffusion layer formed on the semiconductor substrate 11, a word line, a bit line, a lower metal wiring, or the like. The interlayer insulating layer 14 may be formed in a single layer or multiple layers using an oxide-based insulating material. For example, the multilayer interlayer insulating film 14 may first deposit SiON-based oxides having a thickness of 80 to 120 nm, and secondly deposit SOD-based oxides having a thickness of 400 to 600 nm on the first deposited layer. On the secondary deposited layer, a SiON-based oxide is formed by tertiary deposition to a thickness of 350 to 500 nm. The metal contact stop nitride film 13 and the metal stop nitride film 15 are formed by depositing nitride to a thickness of 50 to 120 nm by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The passivation oxide film 16 is formed by depositing a high density plasma oxide (HDP oxide) to a thickness of 900 to 1100 nm.
도 1b를 참조하면, 콘택홀이 형성될 영역이 개방(open)된 제 1 포토레지스트 패턴(17)을 패시베이션 산화막(16) 상에 형성한다.Referring to FIG. 1B, a first photoresist pattern 17 having a region where a contact hole is to be opened is formed on the passivation oxide layer 16.
상기에서, 제 1 포토레지스트 패턴(17)은 포토레지스트를 800 내지 900nm의 두께로 도포한 후 포토리소그라피(photo-lithography) 공정에 의해 형성한다. 제 1 포토레지스트 패턴(17)을 형성하기 전에 패시베이션 산화막(16) 상에 유기(organic) BARC층을 50 내지 70nm의 두께로 형성할 수도 있다.In the above, the first photoresist pattern 17 is formed by a photo-lithography process after applying the photoresist to a thickness of 800 to 900nm. Before forming the first photoresist pattern 17, an organic BARC layer may be formed on the passivation oxide layer 16 to a thickness of 50 to 70 nm.
도 1c를 참조하면, 제 1 포토레지스트 패턴(17)을 식각 마스크로 한 식각 공정으로 패시베이션 산화막(16), 메탈 스톱 질화막(15), 층간 절연막(14) 및 메탈 콘택 스톱 질화막(13)을 순차적으로 식각하여 하부 도전층(12)의 일부분이 노출되는 콘택홀(18)을 형성한다. 이후, 제 1 포토레지스트 패턴(17)을 제거한다.Referring to FIG. 1C, the passivation oxide film 16, the metal stop nitride film 15, the interlayer insulating film 14, and the metal contact stop nitride film 13 are sequentially formed by an etching process using the first photoresist pattern 17 as an etching mask. Etching to form a contact hole 18 through which a portion of the lower conductive layer 12 is exposed. Thereafter, the first photoresist pattern 17 is removed.
도 1d를 참조하면, 콘택홀(18)을 포함한 배선이 형성될 영역이 개방(open)된 제 2 포토레지스트 패턴(19)을 패시베이션 산화막(16) 상에 형성한다.Referring to FIG. 1D, a second photoresist pattern 19 is formed on the passivation oxide layer 16 in which a region including a contact hole 18 is to be opened.
상기에서, 제 2 포토레지스트 패턴(19)은 포토레지스트를 800 내지 900nm의 두께로 도포한 후 포토리소그라피(photo-lithography) 공정에 의해 형성하는데, 콘택홀(18) 내부는 깊이가 포토리소그라피 공정을 통해서도 제거되지 않고 남아있게 된다.In the above, the second photoresist pattern 19 is formed by a photo-lithography process after applying the photoresist to a thickness of 800 to 900nm, the inside of the contact hole 18 has a depth photolithography process It will not be removed through it.
도 1e를 참조하면, 제 2 포토레지스트 패턴(19)을 식각 마스크로 한 식각 공정으로 패시베이션 산화막(16)을 식각하여 배선이 형성될 트렌치(20)가 형성되고, 이로 인하여 콘택홀(18) 및 트렌치(20)로 이루어진 다마신 패턴(damascen pattern; 182)이 형성된다. 이후, 제 2 포토레지스트 패턴(19)을 제거한다.Referring to FIG. 1E, a trench 20 in which wirings are formed by etching the passivation oxide layer 16 is formed by an etching process using the second photoresist pattern 19 as an etching mask, thereby forming contact holes 18 and A damascene pattern 182 formed of trenches 20 is formed. Thereafter, the second photoresist pattern 19 is removed.
상기에서, 트렌치(20)를 형성하기 위한 식각 공정시 메탈 스톱 질화막(15)은 층간 절연막(14)이 식각되는 것을 방지하는 역할을 한다.In the above, the metal stop nitride layer 15 serves to prevent the interlayer insulating layer 14 from being etched during the etching process for forming the trench 20.
도 1f를 참조하면, 다마신 패턴(182)을 포함한 패시베이션 산화막(16)의 표면을 따라 루테늄 옥사이드층(RuO2layer; 21)을 형성하고, 루테늄 옥사이드층(21)이 형성된 다마신 패턴(182)이 충분히 매립되도록 루테늄층(Ru layer; 22)을 형성한다. 화학기계적 평탄화(chemical mechanical planarization; CMP) 혹은 식각 공정으로 루테늄층(22) 및 루테늄 옥사이드층(21)을 패시베이션 산화막(16)의 상단 표면이 노출될 때까지 식각하고, 이로 인하여 하부 도전층(12)과 연결된 루테늄 배선이 다마신 패턴(182) 내에 형성된다.Referring to FIG. 1F, a ruthenium oxide layer (RuO 2 layer) 21 is formed along the surface of the passivation oxide layer 16 including the damascene pattern 182, and the damascene pattern 182 on which the ruthenium oxide layer 21 is formed. Ru layer 22 is formed to sufficiently fill (). The chemical mechanical planarization (CMP) or etching process etches the ruthenium layer 22 and the ruthenium oxide layer 21 until the top surface of the passivation oxide layer 16 is exposed, thereby lowering the conductive layer 12. Ruthenium wires connected to the () are formed in the damascene pattern 182.
상기에서, 루테늄 옥사이드층(21)은 아르곤(Ar)과 산소(O2)가 혼합된 챔버에서 물리기상증착(PVD)법으로 5 내지 30nm의 두께로 형성되며, 배리어층(barrier layer) 역할을 한다. 아르곤과 산소의 혼합에서 산소의 비율은 20 내지 60%로 유지한다. 루테늄 옥사이드층(18)을 증착하기 위한 스퍼터링(sputtering)시 DC 전력(power)을 2 내지 12㎾로 한다. 루테늄층(21)은 반응 챔버의 온도를 250 내지 280 ℃로 유지하고, 반응 챔버의 압력을 0.3 내지 0.7 Torr로 유지하고, 루테늄 소오스 가스와 반응 가스를 반응 챔버에 공급하여 화학기상증착(CVD)법에 의해 형성한다.In the above, the ruthenium oxide layer 21 is formed to a thickness of 5 to 30nm by physical vapor deposition (PVD) method in a chamber in which argon (Ar) and oxygen (O 2 ) are mixed, and serves as a barrier layer. do. The proportion of oxygen in the mixture of argon and oxygen is kept at 20 to 60%. When sputtering for depositing the ruthenium oxide layer 18, the DC power is 2 to 12 kW. The ruthenium layer 21 maintains the temperature of the reaction chamber at 250 to 280 ° C., maintains the pressure of the reaction chamber at 0.3 to 0.7 Torr, and supplies ruthenium source gas and reactant gas to the reaction chamber to provide chemical vapor deposition (CVD). Form by law.
상술한 바와 같이, 본 발명은 금속배선으로 루테늄을 사용하므로, 융점이 약 1083℃인 구리(Cu)보다 높아(루테늄의 융점은 약 3210℃ 임) 고온 열안정성이 뛰어나며, 귀금속(noble metal)이라 다른 물질과 잘 반응하지 않아 전기 전도도를 그대로 유지시킬 수 있다. 또한, 본 발명은 루테늄의 산화물인 루테늄 옥사이드를 텅스텐 플러그와 루테늄층 사이에 적용하므로, 오믹 콘택(Ohmic contact)을 양호하게 유지할 수 있을 뿐만 아니라 확산 배리어층 역할을 충실히 수행할 수 있다. 더욱이, 루테늄이나 루테늄 옥사이드는 다른 귀금속과는 달리 식각이 용이하여 구조를 형성하기가 용이하여 원하는 모양의 금속배선을 형성할 수 있다.As described above, since the present invention uses ruthenium as a metal wiring, the melting point is higher than copper (Cu) having a melting point of about 1083 ° C (the melting point of ruthenium is about 3210 ° C), and is excellent in high temperature thermal stability and is called a noble metal. It does not react well with other materials and can maintain its electrical conductivity. In addition, the present invention applies ruthenium oxide, which is an oxide of ruthenium, between the tungsten plug and the ruthenium layer, thereby not only maintaining ohmic contact well but also faithfully serving as a diffusion barrier layer. Moreover, ruthenium or ruthenium oxide, unlike other precious metals, can be easily etched to form a structure, thereby forming a metal wiring of a desired shape.
Claims (7)
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| KR1020020037349A KR20040002012A (en) | 2002-06-29 | 2002-06-29 | Method of forming a metal wiring in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20180005607A (en) * | 2016-07-06 | 2018-01-16 | 도쿄엘렉트론가부시키가이샤 | Ruthenium wiring and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20180005607A (en) * | 2016-07-06 | 2018-01-16 | 도쿄엘렉트론가부시키가이샤 | Ruthenium wiring and manufacturing method thereof |
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