KR20020056009A - method for forming dual damascene of semiconductor device - Google Patents
method for forming dual damascene of semiconductor device Download PDFInfo
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- KR20020056009A KR20020056009A KR1020000085290A KR20000085290A KR20020056009A KR 20020056009 A KR20020056009 A KR 20020056009A KR 1020000085290 A KR1020000085290 A KR 1020000085290A KR 20000085290 A KR20000085290 A KR 20000085290A KR 20020056009 A KR20020056009 A KR 20020056009A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 230000009977 dual effect Effects 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 35
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 미스-얼라인을 방지하도록 하는데 적당한 반도체 소자의 이중 다마신(dual damascene) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a dual damascene of a semiconductor device suitable for preventing misalignment.
일반적으로 집적 회로의 집적도의 증가는 상호 연결(interconnection)을 형성하기 위한 칩의 표면 부족의 원인이 된다.In general, an increase in the degree of integration of integrated circuits causes a lack of surface of the chip to form interconnects.
소자의 크기가 감소함에 따라, 더 많은 배선(wiring lines) 요구를 충족시키기 위해서, 다층 상호 연결 디자인이 IC 공정에 요구된다.As the size of devices decreases, multilayer interconnect designs are required for IC processes in order to meet more wiring lines requirements.
다층 상호 연결은 3차원 배선 구조이다. 다층 상호 연결 구조를 형성하기 위해서, 반도체 기판 상의 MOS(Metal Oxide Semiconductor) 트랜지스터의 소오스/드레인 영역에 연결되는 제 1 금속 배선이 먼저 형성되고, 다음 상기 제 1 금속 배선과 연결되는 제 2 금속 배선이 형성된다. 금속 배선들은 금속 내지 폴리 실리콘 등의 도전 물질로 형성된다. 필요하다면, 두 층 이상의 금속 배선들이 형성된다.Multilayer interconnection is a three-dimensional wiring structure. In order to form a multi-layer interconnect structure, a first metal wiring connected to a source / drain region of a metal oxide semiconductor (MOS) transistor on a semiconductor substrate is first formed, and then a second metal wiring connected to the first metal wiring is formed. Is formed. The metal wires are formed of a conductive material such as metal to polysilicon. If necessary, two or more layers of metal wirings are formed.
그러나, 딥 서브 마이크론 이하의 크기를 갖는 IC 소자에 있어서, 종래 이중 다마신 기술은 만족스럽지 못하다. 예를 들어, 종래 콘택 플러그 형성을 위한 필링 물질인 구리(copper)는 에치 백 공정 동안 식각 하기가 어렵고, 또한 적절한 식각 용액(etchant)을 선택하기 어렵다.However, for IC devices having a sub submicron size, the conventional dual damascene technique is not satisfactory. For example, copper, a filling material for forming contact plugs, is difficult to etch during the etch back process, and also difficult to select an appropriate etchant.
더구나 플러그 내에 금속 증착 공정을 수행하는 동안 또는 금속 배선 사이에 절연층을 증착 하는 동안, 스텝 커버리지의 불량(poor step coverage)은 보이드(void) 형성 및 불순물 트랩핑(trapping)의 원인이 된다.Furthermore, poor step coverage during the metal deposition process in the plug or during the deposition of the insulating layer between the metal wires causes void formation and impurity trapping.
따라서, IC 소자의 축소에 따른 결함을 피하고, 또한 평탄한 절연층 표면을 형성하는 종래의 이중 다마신 기술이 제안되었다.Therefore, a conventional dual damascene technique has been proposed that avoids the defects caused by the shrinkage of the IC element and also forms a flat insulating layer surface.
가장 일반적으로 사용되는 이중 다마신 기술은 패터닝 동안 CMP(chemical mechanical polishing) 사용을 포함한다. 상기 CMP는 알루미늄, 구리, 그리고 알루미늄 합금과 같이 배선 금속의 폭 넓은 선택을 제공하고, 따라서 낮은 저항 및 낮은 전기적 이동(electro migration) 요구를 충족시키게 된다. 결과적으로, 상기 기술은 일반적으로 0.25㎛ 이하의 VLSI를 위한 공정에서 사용된다.The most commonly used dual damascene technique involves the use of chemical mechanical polishing (CMP) during patterning. The CMP provides a wide choice of wiring metals, such as aluminum, copper, and aluminum alloys, thus meeting low resistance and low electro migration requirements. As a result, the technique is generally used in processes for VLSIs of 0.25 μm or less.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 이중 다마신 형성방법을 설명하면 다음과 같다.Hereinafter, a double damascene formation method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래의 반도체 소자의 이중 다마신 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a double damascene of a conventional semiconductor device.
도 1a에 도시된 바와 같이, 반도체 기판(11)상에 산화막과 같은 절연 물질을 사용하여 층간 절연막(12)을 형성하고, 포토 및 식각공정을 통해 상기 층간 절연막(12)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(13)를 형성한다.As shown in FIG. 1A, an interlayer insulating film 12 is formed on the semiconductor substrate 11 using an insulating material such as an oxide film, and the interlayer insulating film 12 is selectively removed through photo and etching processes. A trench 13 having a depth is formed.
도 1b에 도시된 바와 같이, 포토 및 식각공정을 통해 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 상기 트랜치(13)가 형성된 층간 절연막(12)을 선택적으로 제거하여 상기 트랜치(13)보다 좁은 폭은 갖는 콘택홀(14)을 형성한다.As illustrated in FIG. 1B, the interlayer insulating layer 12 having the trench 13 may be selectively removed to expose a predetermined portion of the surface of the semiconductor substrate 11 through photo and etching processes. The narrow width forms a contact hole 14 having.
도 1c에 도시된 바와 같이, 상기 트랜치(13) 및 콘택홀(14)을 포함한 반도체 기판(11)의 전면에 금속막(15)을 증착한다.As illustrated in FIG. 1C, a metal film 15 is deposited on the entire surface of the semiconductor substrate 11 including the trench 13 and the contact hole 14.
도 1d에 도시된 바와 같이, 상기 층간 절연막(12)의 상부 표면을 앤드 포인트로 하여 상기 금속막(15)의 전면에 에치 백(etch back) 또는 CMP 공정을 실시하여 상기 트랜치(13) 및 콘택홀(14)의 내부에 금속 배선(15a)을 형성한다.As shown in FIG. 1D, the trench 13 and the contact are subjected to an etch back or CMP process on the entire surface of the metal film 15 using the upper surface of the interlayer insulating film 12 as an end point. The metal wiring 15a is formed in the hole 14.
도 2a 및 도 2b는 0.13㎛급의 고성능 반도체 소자의 금속배선 형성 공정에서 나타나는 문제점을 설명하기 위한 도면이다.2A and 2B are diagrams for explaining a problem in a metal wiring forming process of a high performance semiconductor device having a class of 0.13 µm.
즉, 도 2a에서와 같이, 0.13㎛급에서의 금속배선과 그 아래의 홀 부분의 적층은 0.01㎛이하인 부분이 디자인 룰(design rule)상 충분히 존재할 수 있으나, 노광 장비에서의 적층 능력은 0.03㎛이하로는 제어하기가 어렵고, 실제 반도체 소자의 제작 공정에 있어서는 증착막의 두께 균일도, 장비 상태에 따른 변동 범위는 0.07㎛이상이 된다.That is, as shown in Figure 2a, the metal wiring in the 0.13㎛ class and the hole portion beneath it may have a portion less than 0.01㎛ in the design rule, the stacking ability in the exposure equipment is 0.03㎛ In the following, it is difficult to control, and in the manufacturing process of the actual semiconductor device, the variation range depending on the thickness uniformity of the deposited film and the equipment state is 0.07 µm or more.
이러한 제약들은 도 1a 내지 도 1d에서와 같이 트랜치(13)를 먼저 형성하는 경우 도 2b에서와 같이 감광막(16)을 도포한 후 노광 및 현상공정을 패터닝하여 콘택 영역을 정의할 때 미스-얼라인(mis-align)이 발생하게 되고, 콘택홀을 먼저 식각 공정이나 자기 정렬 방법도 마찬가지로 후속 패터닝 공정에서 미스-얼라인이 발생한다.These constraints are misaligned when defining the contact region by applying the photoresist film 16 as shown in FIG. 2B and then patterning the exposure and development processes as shown in FIG. 2B when the trench 13 is first formed as shown in FIGS. 1A to 1D. (mis-align) occurs, and the contact hole is first etched or the self-aligned method is also mis-aligned in the subsequent patterning process.
만약, 미스-얼라인이 발생하지 않는다면 상기 감광막(16)은 점선으로 나타낸 A 부분에 콘택 영역이 정의되어야 한다.If no misalignment occurs, the contact region should be defined in the portion A of the photosensitive film 16 indicated by a dotted line.
한편, 콘택홀을 먼저 형성한 후 트랜치를 식각할 때 트랜치를 형성하기 위한 감광막 노광 후 현상 공정에서 알칼리성인 현상액에 의해 노광된 곳에서 발생한 산성의 H+가 중성(H2O)이 되면서 용해되어야 하지만 콘택홀내에 잔류하고 있던 NH+, NH2 +, NH3 +등에 의해 콘택홀의 위 부분까지 용해되지 않고 버섯 모양으로 남게 된다.On the other hand, when the contact hole is first formed and the trench is etched, the acidic H + generated at the place exposed by the alkaline developer in the post-exposure developing process for forming the trench must be dissolved while being neutral (H 2 O). However, NH + , NH 2 + , NH 3 +, etc. that remained in the contact hole do not dissolve to the upper part of the contact hole but remain in a mushroom shape.
또한, 미스-얼라인과는 달리 콘택홀을 먼저 형성한 후, 트랜치를 형성하기 위한 감광막을 패터닝할 때 콘택홀내에 채워지는 감광막이 식각에 방해를 주어서는 안되지만 콘택홀과 트랜치의 폭이 좁아서 발생되는 식각 부산물이 홀에 채워진 감광막 주위에 붙어 있게 된다.In addition, unlike the misalignment, after forming the contact hole first, when the photoresist film for forming the trench is patterned, the photoresist film filled in the contact hole should not interfere with etching, but is caused by the narrow width of the contact hole and the trench. Etch by-products stick around the photoresist in the hole.
그러나 상기와 같은 종래의 반도체 소자의 이중 다마신 형성방법에 있어서 다음과 같은 문제점이 있었다.However, there is a problem in the method of forming a double damascene of the conventional semiconductor device as described above.
즉, 트랜치를 형성한 후 콘택홀을 형성 또는 콘택홀을 형성한 후 트랜치를 형성하는 공정은 후속 식각 공정에서 미스-얼라인이 발생한다.That is, in the process of forming the trench after forming the trench or forming the trench after forming the contact hole, misalignment occurs in a subsequent etching process.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 트랜치 및 콘택홀을 형성할 때 미스-얼라인을 방지하도록 한 반도체 소자의 이중 다마신 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a double damascene of a semiconductor device to prevent misalignment when forming trenches and contact holes.
도 1a 내지 도 1d는 종래의 반도체 소자의 이중 다마신 형성방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method for forming a double damascene of a conventional semiconductor device.
도 2a 및 도 2b는 0.13㎛급의 고성능 반도체 소자의 금속배선 형성 공정에서 나타나는 문제점을 설명하기 위한 도면2A and 2B are views for explaining a problem in a metal wiring forming process of a 0.13 μm class high performance semiconductor device;
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 이중 다마신 형성방법을 나타낸 공정단면도3A to 3E are cross-sectional views illustrating a method for forming a double damascene semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 확산 방지막21 semiconductor substrate 22 diffusion barrier film
23 : TEOS막 24 : BPSG막23: TEOS film 24: BPSG film
25 : 감광막 26 : 층간 절연막25 photosensitive film 26 interlayer insulating film
27 : 콘택홀 28 : 트랜치27: contact hole 28: trench
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 이중 다마신 형성방법은 구리 배선이 형성된 반도체 기판상에 확산 방지막을 형성하는 단계와, 상기 확산 방지막상에 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막상에 제 1 절연막보다 선택비가 높은 제 2 절연막을 형성하는 단계와, 상기 제 2 절연막상에 감광막을 도포한 후 패터닝하여 콘택 영역을 정의하는 단계와, 상기 패터닝된 감광막을 마스크로 이용하여 제 2, 제 1 절연막을 건식 식각으로 1차 식각하고 습식 식각으로 2차 식각하는 단계와, 상기 감광막을 제거하는 단계와, 상기 제 2 절연막의 상부 표면 높이로 반도체 기판의 전면에 층간 절연막을 형성하는 단계와, 상기 제 1, 제 2 절연막을 제거하여 콘택홀 및 트랜치를 동시에 형성하는 단계와, 상기 콘택홀 저면의 확산 방지막을 선택적으로 제거하는 단계를 포함하여 형성함을 특징으로 한다.The method for forming a double damascene of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a diffusion barrier on a semiconductor substrate on which copper wiring is formed, and forming a first insulating film on the diffusion barrier; Forming a second insulating film having a higher selectivity than the first insulating film on the first insulating film, applying and patterning the photosensitive film on the second insulating film, and defining a contact region, and masking the patterned photosensitive film. First etching the second and first insulating layers by dry etching and second etching by wet etching, removing the photoresist layer, and forming an interlayer on the front surface of the semiconductor substrate at an upper surface height of the second insulating layer. Forming an insulating film, removing the first and second insulating films at the same time, forming a contact hole and a trench, and forming a diffusion chamber at the bottom of the contact hole. Including the step of selectively removing the film is characterized in that it is formed.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 이중 다마신 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming double damascene of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 이중 다마신 형성방법을 나타낸 공정단면도이다.3A to 3E are cross-sectional views illustrating a method for forming double damascene of a semiconductor device according to the present invention.
도 3a에 도시한 바와 같이, 구리(Cu) 배선(도시되지 않음)이 형성된 반도체 기판(21)의 전면에 확산 방지막(22)을 형성하고, 상기 확산 방지막(22)상에 서로 선택비가 다른 절연막으로 TEOS(Tetra Ethyl Ortho Silicate)막(23)과 BPSG(Boron Phosphorus Silicate Glass)막(24)을 차례로 형성한다.As shown in FIG. 3A, a diffusion barrier 22 is formed over the entire surface of the semiconductor substrate 21 on which copper (Cu) wiring (not shown) is formed, and the insulation barriers having different selectivities on the diffusion barrier 22 are different. As a result, a TEOS (Tetra Ethyl Ortho Silicate) film 23 and a BPSG (Boron Phosphorus Silicate Glass) film 24 are sequentially formed.
여기서 상기 TEOS막(23)과 BPSG막(24)은 HF 또는 9:1 BOE에서 10:1 정도의 선택비를 갖는다.The TEOS film 23 and the BPSG film 24 have a selectivity of about 10: 1 in HF or 9: 1 BOE.
한편, 식각 속도가 빠른 TEOS막(23)은 약 8000Å 정도로 형성하고, 식각 속도가 느린 BPSG막(24)은 약 5000Å 정도로 형성한다.On the other hand, the TEOS film 23 having a high etching speed is formed at about 8000 GPa, and the BPSG film 24 having a slow etching speed is formed at about 5000 GPa.
도 3b에 도시한 바와 같이, 상기 BPSG막(24)상에 감광막(25)을 도포한 후, 노광 및 현상 공정으로 감광막(25)을 패터닝하여 콘택 영역을 정의한다.As shown in FIG. 3B, after the photoresist 25 is applied onto the BPSG film 24, the photoresist 25 is patterned by an exposure and development process to define a contact region.
도 3c에 도시한 바와 같이, 상기 패터닝된 감광막(25)을 마스크로 이용하여상기 BPSG막(24)과 TEOS막(23)을 건식 식각(dry etch)하여 1차로 식각하고, 계속해서 습식 식각하여 2차로 식각한다.As shown in FIG. 3C, the BPSG film 24 and the TEOS film 23 are dry etched by dry etching using the patterned photosensitive film 25 as a mask, followed by wet etching. Etch second.
여기서 상기 BPSG막(24)과 TEOS막(23)을 건식 식각과 습식 식각으로 식각할 때 BPSG막(24)보다 식각 속도가 빠른 TEOS막(23)은 습식 식각시 빠르게 식각되어 잔류한 BPSG막(24)과 TEOS막(23)이 "T" 자 형태를 갖게 된다.Here, when the BPSG film 24 and the TEOS film 23 are etched by dry etching and wet etching, the TEOS film 23 having a faster etching rate than the BPSG film 24 is rapidly etched and wetted by the wet BPSG film ( 24 and the TEOS film 23 have a "T" shape.
도 3d에 도시한 바와 같이, 상기 감광막(25)을 제거하고, 상기 "T"자 형태를 갖는 BPSG막(24) 및 TEOS막(23)을 포함한 반도체 기판(21)의 전면에 유기 화학적 층간 절연막(26)의 회전 코팅하여 형성한다.As shown in FIG. 3D, the photosensitive film 25 is removed and an organic chemical interlayer insulating film is formed on the entire surface of the semiconductor substrate 21 including the BPSG film 24 and the TEOS film 23 having the "T" shape. It is formed by rotating coating (26).
한편, 상기 층간 절연막(26)을 형성할 때 그 하부의 BPSG막(24) 및 TEOS막(23)에 가해지는 기계적 응력으로 인한 패턴 무너짐을 방지하기 위하여 층간 절연막(26)의 점도를 의도적으로 낮추어서 응력을 감소시키어 형성한다.Meanwhile, when the interlayer insulating layer 26 is formed, the viscosity of the interlayer insulating layer 26 is intentionally lowered to prevent the pattern from being collapsed due to the mechanical stress applied to the lower BPSG film 24 and the TEOS film 23. Form by reducing stress.
이어, 상기 BPSG막(24)의 상부 표면이 노출되도록 CMP 공정을 통해 연마 공정을 실시한다.Subsequently, a polishing process is performed through the CMP process so that the upper surface of the BPSG film 24 is exposed.
여기서 상기 층간 절연막(26)을 회전 코팅하지 않고 HSQ(Hydrogen Silsequioxane) 등과 같이 회전 코팅할 수 있는 실리카를 사용할 수 있다.Here, silica that can be spin-coated, such as HSQ (Hydrogen Silsequioxane), may be used without spin-coating the interlayer insulating layer 26.
도 3e에 도시한 바와 같이, 상기 BPSG막(24) 및 TEOS막(23)을 습식 식각으로 제거하여 콘택홀(27)과 트랜치(28)를 동시에 형성한다.As shown in FIG. 3E, the BPSG layer 24 and the TEOS layer 23 are removed by wet etching to simultaneously form the contact hole 27 and the trench 28.
이어, 상기 콘택홀(27)의 저면에 형성된 확산 방지막(22)을 건식 식각으로 제거하여 상기 반도체 기판(21)상에 형성된 구리 배선의 표면이 노출시킨다.Next, the diffusion barrier 22 formed on the bottom surface of the contact hole 27 is removed by dry etching to expose the surface of the copper wiring formed on the semiconductor substrate 21.
그리고 이후 공정은 도면에 도시하지 않았지만 상기 콘택홀(27) 및트랜치(28)을 포함한 전면에 금속막을 증착한 후 에치 백 또는 CMP 공정을 실시하여 금속배선을 형성한다.Although a subsequent process is not shown in the figure, a metal film is deposited on the entire surface including the contact hole 27 and the trench 28, and then an etch back or CMP process is performed to form a metal wiring.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 이중 다마신 형성방법은 다음과 같은 효과가 있다.As described above, the method of forming double damascene of the semiconductor device according to the present invention has the following effects.
즉, 서로 다른 선택비를 갖는 두 층의 절연막을 형성한 후 건식 식각과 습식 식각을 병행하여 두 층의 절연막을 선택적으로 제거하고, 전면에 유기 화학적 층간 절연막을 형성한 후에 두 층의 절연막을 제거하여 콘택홀과 트랜치를 동시에 형성함으로서 미스-얼라인의 발생이 없는 자기 정렬 층간 절연막을 형성할 수 있다.That is, after forming two layers of insulating films having different selectivity ratios, the two layers of insulating films are selectively removed by dry etching and wet etching, and the organic chemical interlayer insulating film is formed on the entire surface, and then the two layers of insulating films are removed. By forming contact holes and trenches at the same time, a self-aligned interlayer insulating film can be formed without occurrence of misalignment.
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