KR100436131B1 - Method of forming fine pattern of semiconductor device using hemispherical polycrystalline silicon layer as anti-reflective coating and etching mask - Google Patents

Abstract

PURPOSE: A method is provided to form stably a fine pattern without notching by using a hemispherical polycrystalline silicon layer as an anti-reflective coating and an etching mask. CONSTITUTION: A predetermined layer is formed on a semiconductor substrate(11) with a stepped portion. A hemispherical conductive layer(21) is formed on the predetermined layer by using a CVD(Chemical Vapor Deposition) at a temperature of 100 to 700 . A hemispherical conductive pattern is formed by patterning selectively the hemispherical conductive layer using a photoresist pattern(23) as an etching mask. At this time, the hemispherical conductive pattern is used as an anti-reflective coating. A fine pattern is formed by etching selectively the predetermined layer using the hemispherical conductive pattern as an etching mask. The hemispherical conductive pattern is removed therefrom. The hemispherical conductive layer is a hemispherical polycrystalline silicon layer. The thickness of the hemispherical conductive layer is within 100 to 1000 angstrom.

Description

Micro pattern formation method of semiconductor device

The present invention relates to a method for forming a micropattern of a semiconductor device, and in particular, to prevent damage and loss of a pattern due to a notching phenomenon that may occur when a micropattern is formed on a surface having a step, thereby improving yield and productivity of the semiconductor device. It is about a technology that can be improved.

As semiconductor devices have been highly integrated, a pattern having a smaller width on a semiconductor substrate is required.

However, in the case of forming the micropattern, the photoresist pattern for forming the micropattern may be damaged or lost due to the reflection of the light source generated by the inclined surface of the boundary between the high and low steps, thereby reducing the yield of the semiconductor device. .

In order to solve this problem, the prior art has flattened the upper surface and performed a patterning process or an antireflection film was used to prevent the occurrence of a hardening phenomenon. In addition, damage to the photoresist pattern by the light source was prevented by using the dried photoresist.

However, the patterning process after the planarization process raises the process cost and lowers the stability of the process.

In the case of using the dried photosensitive film, the resolution of the pattern is reduced and the process margin is reduced.

On the other hand, in the case of using the anti-reflection film, there is a case of using an inorganic anti-reflection film, a case of using an anti-reflection film on the top of the photoresist film, and a case of using an anti-reflection film on the bottom of the photoresist film.

However, when the inorganic antireflection film is used, the process cost is increased because of contamination by metal ions and complicated processes. In the case where the anti-reflection film is used on the upper portion, the CD swing is improved but not the curing phenomenon. In addition, in the case where the anti-reflection film is used in the lower portion, additional equipment introduction is required and the productivity of the semiconductor device is reduced.

1 is a cross-sectional view illustrating a method for forming a fine pattern of a semiconductor device according to the prior art, and illustrates a word line forming process as an example.

Referring to FIG. 1, a device isolation insulating film 53 is formed on a semiconductor substrate 51, and a polycrystalline silicon film 55, a tungsten silicide 57, and a tetra-ethic ortho silicate (hereinafter, TeS) are formed on the entire surface. Each oxide film 59 is formed to have a predetermined thickness.

The photoresist pattern 61 is formed on the theos oxide layer 59. In this case, the photoresist pattern 61 is formed by an exposure and development process using a word line mask (not shown).

In this case, the arrow of FIG. 1 shows the entry path of the light source.

As described above, in the method of forming a micropattern of a semiconductor device according to the prior art, a light source reflected on an inclined surface exposes a predetermined photoresist pattern and is developed during a subsequent development process to form a damaged photoresist pattern or a photoresist pattern is lost. There is a problem in that the yield is lowered, thereby lowering the productivity of the semiconductor device, thereby making it difficult to integrate the semiconductor device.

The present invention forms a hemispherical polysilicon film on the etched layer to be used as an antireflection film, and forms a etched layer pattern using the hemispherical polysilicon film as a mask to form a stable photoresist pattern. Accordingly, an object of the present invention is to provide a method of forming a fine pattern of a semiconductor device, which improves the yield and productivity of the semiconductor device and thereby enables high integration of the semiconductor device.

1 is a cross-sectional view showing a method for forming a fine pattern of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11,31,51: semiconductor substrate 13,33,53: device isolation insulating film

15,35,55 polysilicon film 17,37,57 tungsten silicide

19,41,59: TEOS oxide film 21,39: hemispherical polysilicon film

23,43,61: Photoresist pattern

In order to achieve the above object, the method of forming a fine pattern of a semiconductor device according to the present invention,

Forming an etching target layer on the semiconductor substrate having a step difference;

Forming a hemispherical conductive layer on the etched layer at a temperature of 100 to 700 캜 by CVD;

Patterning the hemispherical conductive layer to form a hemispherical conductive layer pattern;

Etching the etched layer using the hemispherical conductive layer pattern as a mask to form a fine pattern;

A first feature is to include a step of removing the hemispherical conductive layer pattern.

In addition, in order to achieve the above object, the method of forming a fine pattern of a semiconductor device according to the present invention,

Forming a first etching layer on the semiconductor substrate having a step;

Forming a hemispherical conductive layer on the first etched layer;

Forming a second etching layer on the hemispherical conductive layer;

Forming a photoresist pattern on the etched layer;

Patterning a second etched layer using the hemispherical conductive layer as an antireflection film;

Etching the hemispherical conductive layer and the first etched layer using the photosensitive film pattern as a mask, respectively;

It is a 2nd characteristic that it includes the process of removing the said photosensitive film pattern.

The principle of the present invention for achieving the above object, by forming a hemispherical polysilicon film on the etched layer and a photosensitive film pattern on the upper part to disperse the reflection of the light source during the exposure process to the hemispherical polysilicon film is generated during the exposure process Forming a photoresist pattern of a predetermined size by suppressing a hardening phenomenon, patterning the hemispherical polysilicon film using the photoresist pattern as a mask in a subsequent step, removing the photoresist pattern, and then etching the patterned hemispherical polysilicon film as a mask By patterning this, a stable fine pattern is formed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention, and show word lines as an example.

First, a device isolation insulating film 13 is formed on the semiconductor substrate 11. The polysilicon film 15, the tungsten silicide 17, and the TEOS oxide film 19 are sequentially formed on the semiconductor substrate 11 in predetermined order.

Next, a hemispherical polysilicon film 21 is formed on the TEOS oxide film 19 at a predetermined thickness.

At this time, the hemispherical polysilicon film 21 is formed to a thickness of 100 to 1000 kPa by chemical vapor deposition (CVD) at a temperature of about 100 ~ 700 ℃.

Next, a photosensitive film pattern 23 is formed on the hemispherical polysilicon film 21.

In this case, the photoresist pattern 23 is formed by an exposure and development process using a word line mask (not shown).

Here, the photosensitive film pattern 23 weakens the light intensity by being diffusely reflected from the inclined surface of the substrate by the hemispherical polysilicon film 21 during the exposure process, and the knocking phenomenon that one side of the photosensitive film pattern 23 is damaged during the development process. Can be suppressed. (FIG. 2A)

Next, the hemispherical polysilicon layer 21 is etched using the photosensitive film pattern 23 as a mask to form a hemispherical polysilicon layer 21 pattern.

At this time, the etching process of the hemispherical polysilicon film 21 is performed by a dry method, source power (1000-2000 watts), bias power (bias power) 0-1000 watts, pressure 10-100 mTorr and the temperature of the board | substrate are performed on 10-30 degreeC. (FIG. 2B)

Next, the photoresist pattern 21 is removed. At this time, the photosensitive film pattern 23 is implemented in the prior art, such as using an oxygen plasma. (FIG. 2C)

The TEOS oxide film 19 is dry-etched using the hemispherical polysilicon film 21 pattern as a mask. (FIG. 2D)

Next, using the hemispherical polysilicon layer 21 as a mask, the tungsten silicide 17 and the polysilicon layer 15 are continuously etched following the process of FIG. 2D, and the hemispherical polysilicon layer 21 By removing the pattern, a fine pattern for a word line formed of a laminated structure of the polysilicon film 15, the tungsten silicide 17, and the TEOS oxide film 19 is formed. (FIG. 2E)

3 is a cross-sectional view illustrating a method of forming a fine pattern of a semiconductor device in accordance with another embodiment of the present invention, and illustrates word lines as an example.

First, an isolation layer 33 is formed on the semiconductor substrate 31. A polysilicon film 35, a tungsten silicide 37, a hemispherical polysilicon film 39, and a TEOS oxide film 41 are sequentially formed on the semiconductor substrate 31, respectively.

The photoresist pattern 43 is formed on the TEOS oxide layer 41.

In this case, the photoresist pattern 43 is formed by an exposure and development process using a word line mask (not shown). (Figure 3)

As described above, in the method of forming a micropattern of a semiconductor device according to the present invention, a semispherical polysilicon film is formed on and in the middle of an etched layer, and a etched layer pattern is formed using the same to form a stable fine pattern without the occurrence of a knocking phenomenon. There is an advantage to improve the yield and productivity of the semiconductor device and thereby high integration of the semiconductor device.

Claims (9)

Forming an etching target layer on the semiconductor substrate having a step difference; Forming a hemispherical conductive layer on the etched layer by a CVD method at a temperature of 100 to 700 ° C., Patterning the hemispherical conductive layer to form a hemispherical conductive layer pattern; Etching the etched layer using the hemispherical conductive layer pattern as a mask to form a fine pattern; The method of forming a fine pattern of a semiconductor device comprising the step of removing the hemispherical conductive layer pattern. The method according to claim 1, And said hemispherical conductive layer is a hemispherical polysilicon film. The method according to claim 1, Said hemispherical conductive layer is formed in the thickness of 100-1000 micrometers, The fine pattern formation method of the semiconductor element characterized by the above-mentioned. The method according to claim 1, The patterning of the hemispherical conductive layer is performed by a process of forming a photoresist pattern by an exposure and development process using an exposure mask and dry etching the hemispherical conductive layer using the photoresist pattern as a mask. Formation method. The method according to claim 1, Patterning process of the hemispherical conductive layer is carried out under the conditions of source power of 1000 to 2000 watts, bias power of 0 to 1000 watts, pressure of 10 to 100 mTorr and substrate temperature of 10 to 30 ℃ Pattern formation method. The method according to claim 1, The etching process of the etched layer is a method of forming a fine pattern of a semiconductor device, characterized in that performed by a dry method. Forming a first etching layer on the semiconductor substrate having a step; Forming a hemispherical conductive layer on the first etched layer; Forming a second etching layer on the hemispherical conductive layer; Forming a photoresist pattern on the etched layer; Patterning a second etched layer using the hemispherical conductive layer as an antireflection film; Etching the hemispherical conductive layer and the first etched layer using the photoresist pattern as a mask, respectively; The method of forming a fine pattern of a semiconductor device comprising the step of removing the photosensitive film pattern. The method according to claim 7, The hemispherical conductive layer is a fine pattern forming method of a semiconductor device, characterized in that for forming a hemispherical polysilicon film having a thickness of about 100 ~ 1000 에서 at a temperature of about 100 ~ 700 ℃ by CVD method. The method according to claim 7, The patterning process of the hemispherical conductive layer is carried out under the conditions of source power of 1000 to 2000 watts, bias power of 0 to 1000 watts, pressure of 10 to 100 mTorr, and substrate temperature of 10 to 30 ° C. Pattern formation method.